Searched full:lpddr2 (Results 1 – 8 of 8) sorted by relevance
| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr2.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
23 - jedec,lpddr2-nvm
24 - jedec,lpddr2-s2
25 - jedec,lpddr2-s4
27 - pattern: "^lpddr2-[0-9a-f]{2},[0-9a-f]{4}$"
29 - jedec,lpddr2-nvm
30 - jedec,lpddr2-s2
31 - jedec,lpddr2-s4
128 "^lpddr2-timings":
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| D | jedec,lpddr2-timings.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
14 const: jedec,lpddr2-timings
117 compatible = "jedec,lpddr2-timings";
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| D | jedec,lpddr-channel.yaml | 21 - jedec,lpddr2-channel
67 const: jedec,lpddr2-channel
71 $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra20-emc.yaml | 19 standard protocols: DDR1, LPDDR2 and DDR2.
167 lpddr2:
168 $ref: ddr/jedec,lpddr2.yaml#
180 - lpddr2
242 lpddr2 {
243 compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
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| D | nvidia,tegra30-mc.yaml | 34 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
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| D | nvidia,tegra30-emc.yaml | 18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
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| /Documentation/driver-api/memory-devices/ |
| D | ti-emif.rst | 30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
31 This driver takes care of only LPDDR2 memories presently. The
63 - mr4 : last polled value of MR4 register in the LPDDR2 device. MR4
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| /Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 5 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
24 - device-handle : phandle to a "lpddr2" node representing the memory part
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