Searched +full:map +full:- +full:to +full:- +full:dma +full:- +full:channel (Results 1 – 25 of 34) sorted by relevance
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| /Documentation/devicetree/bindings/dma/ |
| D | ti-edma.txt | 3 The eDMA3 consists of two components: Channel controller (CC) and Transfer
4 Controller(s) (TC). The CC is the main entry for DMA users since it is
5 responsible for the DMA channel handling, while the TCs are responsible to
6 execute the actual DMA tansfer.
8 ------------------------------------------------------------------------------
9 eDMA3 Channel Controller
12 --------------------
13 - compatible: Should be:
14 - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
16 - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
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| D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
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| D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
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| /Documentation/devicetree/bindings/dma/ti/ |
| D | k3-bcdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-bcdma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
15 The Block Copy DMA (BCDMA) is intended to perform similar functions as the TR
16 mode channels of K3 UDMA-P.
19 Block copy channels mainly used for memory to memory transfers, but with
20 optional triggers a block copy channel can service peripherals by accessing
21 directly to memory mapped registers or area.
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| D | k3-udma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 title: Texas Instruments K3 NAVSS Unified DMA
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
15 The UDMA-P is intended to perform similar (but significantly upgraded)
16 functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
18 The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
19 data structure compliant packets to/from smaller data blocks that are natively
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| D | k3-pktdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
15 The Packet DMA (PKTDMA) is intended to perform similar functions as the packet
16 mode channels of K3 UDMA-P.
17 PKTDMA only includes Split channels to service PSI-L based peripherals.
19 The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
20 with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
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| /Documentation/devicetree/bindings/dma/xilinx/ |
| D | xlnx,zynqmp-dma-1.0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
11 memory to device and device to memory transfers. It also has flow
12 control and rate control support for slave/peripheral dma access.
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
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| /Documentation/devicetree/bindings/net/ |
| D | ibm,emac.txt | 4 the Axon bridge. To operate this needs to interact with a this
5 special McMAL DMA controller, and sometimes an RGMII or ZMII
6 interface. In addition to the nodes and properties described
8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
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| D | intel,dwmac-plat.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
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| D | fsl,fman.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
23 Frame Processing Manager memory map (0xc3000 from the
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
32 FMan unit in the SoC memory map. In the table below,
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| D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
23 - snps,dwmac
24 - snps,dwmac-3.40a
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| /Documentation/devicetree/bindings/dsp/ |
| D | fsl,dsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
11 - Shengjiu Wang <shengjiu.wang@nxp.com>
15 advanced pre- and post- audio processing.
20 - fsl,imx8qxp-dsp
21 - fsl,imx8qm-dsp
22 - fsl,imx8mp-dsp
23 - fsl,imx8ulp-dsp
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| /Documentation/devicetree/bindings/firmware/ |
| D | intel,stratix10-svc.txt | 3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
5 configured from HPS, there needs to be a way for HPS to notify SDM the
9 To meet the whole system security needs and support virtual machine requesting
12 exception layers must channel through the EL3 software whenever it needs
18 driver also manages secure monitor call (SMC) to communicate with secure monitor
22 -------------------
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc
28 smc - Secure Monitor Call
29 hvc - Hypervisor Call
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| /Documentation/devicetree/bindings/spi/ |
| D | snps,dw-apb-ssi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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| /Documentation/arch/arm/keystone/ |
| D | knav-qmss.rst | 11 multi-core Navigator. QMSS consist of queue managers, packed-data structure
13 Packet DMA.
15 management of the packet queues. Packets are queued/de-queued by writing or
16 reading descriptor address to a particular memory mapped location. The PDSPs
18 Linking RAM registers are used to link the descriptors which are stored in
24 knav qmss driver provides a set of APIs to drivers to open/close qmss queues,
25 allocate descriptor pools, map the descriptors, push/pop to queues etc. For
26 details of the available APIs, please refers to include/linux/soc/ti/knav_qmss.h
29 Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
33 The QMSS PDSP firmware support accumulator channel that can monitor a single
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| /Documentation/virt/hyperv/ |
| D | vpci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 PCI pass-thru devices
5 In a Hyper-V guest VM, PCI pass-thru devices (also called
10 provides higher bandwidth access to the device with lower
12 hypervisor. The device should appear to the guest just as it
14 to the Linux device drivers for the device.
16 Hyper-V terminology for vPCI devices is "Discrete Device
17 Assignment" (DDA). Public documentation for Hyper-V DDA is
20 …tps://learn.microsoft.com/en-us/windows-server/virtualization/hyper-v/plan/plan-for-deploying-devi…
23 and for GPUs. A similar mechanism for NICs is called SR-IOV
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| /Documentation/driver-api/ |
| D | vme.rst | 5 -------------------
9 achieved via a call to :c:func:`vme_register_driver`.
11 A pointer to a structure of type :c:type:`struct vme_driver <vme_driver>` must
12 be provided to the registration function. Along with the maximum number of
13 devices your driver is able to support.
17 element is a pointer to a string holding the device driver's name.
22 the number of devices probed to one:
24 .. code-block:: c
30 if (vdev->id.num >= USER_BUS_MAX)
35 The '.probe' element should contain a pointer to the probe routine. The
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| D | scsi.rst | 12 ---------------
15 parallel I/O bus and a data protocol to connect a wide variety of
17 optical drives, test equipment, and medical devices) to a host computer.
20 out of use, the SCSI command set is more widely used than ever to
23 The `SCSI protocol <https://www.t10.org/scsi-3.htm>`__ is a big-endian
24 peer-to-peer packet based protocol. SCSI commands are 6, 10, 12, or 16
28 are the default protocol for storage devices attached to USB, SATA, SAS,
29 Fibre Channel, FireWire, and ATAPI devices. SCSI packets are also
35 ----------------------------------
46 In between is the SCSI mid-layer, analogous to a network routing layer
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| D | uio-howto.rst | 5 :Author: Hans-Jürgen Koch Linux developer, Linutronix
6 :Date: 2006-12-11
12 ------------
18 -------
21 All that is really needed is some way to handle an interrupt and provide
22 access to the memory space of the device. The logic of controlling the
23 device does not necessarily have to be within the kernel, as the device
24 does not need to take advantage of any of other resources that the
28 To address this situation, the userspace I/O system (UIO) was designed.
39 - The device has memory that can be mapped. The device can be
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| /Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| /Documentation/networking/device_drivers/ethernet/stmicro/ |
| D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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| /Documentation/networking/device_drivers/ethernet/marvell/ |
| D | octeontx2.rst | 1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
12 - `Overview`_
13 - `Drivers`_
14 - `Basic packet flow`_
15 - `Devlink health reporters`_
16 - `Quality of service`_
23 PCI-compatible physical and virtual functions. Each functional block
24 again has multiple local functions (LFs) for provisioning to PCI devices.
27 and has privileges to provision RVU functional block's LFs to each of the
31 - Network pool or buffer allocator (NPA)
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 4 By default, unaccepted memory is accepted lazily to
9 accept_memory=eager can be used to accept all memory
16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
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| /Documentation/firmware-guide/acpi/ |
| D | enumeration.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 In addition we are starting to see peripherals integrated in the
12 SoC/Chipset to appear only in ACPI namespace. These are typically devices
13 that are accessed through memory-mapped registers.
15 In order to support this and re-use the existing drivers as much as
16 possible we decided to do following:
18 - Devices that have no bus connector resource are represented as
21 - Devices behind real busses where there is a connector resource
32 to their ACPI handle in the ACPI namespace.
34 This means that when ACPI_HANDLE(dev) returns non-NULL the device was
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| /Documentation/admin-guide/media/ |
| D | vivid.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 Up to 64 vivid instances can be created, each with up to 16 inputs and 16 outputs.
13 Each input can be a webcam, TV capture device, S-Video capture device or an HDMI
14 capture device. Each output can be an S-Video output device or an HDMI output
18 allows you to use this driver as a test input for application development, since
23 - Support for read()/write(), MMAP, USERPTR and DMABUF streaming I/O.
24 - A large list of test patterns and variations thereof
25 - Working brightness, contrast, saturation and hue controls
26 - Support for the alpha color component
27 - Full colorspace support, including limited/full RGB range
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