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/Documentation/devicetree/bindings/mtd/
Dnand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip Common Properties
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
16 This file covers the generic description of a NAND chip. It implies that the
17 bus interface should not be taken into account: both raw NAND devices and
18 SPI-NAND devices are concerned by this description.
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/Documentation/driver-api/mtd/
Dnand_ecc.rst2 NAND Error-correction Code
8 Having looked at the linux mtd/nand Hamming software ECC engine driver
11 After that the speed was increased by 35-40%.
22 NAND flash (at least SLC one) typically has sectors of 256 bytes.
23 However NAND flash is not extremely reliable so some error detection
31 As I said before the ecc calculation is performed on sectors of 256
41 Back to ecc.
63 - cp0 is the parity that belongs to all bit0, bit2, bit4, bit6.
69 - cp2 is the parity over bit0, bit1, bit4 and bit5
70 - cp3 is the parity over bit2, bit3, bit6 and bit7.
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