Searched +full:non +full:- +full:programmable (Results 1 – 25 of 36) sorted by relevance
12
| /Documentation/devicetree/bindings/display/bridge/ |
| D | simple-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/simple-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Transparent non-programmable DRM bridges
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11 - Maxime Ripard <mripard@kernel.org>
14 This binding supports transparent non-programmable bridges that don't require
20 - items:
21 - enum:
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| D | adi,adv7533.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 - $ref: /schemas/sound/dai-common.yaml#
23 - adi,adv7533
24 - adi,adv7535
38 reg-names:
40 Names of maps with programmable addresses. It can contain any map
41 needing a non-default address.
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| D | adi,adv7511.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
21 - adi,adv7511
22 - adi,adv7511w
23 - adi,adv7513
37 reg-names:
39 Names of maps with programmable addresses. It can contain any map
40 needing a non-default address.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | opencores,or1k-pic.txt | 1 OpenRISC 1000 Programmable Interrupt Controller
5 - compatible : should be "opencores,or1k-pic-level" for variants with
6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
7 edge triggered interrupt lines or "opencores,or1200-pic" for machines
8 with the non-spec compliant or1200 type implementation.
10 "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
19 intc: interrupt-controller {
20 compatible = "opencores,or1k-pic-level";
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| /Documentation/devicetree/bindings/fuse/ |
| D | renesas,rcar-otp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fuse/renesas,rcar-otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: R-Car E-FUSE connected to OTP_MEM
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The E-FUSE is a type of non-volatile memory, which is accessible through the
14 One-Time Programmable Memory (OTP_MEM) module on some R-Car Gen4 SoCs.
19 - renesas,r8a779g0-otp # R-CarV4H
20 - renesas,r8a779h0-otp # R-CarV4M
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | aspeed,ast2600-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/aspeed,ast2600-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Billy Tsai <billy_tsai@aspeedtech.com>
13 • 10-bits resolution for 16 voltage channels.
16 • Channel scanning can be non-continuous.
17 • Programmable ADC clock frequency.
18 • Programmable upper and lower threshold for each channels.
21 • Built-in a compensating method.
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| /Documentation/devicetree/bindings/display/xlnx/ |
| D | xlnx,zynqmp-dpsub.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
18 - clock-lanes: should be <0>
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-cti.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
25 programmable channels, usually 4, but again implementation defined and
28 programmable.
37 indicate this feature (arm,coresight-cti-v8-arch).
52 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
59 Note that some hardware trigger signals can be connected to non-CoreSight
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| /Documentation/devicetree/bindings/clock/ |
| D | ti,cdce925.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI CDCE913/925/937/949 programmable I2C clock synthesizers
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
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| /Documentation/hwmon/ |
| D | nct6775.rst | 19 * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
83 * Nuvoton NCT6796D-S/NCT6799D-R
93 Guenter Roeck <linux@roeck-us.net>
96 -----------
120 triggered if the rotation speed has dropped below a programmable limit. On
121 NCT6775F, fan readings can be divided by a programmable divider (1, 2, 4, 8,
130 An alarm is triggered if the voltage has crossed a programmable minimum
138 The mode works for fan1-fan5.
141 ----------------
143 pwm[1-7]
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| D | pc87360.rst | 22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
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| D | adm1026.rst | 16 - Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing
17 - Justin Thiessen <jthiessen@penguincomputing.com>
20 -----------------
23 List of GPIO pins (0-16) to program as inputs
26 List of GPIO pins (0-16) to program as outputs
29 List of GPIO pins (0-16) to program as inverted
32 List of GPIO pins (0-16) to program as normal/non-inverted
35 List of GPIO pins (0-7) to program as fan tachs
39 -----------
45 16 general purpose digital I/O lines, eight (8) fan speed sensors (8-bit),
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| /Documentation/misc-devices/ |
| D | xilinx_sdfec.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 Xilinx SD-FEC Driver
10 This driver supports SD-FEC Integrated Block for Zynq |Ultrascale+ (TM)| RFSoCs.
15 …f SD-FEC core features, see the `SD-FEC Product Guide (PG256) <https://www.xilinx.com/cgi-bin/docs…
19 - Retrieval of the Integrated Block configuration and status information
20 - Configuration of LDPC codes
21 - Configuration of Turbo decoding
22 - Monitoring errors
24 Missing features, known issues, and limitations of the SD-FEC driver are as
27 - Only allows a single open file handler to any instance of the driver at any time
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| D | oxsemi-tornado.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 value from 1 to 63.875 in increments of 0.125, and then the usual 16-bit
14 value from 1 to 65535. Finally a programmable oversampling rate is used
21 for the usual 16-bit divisor is 115313.653, which is close enough to the
38 obtained, with either exact or highly-accurate actual bit rates for
39 standard and many non-standard rates.
41 Here are the figures for the standard and some non-standard baud rates
56 r: 3686400, a: 3676470.59, d: -0.2694%, tcr: 8, cpr: 2.125, div: 1
57 r: 3500000, a: 3496503.50, d: -0.0999%, tcr: 13, cpr: 1.375, div: 1
58 r: 3000000, a: 2976190.48, d: -0.7937%, tcr: 14, cpr: 1.500, div: 1
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| /Documentation/admin-guide/ |
| D | rtc.rst | 8 the local time zone or daylight savings time -- unless they dual boot
9 with MS-Windows -- but will instead be set to Coordinated Universal Time
12 The newest non-PC hardware tends to just count seconds, like the time(2)
16 Linux has two largely-compatible userspace RTC API families you may
20 so it's not very portable to non-x86 systems.
35 Old PC/AT-Compatible driver: /dev/rtc
36 --------------------------------------
44 a few ways (enabling longer alarm periods, and wake-from-hibernate).
52 subset of the three programmable values, meaning that it could be set to
59 the type of interrupt (update-done, alarm-rang, or periodic) that was
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| /Documentation/driver-api/gpio/ |
| D | intro.rst | 17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
27 several dozen of them. Programmable logic devices (like FPGAs) can easily
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
44 input de-glitch/debounce logic, sometimes with software controls.
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| /Documentation/fb/ |
| D | api.rst | 9 ---------------
12 with frame buffer devices. In-kernel APIs between device drivers and the frame
22 ---------------
36 - FB_CAP_FOURCC
44 --------------------
46 Pixels are stored in memory in hardware-dependent formats. Applications need
58 - FB_TYPE_PACKED_PIXELS
67 - FB_TYPE_PLANES
75 - FB_TYPE_INTERLEAVED_PLANES
86 - FB_TYPE_FOURCC
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| /Documentation/driver-api/ |
| D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
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| /Documentation/trace/coresight/ |
| D | coresight-ect.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
50 The hardware trigger signals can also be connected to non-CoreSight devices
60 ---------------------------
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-counter | 3 Contact: linux-iio@vger.kernel.org
11 Contact: linux-iio@vger.kernel.org
16 MTCLKA-MTCLKB:
20 MTCLKC-MTCLKD:
26 Contact: linux-iio@vger.kernel.org
33 Contact: linux-iio@vger.kernel.org
39 Contact: linux-iio@vger.kernel.org
45 Contact: linux-iio@vger.kernel.org
52 Contact: linux-iio@vger.kernel.org
59 Contact: linux-iio@vger.kernel.org
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| /Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
44 One of the first timer devices available is the programmable interrupt timer,
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
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| /Documentation/arch/arm64/ |
| D | arm-acpi.rst | 23 industry-standard Arm systems, they also apply to more than one operating
25 ACPI and Linux only, on an Arm system -- that is, what Linux expects of
30 ----------------
33 exist in Linux for describing non-enumerable hardware, after all. In this
40 - ACPI’s byte code (AML) allows the platform to encode hardware behavior,
45 - ACPI’s OSPM defines a power management model that constrains what the
49 - In the enterprise server environment, ACPI has established bindings (such
55 - Choosing a single interface to describe the abstraction between a platform
61 - The new ACPI governance process works well and Linux is now at the same
87 interfaces -- one for Linux and one for Windows.
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| /Documentation/gpu/ |
| D | introduction.rst | 6 complex graphics devices, usually containing programmable pipelines well
23 are written as all-uppercase, for example: DRM, KMS, IOCTL, CRTC, and so
44 Functions which have a non-\ ``void`` return value should have a section
47 section name should be all upper-case or not, and whether it should end
48 in a colon or not. Go with the file-local style. Other common section
55 -----------------------------------
88 -----------------------
90 All feature work must be in the linux-next tree by the -rc6 release of the
92 merge window. All patches must have landed in the drm-next tree by latest -rc7,
93 but if your branch is not in linux-next then this must have happened by -rc6
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
27 Each Dual-Core R5F sub-system is represented as a single DTS node
40 - ti,am62-r5fss
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