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/Documentation/devicetree/bindings/spi/
Dspi-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - xlnx,xps-spi-2.00.a
19 - xlnx,xps-spi-2.00.b
20 - xlnx,axi-quad-spi-1.00.a
28 xlnx,num-ss-bits:
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/Documentation/devicetree/bindings/mailbox/
Darm,mhu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
24 check the status of each of the bits of this register independently. The use
25 of 32 bits per interrupt line enables software to provide more information
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
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/Documentation/devicetree/bindings/dma/xilinx/
Dxilinx_dma.txt11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
24 - #dma-cells: Should be <1>, see "dmas" property below
25 - reg: Should contain VDMA registers location and length.
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/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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/Documentation/scsi/
Dncr53c8xx.rst1 .. SPDX-License-Identifier: GPL-2.0
11 95170 DEUIL LA BARRE - FRANCE
64 10.4 PCI configuration fix-up boot option
80 16. Synchronous transfer negotiation tables
81 16.1 Synchronous timings for 53C875 and 53C860 Ultra-SCSI controllers
82 16.2 Synchronous timings for fast SCSI-2 53C8XX controllers
97 - Gerard Roudier <groudier@free.fr>
101 - Wolfgang Stanglmeier <wolf@cologne.de>
102 - Stefan Esser <se@mi.Uni-Koeln.de>
106 - ncr53c8xx generic driver that supports all the SYM53C8XX family including
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/Documentation/arch/powerpc/
Dultravisor.rst1 .. SPDX-License-Identifier: GPL-2.0
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
68 * The privilege of a process is now determined by three MSR bits,
75 +---+---+---+---------------+
79 +---+---+---+---------------+
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/Documentation/driver-api/usb/
Ddwc3.rst15 1. Peripheral-only configuration
16 2. Host-only configuration
17 3. Dual-Role configuration
46 pipe - ep0)
48 3. Simultaneous IN and OUT transfer support
49 4. Scatter-list support
51 6. Support for all transfer types (*Control*, *Bulk*,
58 These features have all been exercised with many of the **in-tree**
67 for new-comers to read the code and understand how it behaves.
82 OUT Transfer Size Requirements
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/Documentation/networking/
Dpacket_mmap.rst1 .. SPDX-License-Identifier: GPL-2.0
22 - Ulisses Alonso Camaró <uaca@i.hate.spam.alumni.uv.es>
23 - Johann Baudy
67 [setup] socket() -------> creation of the capture socket
68 setsockopt() ---> allocation of the circular buffer (ring)
70 mmap() ---------> mapping of the allocated buffer to the
73 [capture] poll() ---------> to wait for incoming packets
75 [shutdown] close() --------> destruction of the capture socket and
88 supported and a link level pseudo-header is provided
107 [setup] socket() -------> creation of the transmission socket
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/Documentation/sound/kernel-api/
Dwriting-an-alsa-driver.rst11 Architecture) <http://www.alsa-project.org/>`__ driver. The document
19 low-level driver implementation details. It only describes the standard
26 -------
56 --------------
60 sub-directories contain different modules and are dependent upon the
74 This directory and its sub-directories are for the ALSA sequencer. This
76 as snd-seq-midi, snd-seq-virmidi, etc. They are compiled only when
85 -----------------
88 to be exported to user-space, or included by several files in different
94 -----------------
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/Documentation/admin-guide/
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
66 debug output. Bits in debug_layer correspond to a
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