Searched +full:on +full:- +full:soc (Results 1 – 25 of 687) sorted by relevance
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| /Documentation/devicetree/bindings/arm/ti/ |
| D | k3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments K3 Multicore SoC architecture
10 - Nishanth Menon <nm@ti.com>
13 Platforms based on Texas Instruments K3 Multicore SoC architecture
22 - description: K3 AM62A7 SoC
24 - enum:
25 - ti,am62a7-sk
26 - const: ti,am62a7
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-soc | 5 The /sys/devices/ directory contains a sub-directory for each
6 System-on-Chip (SoC) device on a running platform. Information
7 regarding each SoC can be obtained by reading sysfs files. This
10 The directory created for each SoC will also house information
12 It has been agreed that if an SoC device exists, its supported
13 devices would be better suited to appear as children of that SoC.
19 Read-only attribute common to all SoCs. Contains the SoC machine
26 Read-only attribute common to all SoCs. Contains SoC family name
29 On many of ARM based silicon with SMCCC v1.2+ compliant firmware
48 which is code 0x3B on the fifth 'page'. This is shortened
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| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
7 The following is a list of provided IDs and clock names on Armada 370/XP:
14 The following is a list of provided IDs and clock names on Armada 375:
20 The following is a list of provided IDs and clock names on Armada 380/385:
26 The following is a list of provided IDs and clock names on Armada 39x:
34 The following is a list of provided IDs and clock names on 98dx3236:
40 The following is a list of provided IDs and clock names on Kirkwood and Dove:
46 The following is a list of provided IDs and clock names on Orion5x:
52 - compatible : shall be one of the following:
53 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
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| /Documentation/process/ |
| D | maintainer-soc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 SoC Subsystem
8 --------
10 The SoC subsystem is a place of aggregation for SoC-specific code.
13 * devicetrees for 32- & 64-bit ARM and RISC-V
14 * 32-bit ARM board files (arch/arm/mach*)
15 * 32- & 64-bit ARM defconfigs
16 * SoC-specific drivers across architectures, in particular for 32- & 64-bit
17 ARM, RISC-V and Loongarch
19 These "SoC-specific drivers" do not include clock, GPIO etc drivers that have
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| /Documentation/arch/arm/spear/ |
| D | overview.rst | 6 ------------
11 The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
19 - SPEAr3XX (3XX SOC series, based on ARM9)
20 - SPEAr300 (SOC)
21 - SPEAr300 Evaluation Board
22 - SPEAr310 (SOC)
23 - SPEAr310 Evaluation Board
24 - SPEAr320 (SOC)
25 - SPEAr320 Evaluation Board
26 - SPEAr6XX (6XX SOC series, based on ARM9)
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| /Documentation/hwmon/ |
| D | smpro-hwmon.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
12 Reference: `Altra SoC BMC Interface Specification`
17 -----------
18 The smpro-hwmon driver supports hardware monitoring for Ampere(R) Altra(R)
19 SoCs based on the SMpro co-processor (SMpro). The following sensor metrics
31 -----------
41 When the SoC is turned off, the driver will fail to read registers and
42 return ``-ENXIO``.
45 -------------
54 temp1_input millicelsius RO SoC temperature
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| D | xgene-hwmon.rst | 1 Kernel driver xgene-hwmon
6 * APM X-Gene SoC
9 -----------
12 APM X-Gene SoC using the mailbox communication interface.
19 - SoC on-die temperature in milli-degree C
20 - Alarm when high/over temperature occurs
23 - CPU power in uW
24 - IO power in uW
26 sysfs-Interface
27 ---------------
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| D | raspberrypi-hwmon.rst | 1 Kernel driver raspberrypi-hwmon
6 * Raspberry Pi A+ (via GPIO on SoC)
7 * Raspberry Pi B+ (via GPIO on SoC)
8 * Raspberry Pi 2 B (via GPIO on SoC)
9 * Raspberry Pi 3 B (via GPIO on port expander)
15 -----------
21 -------------
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| /Documentation/devicetree/bindings/arm/ |
| D | apple.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
15 This currently includes devices based on the "M1" SoC:
17 - Mac mini (M1, 2020)
18 - MacBook Pro (13-inch, M1, 2020)
19 - MacBook Air (M1, 2020)
20 - iMac (24-inch, M1, 2021)
22 Devices based on the "M2" SoC:
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| /Documentation/sound/soc/ |
| D | overview.rst | 2 ALSA SoC Layer Overview
5 The overall project goal of the ALSA System on Chip (ASoC) layer is to
6 provide better ALSA support for embedded system-on-chip processors (e.g.
8 subsystem there was some support in the kernel for SoC audio, however it
9 had some limitations:-
11 * Codec drivers were often tightly coupled to the underlying SoC
12 CPU. This is not ideal and leads to code duplication - for example,
13 Linux had different wm8731 drivers for 4 different SoC platforms.
17 event). These are quite common events on portable devices and often require
18 machine specific code to re-route audio, enable amps, etc., after such an
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| /Documentation/devicetree/bindings/rtc/ |
| D | isil,isl12057.txt | 8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
21 - "reg": I2C bus address of the device
25 - "wakeup-source": mark the chip as a wakeup source, independently of
26 the availability of an IRQ line connected to the SoC.
37 Example isl12057 node with IRQ#2 pin connected to main SoC via MPP6 (note
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| /Documentation/devicetree/bindings/mtd/ |
| D | gpmi-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI)
10 - Han Xu <han.xu@nxp.com>
14 flash chips. The device tree may optionally contain sub-nodes
21 - enum:
22 - fsl,imx23-gpmi-nand
23 - fsl,imx28-gpmi-nand
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| /Documentation/driver-api/phy/ |
| D | samsung-usb2.rst | 6 --------------
18 --------------------
20 - phy-samsung-usb2.c
23 Framework. This two callbacks are used to power on and power off the
24 phy. They carry out the common work that has to be done on all version
25 of the PHY module. Depending on which SoC was chosen they execute SoC
26 specific callbacks. The specific SoC version is selected by choosing
30 - phy-samsung-usb2.h
36 ------------------
38 To support a new SoC a new file should be added to the drivers/phy
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| /Documentation/power/ |
| D | opp.rst | 5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
23 In an operational system executing varied use cases, not all modules in the SoC
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
41 - {300000000, 1000000}
42 - {800000000, 1200000}
43 - {1000000000, 1300000}
46 ----------------------------------------
57 (users) -> registers a set of default OPPs -> (library)
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| /Documentation/devicetree/bindings/watchdog/ |
| D | aspeed,ast2400-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/aspeed,ast2400-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
15 - aspeed,ast2400-wdt
16 - aspeed,ast2500-wdt
17 - aspeed,ast2600-wdt
29 aspeed,reset-type:
32 - cpu
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| /Documentation/arch/arm/keystone/ |
| D | overview.rst | 6 ------------
7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
9 for users to run Linux on Keystone based EVMs from Texas Instruments.
11 Following SoCs & EVMs are currently supported:-
13 K2HK SoC and EVM
16 a.k.a Keystone 2 Hawking/Kepler SoC
23 http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
25 K2E SoC and EVM
28 a.k.a Keystone 2 Edison SoC
30 K2E - 66AK2E05:
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
29 the pad setting value like pull-up on this pin. And that's why fsl,pins entry
35 SION(1 << 30): Software Input On Field.
41 Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
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| D | sprd,pinctrl.txt | 8 pad driving level, system control select and so on ("domain pad
9 driving level": One pin can output 3.0v or 1.8v, depending on the
13 have several systems (AP/CP/CM4) on one SoC.).
16 of them, so we can not make every Spreadtrum-special configuration
32 Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
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| /Documentation/devicetree/bindings/soc/socionext/ |
| D | socionext,uniphier-soc-glue-debug.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic debug part
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic debug part implemented on Socionext UniPhier SoCs is
20 - enum:
21 - socionext,uniphier-ld4-soc-glue-debug
22 - socionext,uniphier-pro4-soc-glue-debug
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| D | socionext,uniphier-soc-glue.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC-glue logic
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
19 - enum:
20 - socionext,uniphier-ld4-soc-glue
21 - socionext,uniphier-pro4-soc-glue
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| /Documentation/i2c/busses/ |
| D | i2c-i801.rst | 2 Kernel driver i2c-i801
7 * Intel 82801AA and 82801AB (ICH and ICH0 - part of the
9 * Intel 82801BA (ICH2 - part of the '815E' chipset)
27 * Intel Avoton (SOC)
31 * Intel BayTrail (SOC)
32 * Intel Braswell (SOC)
35 * Intel DNV (SOC)
36 * Intel Broxton (SOC)
38 * Intel Gemini Lake (SOC)
45 * Intel Jasper Lake (SOC)
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| /Documentation/devicetree/bindings/arm/keystone/ |
| D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
21 on multiple processors including ones running Linux.
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | sci-pm-domain.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/sci-pm-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI generic power domain
10 - Nishanth Menon <nm@ti.com>
13 - $ref: /schemas/power/power-domain.yaml#
17 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
18 the state of the various hardware modules present on the SoC. Communication
20 through a protocol called TI System Control Interface (TI-SCI protocol).
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| D | wkup-m3-ipc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dave Gerlach <d-gerlach@ti.com>
11 - Drew Fustini <dfustini@baylibre.com>
14 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
17 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
19 present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an
20 API to allow the SoC PM code to execute specific PM tasks.
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| /Documentation/trace/coresight/ |
| D | coresight-dummy.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 ------------
14 have permission to access or configure, e.g., CoreSight TPDMs on Qualcomm
18 It provides Coresight API for operations on dummy devices, such as enabling and
23 --------------
30 $ ls -l /sys/bus/coresight/devices | grep dummy
31 dummy_sink0 -> ../../../devices/platform/soc@0/soc@0:sink/dummy_sink0
32 dummy_source0 -> ../../../devices/platform/soc@0/soc@0:source/dummy_source0
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