Searched +full:per +full:- +full:port +full:- +full:set (Results 1 – 25 of 158) sorted by relevance
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| /Documentation/devicetree/bindings/media/ |
| D | cdns,csi2tx.txt | 1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
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| /Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| D | switch-driver.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 The driver uses the switch device driver model and exposes each switch port as
24 [dpaa2-eth] [dpaa2-eth] [ dpaa2-switch ]
30 | ---------- | [DPMAC] [DPMAC]
31 ------------------------------- | |
38 The dpaa2-switch driver probes on DPSW devices found on the fsl-mc bus. These
40 file - DataPath Layout (DPL) - or at runtime using the DPAA2 object APIs
43 At the moment, the dpaa2-switch driver imposes the following restrictions on
48 done, ie when not under a bridge, each switch port will have its own FDB.
53 * Both the broadcast and flooding configuration should be per FDB. This
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| /Documentation/arch/s390/ |
| D | pci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 - Pierre Morel
17 -----------------------
25 Ignore the RID field and force use of one PCI domain per PCI function.
28 ---------------
36 - /sys/kernel/debug/s390dbf/pci_msg/sprintf
52 The slot entries are set up using the function identifier (FID) of the
56 - /sys/bus/pci/slots/XXXXXXXX/power
64 - function_id
67 - function_handle
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| /Documentation/networking/device_drivers/ethernet/intel/ |
| D | i40e.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
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| D | e1000e.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2008-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
34 There needs to be a <VAL#> for each network port in the system supported by
48 ---------------------
49 :Valid Range: 0,1,3,4,100-100000
53 vector can generate per second. Increasing ITR lowers latency at the cost of
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| D | ice.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
43 -------------------------------------------
54 1) Make sure that your system's physical memory is in a high-performance
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| D | iavf.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2013-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Additional Configurations
16 - Known Issues/Troubleshooting
17 - Support
30 The guest OS loading the iavf driver must support MSI-X interrupts.
53 ---------------------
56 your console, set dmesg to eight by entering the following::
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| /Documentation/netlink/specs/ |
| D | team.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 protocol: genetlink-legacy
10 c-family-name: team-genl-name
11 c-version-name: team-genl-version
12 kernel-policy: global
13 uapi-header: linux/if_team.h
16 -
17 name: string-max-len
20 -
21 name: genl-change-event-mc-grp-name
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| /Documentation/scsi/ |
| D | advansys.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
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| /Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 The Tegra186 GPIO controller allows software to set the IO direction of,
26 GPIO register set. These registers exist in a single contiguous block
30 Access to this set of registers is not necessary in all circumstances.
42 implemented by the SoC. Each GPIO is assigned to a port, and a port may
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| /Documentation/networking/ |
| D | mptcp-sysctl.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 add_addr_timeout - INTEGER (seconds)
11 Set the timeout after which an ADD_ADDR control message will be
15 Do not retransmit if set to 0.
17 The default value matches TCP_RTO_MAX. This is a per-namespace
22 allow_join_initial_addr_port - BOOLEAN
23 Allow peers to send join requests to the IP address and port number used
31 This is a per-namespace sysctl.
35 available_schedulers - STRING
39 blackhole_timeout - INTEGER (seconds)
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| D | rds.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 http://oss.oracle.com/pipermail/rds-devel/2007-November/000228.html
22 cluster - so in a cluster with N processes you need N sockets, in contrast
23 to N*N if you use a connection-oriented socket transport like TCP.
25 RDS is not Infiniband-specific; it was designed to support different
29 The high-level semantics of RDS from the application's point of view are
33 RDS uses IPv4 addresses and 16bit port numbers to identify
39 transport has to be IP-based. In fact, RDS over IB uses a
43 The port space is entirely independent of UDP, TCP or any other
59 a active-active HA scenario), but only as long as the address
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| D | ip-sysctl.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 ip_forward - BOOLEAN
11 - 0 - disabled (default)
12 - not 0 - enabled
20 ip_default_ttl - INTEGER
25 ip_no_pmtu_disc - INTEGER
27 fragmentation-required ICMP is received, the PMTU to this
28 destination will be set to the smallest of the old MTU to
38 accept fragmentation-needed errors if the underlying protocol
48 Possible values: 0-3
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,video.txt | 2 -------------------------------
5 ---------------
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
18 in Documentation/devicetree/bindings/dma/dma.txt) per port. Each port
19 requires a DMA channel with the identifier string set to "port" followed by
20 the port index.
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
24 Required port properties:
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| /Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
| D | switchdev.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
19 - Change device to switchdev mode::
21 $ devlink dev eswitch set pci/0000:06:00.0 mode switchdev
23 - Attach mlx5 switchdev representor 'enp8s0f0' to bridge netdev 'bridge1'::
25 $ ip link set enp8s0f0 master bridge1
28 -----
32 - VLAN filtering (including multiple VLANs per port)::
34 $ ip link set bridge1 type bridge vlan_filtering 1
35 $ bridge vlan add dev enp8s0f0 vid 2-3
37 - VLAN push on bridge ingress::
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | cpus.txt | 6 per the definition in the Devicetree Specification.
13 - fsl,eref-*
19 by the Power ISA. For these EREF-specific categories, the existence of
20 a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
24 - fsl,portid-mapping
27 Definition: The Coherency Subdomain ID Port Mapping Registers and
28 Snoop ID Port Mapping registers, which are part of the CoreNet
31 these registers should be set if the corresponding CPU should be
33 that should be set if this cpu should be snooped.
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| /Documentation/driver-api/serial/ |
| D | driver.rst | 10 The reference implementation is contained within amba-pl011.c.
15 --------------------------------
17 The low level serial hardware driver is responsible for supplying port
18 information (defined by uart_port) and a set of control methods (defined
20 responsible for handling interrupts for the port, and providing any
25 ---------------
28 the correct port structure (via uart_get_console()) and decoding command line
38 -------
41 necessary locking using port->lock. There are some exceptions (which
44 There are two locks. A per-port spinlock, and an overall semaphore.
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | renesas,rza1-ports.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
18 Each "port" features up to 16 pins, each of them configurable for GPIO
19 function (port mode) or in alternate function mode.
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| D | renesas,rza2-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17 Each port features up to 8 pins, each of them configurable for GPIO function
18 (port mode) or in alternate function mode.
23 const: renesas,r7s9210-pinctrl # RZ/A2M
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| /Documentation/devicetree/bindings/sound/ |
| D | fsl,sgtl5000.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
13 - $ref: dai-common.yaml#
22 "#sound-dai-cells":
25 assigned-clock-parents: true
26 assigned-clock-rates: true
27 assigned-clocks: true
31 - description: the clock provider of SYS_MCLK
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | imx219.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor
10 - Dave Stevenson <dave.stevenson@raspberrypi.com>
12 description: |-
13 The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor
15 I2C interface. The I2C address is fixed to 0x10 as per sensor data sheet.
16 Image data is sent through MIPI CSI-2, which is configured as either 2 or
30 VDIG-supply:
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| /Documentation/networking/devlink/ |
| D | devlink-port.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 Devlink Port
9 ``devlink-port`` is a port that exists on the device. It has a logically
10 separate ingress/egress point of the device. A devlink port can be any one
11 of many flavours. A devlink port flavour along with port attributes
12 describe what a port represents.
14 A device driver that intends to publish a devlink port sets the
15 devlink port attributes and registers the devlink port.
17 Devlink port flavours are described below.
19 .. list-table:: List of devlink port flavours
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| D | netdevsim.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 * - ``max_macs``
18 - driverinit
20 The ``netdevsim`` driver also implements the following driver-specific
23 .. list-table:: Driver-specific parameters implemented
26 * - Name
27 - Type
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| /Documentation/sound/cards/ |
| D | serial-u16550.rst | 7 * 0 - Roland Soundcanvas support (default)
8 * 1 - Midiator MS-124T support (1)
9 * 2 - Midiator MS-124W S/A mode (2)
10 * 3 - MS-124W M/B mode support (3)
11 * 4 - Generic device with multiple input support (4)
13 For the Midiator MS-124W, you must set the physical M-S and A-B
17 (midiCnD0-midiCnD15). Whenever you write to a different substream, the driver
28 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 speed=115200
34 /sbin/modprobe snd-serial-u16550 port=0x3f8 irq=4 outs=4
36 In MS-124T mode, one raw MIDI substream is supported (midiCnD0); the outs
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| /Documentation/devicetree/bindings/crypto/ |
| D | img-hash.txt | 8 - compatible : "img,hash-accelerator"
9 - reg : Offset and length of the register set for the module, and the DMA port
10 - interrupts : The designated IRQ line for the hashing module.
11 - dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt
12 - dma-names : Should be "tx"
13 - clocks : Clock specifiers
14 - clock-names : "sys" Used to clock the hash block registers
20 compatible = "img,hash-accelerator";
24 dma-names = "tx";
26 clock-names = "sys", "hash";
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