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/Documentation/devicetree/bindings/net/
Dfsl-tsec-phy.txt3 The MDIO is a bus to which the PHY devices are connected. For each
5 the definition of the PHY node in booting-without-of.txt for an example
6 of how to define a PHY.
9 - reg : Offset and length of the register set for the device, and optionally
10 the offset and length of the TBIPA register (TBI PHY address
14 - compatible : Should define the compatible device type for the
16 - "fsl,gianfar-tbi"
17 - "fsl,gianfar-mdio"
18 - "fsl,etsec2-tbi"
19 - "fsl,etsec2-mdio"
[all …]
Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCA807x Ethernet PHY
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
14 Qualcomm QCA8072/5 Ethernet PHY is PHY package of 2 or 5
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
18 They feature 2 SerDes, one for PSGMII or QSGMII connection with
[all …]
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
Dnxp,tja11xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP TJA11xx PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
[all …]
Dfsl,qoriq-mc-dpmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: ethernet-controller.yaml#
21 const: fsl,qoriq-mc-dpmac
27 pcs-handle:
[all …]
Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR803x PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
26 qca,clk-out-strength:
[all …]
Dengleder,tsnep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gerhard Engleder <gerhard@engleder-embedded.com>
13 - $ref: ethernet-controller.yaml#
26 interrupt-names:
29 - const: mac
30 - const: txrx-1
31 - const: txrx-2
32 - const: txrx-3
[all …]
Dfsl,enetc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 (SR-IOV), advanced QoS with 8 traffic classes and 4 drop resilience levels,
16 - Frank Li <Frank.Li@nxp.com>
17 - Vladimir Oltean <vladimir.oltean@nxp.com>
18 - Wei Fang <wei.fang@nxp.com>
19 - Claudiu Manoil <claudiu.manoil@nxp.com>
24 - enum:
25 - pci1957,e100
[all …]
Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
[all …]
Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
12 the information in section 2) depending on the type of interrupt
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
[all …]
/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
Dmac-phy-support.rst1 .. SPDX-License-Identifier: GPL-2.0
5 DPAA2 MAC / PHY support
11 --------
13 The DPAA2 MAC / PHY support consists of a set of APIs that help DPAA2 network
14 drivers (dpaa2-eth, dpaa2-ethsw) interact with the PHY library.
17 ---------------------------
19 Among other DPAA2 objects, the fsl-mc bus exports DPNI objects (abstracting a
20 network interface) and DPMAC objects (abstracting a MAC). The dpaa2-eth driver
25 DPNIs. Depending on the connection type, the netif_carrier_[on/off] is handled
26 directly by the dpaa2-eth driver or by phylink.
[all …]
/Documentation/networking/device_drivers/ethernet/intel/
De1000e.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 Linux Driver for Intel(R) Ethernet Network Connection
8 Copyright(c) 2008-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
48 ---------------------
49 :Valid Range: 0,1,3,4,100-100000
70 that it receives. After determining the type of incoming traffic in the last
[all …]
/Documentation/devicetree/bindings/media/
Drockchip-isp1.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Helen Koike <helen.koike@collabora.com>
19 - fsl,imx8mp-isp
20 - rockchip,px30-cif-isp
21 - rockchip,rk3399-cif-isp
30 interrupt-names:
32 - const: isp
[all …]
/Documentation/networking/
Dphy.rst2 PHY Abstraction Layer
9 to a MAC layer, which communicates with the physical connection through a
10 PHY. The PHY concerns itself with negotiating link parameters with the link
11 partner on the other side of the network connection (typically, an ethernet
17 the PHY management code with the network driver. This has resulted in large
23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
30 Basically, this layer is meant to provide an interface to PHY devices which
37 Most network devices are connected to a PHY by means of a management bus.
[all …]
/Documentation/devicetree/bindings/phy/
Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/Documentation/driver-api/nfc/
Dnfc-hci.rst5 - Author: Eric Lapuyade, Samuel Ortiz
6 - Contact: eric.lapuyade@intel.com, samuel.ortiz@intel.com
9 -------
12 enables easy writing of HCI-based NFC drivers. The HCI layer runs as an NFC Core
17 ---
30 - one for executing commands : nfc_hci_msg_tx_work(). Only one command
32 - one for dispatching received events and commands : nfc_hci_msg_rx_work().
35 --------------------------
41 In case the chip supports pre-opened gates and pseudo-static pipes, the driver
45 -------------------
[all …]
/Documentation/devicetree/bindings/mfd/
Dstericsson,ab8500.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Analog Baseband AB8500 and AB8505
10 - Linus Walleij <linus.walleij@linaro.org>
13 the AB8500 "Analog Baseband" is the mixed-signals integrated circuit
14 handling power management (regulators), analog-to-digital conversion
15 (ADC), battery charging, fuel gauging of the battery, battery-backed
16 RTC, PWM, USB PHY and some GPIO lines in the ST-Ericsson U8500 platforms
17 in connection with the DB8500 digital baseband. The DB8500 PRCMU
[all …]
/Documentation/firmware-guide/acpi/dsd/
Dphy.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The PHYs on an MDIO bus [phy] are probed and registered using
14 for connecting PHYs on the MDIO bus [dsd-properties-rules] to the MAC layer.
17 Properties UUID For _DSD" [dsd-guide] document and the
18 daffd814-6eba-4d8c-8a91-bc9bbf4aa301 UUID must be used in the Device
21 phy-handle
22 ----------
23 For each MAC node, a device property "phy-handle" is used to reference
24 the PHY that is registered on an MDIO bus. This is mandatory for
30 .. code-block:: none
[all …]
/Documentation/driver-api/usb/
Dtypec.rst3 USB Type-C connector class
7 ------------
9 The typec class is meant for describing the USB Type-C ports in a system to the
14 The platforms are expected to register every USB Type-C port they have with the
15 class. In a normal case the registration will be done by a USB Type-C or PD PHY
18 considers the component registering the USB Type-C ports with the class as "port
26 attributes are described in Documentation/ABI/testing/sysfs-class-typec.
29 --------------------
36 "port0-partner". Full path to the device would be
37 /sys/class/typec/port0/port0-partner/.
[all …]
/Documentation/devicetree/bindings/connector/
Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
20 - enum:
21 - usb-a-connector
22 - usb-b-connector
23 - usb-c-connector
25 - items:
[all …]

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