Searched +full:port +full:- +full:level (Results 1 – 25 of 214) sorted by relevance
123456789
| /Documentation/driver-api/serial/ |
| D | driver.rst | 2 Low Level Serial API
10 The reference implementation is contained within amba-pl011.c.
14 Low Level Serial Hardware Driver
15 --------------------------------
17 The low level serial hardware driver is responsible for supplying port
19 by uart_ops) to the core serial driver. The low level driver is also
20 responsible for handling interrupts for the port, and providing any
25 ---------------
28 the correct port structure (via uart_get_console()) and decoding command line
38 -------
[all …]
|
| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-dma3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 described in "#dma-cells" property description below, using a three-cell
26 - Amelie Delaunay <amelie.delaunay@foss.st.com>
29 - $ref: /schemas/dma/dma-controller.yaml#
33 const: st,stm32mp25-dma3
42 Should contain all of the per-channel DMA interrupts in ascending order
51 power-domains:
[all …]
|
| /Documentation/devicetree/bindings/display/ |
| D | st,stm32mp25-lvds.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
19 - LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
21 - LVDS PHY: parallelize the data and drives the LVDS data lanes
22 - LVDS wrapper: handles top-level settings
[all …]
|
| /Documentation/devicetree/bindings/phy/ |
| D | phy-stm32-usbphyc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
13 selects either OTG or HOST controller for the second PHY port. It also sets
19 |_ PHY port#1 _________________ HOST controller
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
[all …]
|
| D | realtek,usb2phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <stanley_chang@realtek.com>
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
33 XHCI controller#0 -- usb2phy -- phy#0
[all …]
|
| /Documentation/devicetree/bindings/net/ |
| D | marvell-orion-net.txt | 9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
11 the multiple levels is that the port registers are interleaved within a single
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
25 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
26 - reg: address and length of the controller registers.
29 - clocks: phandle reference to the controller clock.
[all …]
|
| /Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
42 implemented by the SoC. Each GPIO is assigned to a port, and a port may
44 alphabetical port name and an integer GPIO name within the port. For
48 of implemented GPIOs within each port varies. GPIO registers within a
49 controller are grouped and laid out according to the port they affect.
[all …]
|
| D | aspeed,sgpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
17 - Support interrupt option for each input port and various interrupt
18 sensitivity option (level-high, level-low, edge-high, edge-low)
19 - Support reset tolerance option for each output port
20 - Directly connected to APB bus and its shift clock is from APB bus clock
22 - Co-work with external signal-chained TTL components (74LV165/74LV595)
27 - aspeed,ast2400-sgpio
[all …]
|
| /Documentation/arch/m68k/ |
| D | buddha-driver.rst | 8 ------------------------------------------------------------------------
11 Buddha-part of the Catweasel Zorro-II version
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
36 otherwise your chance is only 1:16 to find the board :-).
38 The local memory-map is even active when mapped to $e8:
41 $0-$7e Autokonfig-space, see Z-II docs.
[all …]
|
| /Documentation/scsi/ |
| D | advansys.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
[all …]
|
| /Documentation/netlabel/ |
| D | draft-ietf-cipso-ipsecurity-01.txt | 12 This Internet Draft provides the high level specification for a Commercial
27 Please check the I-D abstract listing contained in each Internet Draft
46 mandatory access controls and multi-level security. These systems are
88 once in a datagram. All multi-octet fields in the option are defined to be
91 +----------+----------+------//------+-----------//---------+
93 +----------+----------+------//------+-----------//---------+
124 corresponding ASCII representations. Non-related groups of systems may
138 number 1 to represent that same security level. The DOI identifier is used
148 actual security information to be passed. All multi-octet fields in a tag
171 +----------+----------+--------//--------+
[all …]
|
| /Documentation/admin-guide/ |
| D | thunderbolt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 some differences at the register level among other things. Connection
18 software connection manager in Linux also advertises security level
21 the software connection manager only supports ``user`` security level and
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
35 ``/etc/udev/rules.d/99-local.rules``::
44 security levels available. Intel Titan Ridge added one more security level
51 treated as another security level (nopcie).
[all …]
|
| /Documentation/devicetree/bindings/media/i2c/ |
| D | ti,ds90ub960.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DS90UB9XX Family FPD-Link Deserializer Hubs
10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
13 The TI DS90UB9XX devices are FPD-Link video deserializers with I2C and GPIO
17 - $ref: /schemas/i2c/i2c-atr.yaml#
22 - ti,ds90ub960-q1
23 - ti,ds90ub9702-q1
33 clock-names:
[all …]
|
| D | max2175.txt | 2 -----------------------------------------
4 The MAX2175 IC is an advanced analog/digital hybrid-radio receiver with
5 RF to Bits® front-end designed for software-defined radio solutions.
8 --------------------
9 - compatible: "maxim,max2175" for MAX2175 RF-to-bits tuner.
10 - clocks: clock specifier.
11 - port: child port node corresponding to the I2S output, in accordance with
13 Documentation/devicetree/bindings/media/video-interfaces.txt. The port
17 --------------------
18 - maxim,master : phandle to the master tuner if it is a slave. This
[all …]
|
| /Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,video.txt | 2 -------------------------------
5 ---------------
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
10 node of the VIPP represents as a top level node of the pipeline and defines
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
18 in Documentation/devicetree/bindings/dma/dma.txt) per port. Each port
19 requires a DMA channel with the identifier string set to "port" followed by
20 the port index.
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
[all …]
|
| D | xlnx,v-tpg.txt | 2 -----------------------------------------
6 - compatible: Must contain at least one of
8 "xlnx,v-tpg-5.0" (TPG version 5.0)
9 "xlnx,v-tpg-6.0" (TPG version 6.0)
11 TPG versions backward-compatible with previous versions should list all
14 - reg: Physical base address and length of the registers set for the device.
16 - clocks: Reference to the video core clock.
18 - xlnx,video-format, xlnx,video-width: Video format and width, as defined in
21 - port: Video port, using the DT bindings defined in ../video-interfaces.txt.
22 The TPG has a single output port numbered 0.
[all …]
|
| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,tpd12s015.txt | 1 TPD12S015 HDMI level shifter and ESD protection chip
5 - compatible: "ti,tpd12s015"
8 - gpios: CT CP HPD, LS OE and HPD gpios
11 - Video port 0 for HDMI input
12 - Video port 1 for HDMI output
15 -------
25 #address-cells = <1>;
26 #size-cells = <0>;
28 port@0 {
32 remote-endpoint = <&hdmi_out>;
[all …]
|
| D | ti,k2g-dss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
15 The K2G DSS is an ultra-light version of TI Keystone Display
16 SubSystem. It has only one output port and video plane. The
21 const: ti,k2g-dss
25 - description: cfg DSS top level
[all …]
|
| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-hisi_ptt | 9 See Documentation/trace/hisi-ptt.rst for more information.
19 to 2. The value indicates a probable level of the event.
25 Description: (RW) Controls the weight of Tx non-posted TLPs, which influence
26 the proportion of outbound non-posted TLPs on the PCIe link.
29 to 2. The value indicates a probable level of the event.
39 to 2. The value indicates a probable level of the event.
50 to 2. The value indicates a probable level of the event.
61 to 2. The value indicates a probable level of the event.
67 Description: This directory contains the files providing the PCIe Root Port filters
69 Root Port device name <domain>:<bus>:<device>.<function>.
[all …]
|
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | qcom,pdc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 Power Domain Controller (PDC) that is on always-on domain. In addition to
17 well detect interrupts when the GIC is non-operational.
19 GIC is parent interrupt controller at the highest level. Platform interrupt
22 specify PDC as their interrupt controller and request the PDC port associated
28 - enum:
[all …]
|
| /Documentation/devicetree/bindings/media/ |
| D | cdns,csi2tx.txt | 1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
[all …]
|
| D | imx.txt | 5 ---------------------------
12 - compatible : "fsl,imx-capture-subsystem";
13 - ports : Should contain a list of phandles pointing to camera
18 capture-subsystem {
19 compatible = "fsl,imx-capture-subsystem";
25 --------------
27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
29 combined with a D-PHY core mixed into the same register block. In
30 addition this device consists of an i.MX-specific "CSI2IPU gasket"
[all …]
|
| /Documentation/arch/s390/ |
| D | pci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 - Pierre Morel
17 -----------------------
28 ---------------
36 - /sys/kernel/debug/s390dbf/pci_msg/sprintf
40 Change the level of logging to be more or less verbose by piping
41 a number between 0 and 6 to /sys/kernel/debug/s390dbf/pci_*/level. For
56 - /sys/bus/pci/slots/XXXXXXXX/power
64 - function_id
67 - function_handle
[all …]
|
| /Documentation/networking/device_drivers/ethernet/microsoft/ |
| D | netvsc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Hyper-V network driver
17 ----------------
19 Hyper-V host version does. Windows Server 2016 and Azure
24 --------------------
25 Hyper-V supports receive side scaling. For TCP & UDP, packets can
26 be distributed among available queues based on IP address and port
29 For TCP & UDP, we can switch hash level between L3 and L4 by ethtool
31 hash level is L4. We currently only allow switching TX hash level
39 To include UDP port numbers in hashing::
[all …]
|
| /Documentation/driver-api/cxl/ |
| D | memory-devices.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
35 port and an endpoint may interleave cycles across multiple Downstream Switch
40 Ports. Each of those Root Ports are connected to 2-way switches with endpoints
43 # cxl list -BEMPu -b cxl_test
49 "port":"port5",
53 "port":"port8",
83 "port":"port12",
[all …]
|
123456789