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/Documentation/devicetree/bindings/pwm/
Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
14 (controller specific)
[all …]
Dpwm-hibvt.txt1 Hisilicon PWM controller
4 -compatible: should contain one SoC specific compatible string
6 "hisilicon,hi3516cv300-pwm"
7 "hisilicon,hi3519v100-pwm"
8 "hisilicon,hi3559v100-shub-pwm"
9 "hisilicon,hi3559v100-pwm
10 - reg: physical base address and length of the controller's registers.
11 - clocks: phandle and clock specifier of the PWM reference clock.
12 - resets: phandle and reset specifier for the PWM controller reset.
13 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
[all …]
Dmediatek,mt2712-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek PWM Controller
10 - John Crispin <john@phrozen.org>
13 - $ref: pwm.yaml#
18 - enum:
19 - mediatek,mt2712-pwm
20 - mediatek,mt6795-pwm
[all …]
Dpwm-sprd.txt1 Spreadtrum PWM controller
3 Spreadtrum SoCs PWM controller provides 4 PWM channels.
6 - compatible : Should be "sprd,ums512-pwm".
7 - reg: Physical base address and length of the controller's registers.
8 - clocks: The phandle and specifier referencing the controller's clocks.
9 - clock-names: Should contain following entries:
10 "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
11 "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
12 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
16 - assigned-clocks: Reference to the PWM clock entries.
[all …]
Dmediatek,pwm-disp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DISP_PWM Controller
10 - Jitao Shi <jitao.shi@mediatek.com>
13 - $ref: pwm.yaml#
18 - enum:
19 - mediatek,mt2701-disp-pwm
20 - mediatek,mt6595-disp-pwm
[all …]
Datmel,hlcdc-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/atmel,hlcdc-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel's HLCDC's PWM controller
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Alexandre Belloni <alexandre.belloni@bootlin.com>
12 - Claudiu Beznea <claudiu.beznea@tuxon.dev>
15 The LCDC integrates a Pulse Width Modulation (PWM) Controller. This block
17 display's contrast by software. LCDC_PWM is an 8-bit PWM signal that can be
[all …]
Dspear-pwm.txt1 == ST SPEAr SoC PWM controller ==
4 - compatible: should be one of:
5 - "st,spear320-pwm"
6 - "st,spear1340-pwm"
7 - reg: physical base address and length of the controller's registers
8 - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
13 pwm: pwm@a8000000 {
14 compatible ="st,spear320-pwm";
16 #pwm-cells = <2>;
Dcirrus,clps711x-pwm.txt1 * Cirris Logic CLPS711X PWM controller
4 - compatible: Shall contain "cirrus,ep7209-pwm".
5 - reg: Physical base address and length of the controller's registers.
6 - clocks: phandle + clock specifier pair of the PWM reference clock.
7 - #pwm-cells: Should be 1. The cell specifies the index of the channel.
10 pwm: pwm@80000400 {
11 compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm";
14 #pwm-cells = <1>;
Dopencores,pwm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OpenCores PWM controller
10 - William Qiu <william.qiu@starfivetech.com>
13 The OpenCores PTC ip core contains a PWM controller. When operating in PWM
14 mode, the PTC core generates binary signal with user-programmable low and
15 high periods. All PTC counters and registers are 32-bit.
18 - $ref: pwm.yaml#
[all …]
Dbrcm,bcm7038-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/brcm,bcm7038-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller)
10 - Florian Fainelli <f.fainelli@gmail.com>
13 - $ref: pwm.yaml#
17 const: brcm,bcm7038-pwm
22 "#pwm-cells":
29 - compatible
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Dpwm-berlin.txt1 Berlin PWM controller
4 - compatible: should be "marvell,berlin-pwm"
5 - reg: physical base address and length of the controller's registers
6 - clocks: phandle to the input clock
7 - #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
12 pwm: pwm@f7f20000 {
13 compatible = "marvell,berlin-pwm";
16 #pwm-cells = <3>;
Dvt8500-pwm.txt1 VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller
4 - compatible: should be "via,vt8500-pwm"
5 - reg: physical base address and length of the controller's registers
6 - #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
9 - clocks: phandle to the PWM source clock
13 pwm1: pwm@d8220000 {
14 #pwm-cells = <3>;
15 compatible = "via,vt8500-pwm";
Dbrcm,kona-pwm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pwm/brcm,kona-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family PWM controller
10 This controller has 6 channels.
13 - Florian Fainelli <f.fainelli@gmail.com>
16 - $ref: pwm.yaml#
21 - enum:
22 - brcm,bcm11351-pwm
[all …]
Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
15 only supports one period for all channels in the PWM. All PWMs need to
18 achievable period. PWM RTL that corresponds to the IP block version
19 numbers can be found here -
[all …]
Dpwm-bcm2835.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm-bcm2835.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2835 PWM controller (Raspberry Pi controller)
10 - Stefan Wahren <stefan.wahren@i2se.com>
13 - $ref: pwm.yaml#
17 const: brcm,bcm2835-pwm
25 "#pwm-cells":
29 - compatible
[all …]
Dbrcm,iproc-pwm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pwm/brcm,iproc-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom iProc PWM controller
10 - Rafał Miłecki <rafal@milecki.pl>
13 This controller has 4 channels.
16 - $ref: pwm.yaml#
20 const: brcm,iproc-pwm
29 "#pwm-cells":
[all …]
Dlpc32xx-pwm.txt1 LPC32XX PWM controller
4 - compatible: should be "nxp,lpc3220-pwm"
5 - reg: physical base address and length of the controller's registers
9 pwm@4005c000 {
10 compatible = "nxp,lpc3220-pwm";
14 pwm@4005c004 {
15 compatible = "nxp,lpc3220-pwm";
Dkontron,sl28cpld-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/kontron,sl28cpld-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PWM driver for the sl28cpld board management controller
10 - Michael Walle <michael@walle.cc>
13 This module is part of the sl28cpld multi-function device. For more
16 The controller supports one PWM channel and supports only four distinct
20 - $ref: pwm.yaml#
24 const: kontron,sl28cpld-pwm
[all …]
Dst,stmpe-pwm.txt1 == ST STMPE PWM controller ==
3 This is a PWM block embedded in the ST Microelectronics STMPE
4 (ST Multi-Purpose Expander) chips. The PWM is registered as a
8 - compatible: should be:
9 - "st,stmpe-pwm"
10 - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
15 pwm0: pwm {
16 compatible = "st,stmpe-pwm";
17 #pwm-cells = <2>;
Datmel,at91sam-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/atmel,at91sam-pwm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Atmel/Microchip PWM controller
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
14 - $ref: pwm.yaml#
19 - items:
20 - enum:
21 - atmel,at91sam9rl-pwm
[all …]
/Documentation/devicetree/bindings/hwmon/
Dnpcm750-pwm-fan.txt1 Nuvoton NPCM PWM and Fan Tacho controller device
3 The Nuvoton BMC NPCM7XX supports 8 Pulse-width modulation (PWM)
4 controller outputs and 16 Fan tachometer controller inputs.
6 The Nuvoton BMC NPCM8XX supports 12 Pulse-width modulation (PWM)
7 controller outputs and 16 Fan tachometer controller inputs.
9 Required properties for pwm-fan node
10 - #address-cells : should be 1.
11 - #size-cells : should be 0.
12 - compatible : "nuvoton,npcm750-pwm-fan" for Poleg NPCM7XX.
13 : "nuvoton,npcm845-pwm-fan" for Arbel NPCM8XX.
[all …]
Daspeed-pwm-tacho.txt1 ASPEED AST2400/AST2500 PWM and Fan Tacho controller device driver
3 The ASPEED PWM controller can support upto 8 PWM outputs. The ASPEED Fan Tacho
4 controller can support upto 16 Fan tachometer inputs.
6 There can be upto 8 fans supported. Each fan can have one PWM output and
9 Required properties for pwm-tacho node:
10 - #address-cells : should be 1.
12 - #size-cells : should be 1.
14 - #cooling-cells: should be 2.
16 - reg : address and length of the register set for the device.
18 - pinctrl-names : a pinctrl state named "default" must be defined.
[all …]
Daspeed,g6-pwm-tach.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/aspeed,g6-pwm-tach.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ASPEED G6 PWM and Fan Tach controller
11 - Billy Tsai <billy_tsai@aspeedtech.com>
14 The ASPEED PWM controller can support up to 16 PWM outputs.
15 The ASPEED Fan Tacho controller can support up to 16 fan tach input.
22 - aspeed,ast2600-pwm-tach
33 "#pwm-cells":
[all …]
/Documentation/devicetree/bindings/mfd/
Dkontron,sl28cpld.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Kontron's sl28cpld board management controller
10 - Michael Walle <michael@walle.cc>
13 The board management controller may contain different IP blocks like
14 watchdog, fan monitoring, PWM controller, interrupt controller and a
15 GPIO controller.
26 "#address-cells":
29 "#size-cells":
[all …]
Datmel,hlcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel's HLCD Controller
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Alexandre Belloni <alexandre.belloni@bootlin.com>
12 - Claudiu Beznea <claudiu.beznea@tuxon.dev>
15 The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs exposes two
16 subdevices, a PWM chip and a Display Controller.
21 - atmel,at91sam9n12-hlcdc
[all …]

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