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/Documentation/devicetree/bindings/reset/
Dintel,rcu-gw.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
15 - intel,rcu-lgm
16 - intel,rcu-xrx200
22 intel,global-reset:
23 description: Global reset register offset and bit offset.
24 $ref: /schemas/types.yaml#/definitions/uint32-array
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/Documentation/devicetree/bindings/gpio/
Dgpio-mvebu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 - Andrew Lunn <andrew@lunn.ch>
16 - enum:
17 - marvell,armada-8k-gpio
18 - marvell,orion-gpio
20 - items:
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/Documentation/hwmon/
Dlm85.rst79 - Philip Pokorny <ppokorny@penguincomputing.com>,
80 - Frodo Looijaard <frodol@dds.nl>,
81 - Richard Barrington <rich_b_nz@clear.net.nz>,
82 - Margit Schubert-While <margitsw@t-online.de>,
83 - Justin Thiessen <jthiessen@penguincomputing.com>
86 -----------
92 The LM85 uses the 2-wire interface compatible with the SMBUS 2.0
94 temperatures and five (5) voltages. It has four (4) 16-bit counters for
96 VID signals from the processor to the VRM. Lastly, there are three (3) PWM
110 A sophisticated control system for the PWM outputs is designed into the
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Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
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Dadt7475.rst39 - Jordan Crouse
40 - Hans de Goede
41 - Darrick J. Wong (documentation)
42 - Jean Delvare
46 -----------
56 The ADT747x uses the 2-wire interface compatible with the SMBus 2.0
58 temperatures and two (2) or more voltages. It has four (4) 16-bit counters
59 for measuring fan speed. There are three (3) PWM outputs that can be used
62 A sophisticated control system for the PWM outputs is designed into the
64 three temperature sensors. Each PWM output is individually adjustable and
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Dasc7621.rst20 Andigilog has both the PECI and pre-PECI versions of the Heceta-6, as
21 Intel calls them. Heceta-6e has high frequency PWM and Heceta-6p has
23 Heceta-6e part and aSC7621 is the Heceta-6p part. They are both in
28 have used registers below 20h for vendor-specific functions in addition
29 to those in the Intel-specified vendor range.
32 The fan speed control uses this finer value to produce a "step-less" fan
33 PWM output. These two bytes are "read-locked" to guarantee that once a
34 high or low byte is read, the other byte is locked-in until after the
37 sheet says 10-bits of resolution, although you may find the lower bits
42 data sheet. Our temperature reports and fan PWM outputs are very smooth
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Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
47 and PWM output control functions. Using this parameter
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
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Dit87.rst174 - Christophe Gauthron
175 - Jean Delvare <jdelvare@suse.de>
179 -----------------
191 Force PWM polarity to active high (DANGEROUS). Some chips are
192 misconfigured by BIOS - PWM values would be inverted. This option tries
209 Provided since there are reports that system-wide acpi_enfore_resources=lax
217 -------------------
219 All the chips supported by this driver are LPC Super-I/O chips, accessed
220 through the LPC bus (ISA-like I/O ports). The IT8712F additionally has an
228 -----------
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Daquacomputer_d5next.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Kernel driver aquacomputer-d5next
25 -----------
37 available through debugfs are the serial number, firmware version and power-on
39 temperature curves directly from the pump. If it's not connected, the fan-related
49 as well as eight PWM controllable fans, along with their speed (in RPM), power, voltage
53 sensor and four PWM controllable fans, along with their speed (in RPM), power,
65 filled with coolant. Pump RPM and flow can be set to enhance on-device calculations,
87 -----------
93 -------------
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Dsysfs-interface.rst5 through the sysfs interface. Since lm-sensors 3.0.0, libsensors is
6 completely chip-independent. It assumes that all the kernel drivers
10 This is a major improvement compared to lm-sensors 2.
22 For this reason, even if we aim at a chip-independent libsensors, it will
37 Up to lm-sensors 3.0.0, libsensors looks for hardware monitoring attributes
38 in the "physical" device directory. Since lm-sensors 3.0.1, attributes found
61 to cause an alarm) is chip-dependent.
69 ----------------
76 -------------------------------------------------------------------------
79 `[0-*]` denotes any positive number starting from 0
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/Documentation/devicetree/bindings/display/
Dsolomon,ssd1307fb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Ripard <mripard@kernel.org>
11 - Javier Martinez Canillas <javierm@redhat.com>
17 - enum:
18 - solomon,ssd1305fb-i2c
19 - solomon,ssd1306fb-i2c
20 - solomon,ssd1307fb-i2c
21 - solomon,ssd1309fb-i2c
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/Documentation/devicetree/bindings/arm/marvell/
Dap80x-system-controller.txt6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
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/Documentation/devicetree/bindings/mfd/
Dtc3589x.txt1 * Toshiba TC3589x multi-purpose expander
3 The Toshiba TC3589x series are I2C-based MFD devices which may expose the
4 following built-in devices: gpio, keypad, rotator (vibrator), PWM (for
7 - TC35890
8 - TC35892
9 - TC35893
10 - TC35894
11 - TC35895
12 - TC35896
15 - compatible : must be "toshiba,tc35890", "toshiba,tc35892", "toshiba,tc35893",
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/Documentation/userspace-api/gpio/
Dchardev.rst1 .. SPDX-License-Identifier: GPL-2.0
18 Read Documentation/driver-api/gpio/drivers-on-gpio.rst to avoid reinventing
21 Similarly, for multi-function lines there may be other subsystems, such as
23 Documentation/driver-api/pwm.rst, Documentation/w1/index.rst etc, that
28 The API is based around two major objects, the :ref:`gpio-v2-chip` and the
29 :ref:`gpio-v2-line-request`.
31 .. _gpio-v2-chip:
41 ``offset`` in the range from 0 to ``chip.lines - 1``, i.e. `[0,chip.lines)`.
43 Lines are requested from the chip using gpio-v2-get-line-ioctl.rst
51 ----------
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/Documentation/ABI/testing/
Dsysfs-class-hwmon16 The contents of the label are free-form.
135 this voltage channel is being used for, and user-space
137 user-space.
145 When disabled the sensor read will return -ENODATA.
147 - 1: Enable
148 - 0: Disable
156 - 1: Failed
157 - 0: Ok
262 Only makes sense if the chip supports closed-loop fan speed
272 this fan channel is being used for, and user-space doesn't.
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