Searched +full:quad +full:- +full:precision (Results 1 – 3 of 3) sorted by relevance
11 ---------------46 -------------56 -------------65 -------------------67 HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI71 ---------------------------------74 32-bit CPU77 64-bit CPU (userspace may be running in 32-bit mode).105 Embedded Floating Point single precision operations are available.108 Embedded Floating Point double precision operations are available.[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V ISA extensions10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>15 RISC-V has a large number of extensions, some of which are "standard"16 extensions, meaning they are ratified by RISC-V International, and others36 Identifies the specific RISC-V instruction set architecture[all …]
26 #. Increase code-reuse27 #. Increase overall code-maintainability67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin84 or the PCB traces insert the correct 1.5-2ns delay97 * PHY devices may offer sub-nanosecond granularity in how they allow a99 precision may be required to account for differences in PCB trace lengths115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are130 -----------------------------------------197 PHY-specific flags should be set in phydev->dev_flags prior to the call[all …]