Searched full:queues (Results 1 – 25 of 167) sorted by relevance
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| /Documentation/networking/ |
| D | multi-pf-netdev.rst | 63 Each combined channel works against one specific PF, creating all its datapath queues against it. We
126 that is capable of pointing to the receive queues of a different PF.
142 - /sys/class/net/eth2/queues/tx-0/xps_cpus:000001
143 - /sys/class/net/eth2/queues/tx-1/xps_cpus:001000
144 - /sys/class/net/eth2/queues/tx-2/xps_cpus:000002
145 - /sys/class/net/eth2/queues/tx-3/xps_cpus:002000
146 - /sys/class/net/eth2/queues/tx-4/xps_cpus:000004
147 - /sys/class/net/eth2/queues/tx-5/xps_cpus:004000
148 - /sys/class/net/eth2/queues/tx-6/xps_cpus:000008
149 - /sys/class/net/eth2/queues/tx-7/xps_cpus:008000
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| D | tc-queue-filters.rst | 7 TC can be used for directing traffic to either a set of queues or
12 1) TC filter directing traffic to a set of queues is achieved
14 the priority maps to a traffic class (set of queues) when
23 queues and/or a single queue are supported as below:
25 1) TC flower filter directs incoming traffic to a set of queues using
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| D | scaling.rst | 27 Contemporary NICs support multiple receive and transmit descriptor queues
29 queues to distribute processing among CPUs. The NIC distributes packets by
62 Some advanced NICs allow steering packets to queues based on
72 module parameter for specifying the number of hardware queues to
75 for each CPU if the device supports enough queues, or otherwise at least
81 default mapping is to distribute the queues evenly in the table, but the
84 indirection table could be done to give different queues different
95 of queues to IRQs can be determined from /proc/interrupts. By default,
110 is to allocate as many queues as there are CPUs in the system (or the
112 is likely the one with the smallest number of receive queues where no
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| D | multiqueue.rst | 18 the subqueue memory, as well as netdev configuration of where the queues
21 The base driver will also need to manage the queues as it does the global
33 A new round-robin qdisc, sch_multiq also supports multiple hardware queues. The
35 bands and queues based on the value in skb->queue_mapping. Use this field in
42 On qdisc load, the number of bands is based on the number of queues on the
56 The qdisc will allocate the number of bands to equal the number of queues that
58 queues, the band mapping would look like::
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| D | devmem.rst | 102 The user must bind a dmabuf to any number of RX queues on a given NIC using
106 struct netdev_queue *queues;
107 queues = malloc(sizeof(*queues) * 1);
109 queues[0]._present.type = 1;
110 queues[0]._present.idx = 1;
111 queues[0].type = NETDEV_RX_QUEUE_TYPE_RX;
112 queues[0].idx = 15;
119 __netdev_bind_rx_req_set_queues(req, queues, n_queue_index);
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| /Documentation/ABI/testing/ |
| D | sysfs-class-net-queues | 1 What: /sys/class/net/<iface>/queues/rx-<queue>/rps_cpus
11 What: /sys/class/net/<iface>/queues/rx-<queue>/rps_flow_cnt
19 What: /sys/class/net/<iface>/queues/tx-<queue>/tx_timeout
27 What: /sys/class/net/<iface>/queues/tx-<queue>/tx_maxrate
35 What: /sys/class/net/<iface>/queues/tx-<queue>/xps_cpus
45 What: /sys/class/net/<iface>/queues/tx-<queue>/xps_rxqs
56 What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/hold_time
65 What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/inflight
73 What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/limit
82 What: /sys/class/net/<iface>/queues/tx-<queue>/byte_queue_limits/limit_max
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| /Documentation/networking/device_drivers/ethernet/huawei/ |
| D | hinic.rst | 55 Asynchronous Event Queues(AEQs) - The event queues for receiving messages from
69 Completion Event Queues(CEQs) - The completion Event Queues that describe IO
72 Work Queues(WQ) - Contain the memory and operations for use by CMD queues and
77 Command Queues(CMDQ) - The queues for sending commands for IO management and is
82 Queue Pairs(QPs) - The HW Receive and Send queues for Receiving and Transmitting
104 Tx Queues - Logical Tx Queues that use the HW Send Queues for transmit.
108 Rx Queues - Logical Rx Queues that use the HW Receive Queues for receive.
112 hinic_dev - de/constructs the Logical Tx and Rx Queues.
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 9 management of the packet queues. Packets are queued/de-queued by writing or
32 -- managed-queues : the actual queues managed by each queue manager
33 instance, specified as <"base queue #" "# of queues">.
51 - qpend : pool of qpend(interruptible) queues
52 - general-purpose : pool of general queues, primarily used
53 as free descriptor queues or the
54 transmit DMA queues.
55 - accumulator : pool of queues on PDSP accumulator channel
57 -- qrange : number of queues to use per queue range, specified as
58 <"base queue #" "# of queues">.
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| /Documentation/devicetree/bindings/misc/ |
| D | intel,ixp4xx-ahb-queue-manager.yaml | 14 The IXP4xx AHB Queue Manager maintains queues as circular buffers in
17 IXP4xx for accelerating queues, especially for networking. Clients pick
18 queues from the queue manager with foo-queue = <&qmgr N> where the
33 - description: Interrupt for queues 0-31
34 - description: Interrupt for queues 32-63
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| /Documentation/arch/arm/keystone/ |
| D | knav-qmss.rst | 15 management of the packet queues. Packets are queued/de-queued by writing or
24 knav qmss driver provides a set of APIs to drivers to open/close qmss queues,
25 allocate descriptor pools, map the descriptors, push/pop to queues etc. For
31 Accumulator QMSS queues using PDSP firmware
34 queue or multiple contiguous queues. drivers/soc/ti/knav_qmss_acc.c is the
37 1 or 32 queues per channel. More description on the firmware is available in
56 Use of accumulated queues requires the firmware image to be present in the
57 file system. The driver doesn't acc queues to the supported queue range if
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| /Documentation/block/ |
| D | blk-mq.rst | 37 spawns multiple queues with individual entry points local to the CPU, removing
49 blk-mq has two group of queues: software staging queues and hardware dispatch
50 queues. When the request arrives at the block layer, it will try the shortest
56 Then, after the requests are processed by software queues, they will be placed
62 Software staging queues
65 The block IO subsystem adds requests in the software staging queues
71 the number of queues is defined by a per-CPU or per-node basis.
93 requests from different queues, otherwise there would be cache trashing and a
99 queue (a.k.a. run the hardware queue), the software queues mapped to that
102 Hardware dispatch queues
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| /Documentation/networking/device_drivers/ethernet/google/ |
| D | gve.rst | 47 - Transmit and Receive Queues
109 The handler for the management irq simply queues the service task in
115 the queues associated with that interrupt.
118 and poll the queues.
120 GQI Traffic Queues
122 GQI queues are composed of a descriptor ring and a buffer and are assigned to a
145 DQO Traffic Queues
149 - TX and RX buffers queues, which send descriptors to the device, use MMIO
152 - RX and TX completion queues, which receive descriptors from the device, use a
160 queues are not overrun. This can be accomplished by limiting the number of
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| /Documentation/devicetree/bindings/net/ |
| D | brcm,systemport.yaml | 25 - description: interrupt line for RX queues
26 - description: interrupt line for TX queues
54 Number of HW transmit queues
61 Number of HW receive queues
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| D | intel,dwmac-plat.yaml | 68 mtl_rx_setup: rx-queues-config {
69 snps,rx-queues-to-use = <2>;
84 mtl_tx_setup: tx-queues-config {
85 snps,tx-queues-to-use = <2>;
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| D | snps,dwmac.yaml | 188 Multiple RX Queues parameters. Phandle to a node that
189 implements the 'rx-queues-config' object described in
192 rx-queues-config:
195 snps,rx-queues-to-use:
197 description: number of RX queues to be used in the driver
314 Multiple TX Queues parameters. Phandle to a node that
315 implements the 'tx-queues-config' object described in
318 tx-queues-config:
321 snps,tx-queues-to-use:
323 description: number of TX queues to be used in the driver
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| /Documentation/devicetree/bindings/dma/ |
| D | fsl-qdma.yaml | 46 fsl,dma-queues:
48 description: Should contain number of queues supported.
68 based on queues
82 - fsl,dma-queues
133 fsl,dma-queues = <2>;
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| /Documentation/virt/gunyah/ |
| D | message-queue.rst | 3 Message Queues
8 IPC channel requires a pair of queues.
12 use case for message queues, and creates messages queues between itself and VMs
19 involves 2 message queues. Message queue 1 allows VM_A to send messages to VM_B.
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| /Documentation/networking/devlink/ |
| D | mlx5.rst | 108 Hairpin queues are mlx5 hardware specific implementation for hardware
111 Control the number of hairpin queues.
115 - Control the size (in packets) of the hairpin queues.
155 real time information of its send queues status.
159 - Diagnose send queues status::
175 - rx queues' initialization (population) timeout
176 Population of rx queues' descriptors on ring initialization is done
185 provides real time information of its receive queues' status.
187 - Diagnose rx queues' status and corresponding completion queue::
254 number of queues in an error state due to
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| /Documentation/devicetree/bindings/mfd/ |
| D | fsl-imx25-tsadc.txt | 3 This device combines two general purpose conversion queues one used for general
15 conversion queues.
20 This device includes two conversion queues which can be added as subnodes.
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| /Documentation/networking/device_drivers/ethernet/freescale/ |
| D | dpaa.rst | 86 Tx FQs transmission frame queues
143 confirmation frame queues. The driver is then responsible for freeing the
164 strict priority levels. Each traffic class contains NR_CPU TX queues. By
165 default, only one traffic class is enabled and the lowest priority Tx queues
184 Traffic coming on the DPAA Rx queues or on the DPAA Tx confirmation
185 queues is seen by the CPU as ingress traffic on a certain portal.
191 hardware frame queues using a hash on IP v4/v6 source and destination
195 queues are configured to put the received traffic into a pool channel
197 The default frame queues have the HOLDACTIVE option set, ensuring that
204 128 Rx frame queues that are configured to dedicated channels, in a
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| /Documentation/misc-devices/ |
| D | mrvl_cn10k_dpi.rst | 12 mailbox logic, and a set of DMA engines & DMA command queues.
20 the DMA engines and VF device's DMA command queues. Also, driver creates
25 queues and provisions the hardware resources, it cannot initiate any
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| /Documentation/networking/device_drivers/ethernet/ti/ |
| D | cpsw.rst | 26 - TX queues must be rated starting from txq0 that has highest priority
28 - CBS shapers should be used with rated queues
30 potential incoming rate, thus, rate of all incoming tx queues has
150 // Add 4 tx queues, for interface Eth0, and 1 tx queue for Eth1
156 // Check if num of queues is set correctly:
172 // TX queues must be rated starting from 0, so set bws for tx0 and tx1
175 // Leave last 2 tx queues not rated.
176 $ echo 40 > /sys/class/net/eth0/queues/tx-0/tx_maxrate
177 $ echo 20 > /sys/class/net/eth0/queues/tx-1/tx_maxrate
181 // Check maximum rate of tx (cpdma) queues:
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| /Documentation/networking/device_drivers/ethernet/intel/ |
| D | idpf.rst | 115 - The following examples are for queues 1 and 3, but you can adjust other
116 queues.
119 about 100,000 interrupts/second, for queues 1 and 3::
124 - To show the current coalesce settings for queues 1 and 3::
139 - Configure as many Rx/Tx queues in the VM as available. (See the idpf driver
140 documentation for the number of queues supported.) For example::
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| D | iavf.rst | 135 Application Device Queues (ADq)
137 Application Device Queues (ADq) allows you to dedicate one or more queues to a
158 Example: Sets up two tcs, tc0 and tc1, with 16 queues each and max tx rate set
164 queues 16@0 16@16 hw 1 mode channel shaper bw_rlimit min_rate 1Gbit 2Gbit
170 queues: for each tc, <num queues>@<offset> (e.g. queues 16@0 16@16 assigns
171 16 queues to tc0 at offset 0 and 16 queues to tc1 at offset 16. Max total
172 number of queues for all tcs is 64 or number of cores, whichever is lower.)
217 traffic will be duplicated and sent to all matching TC queues. The hardware
255 errors to stdout. Use a maximum of three queues to avoid this issue.
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| /Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| D | ethernet-driver.rst | 25 - queues, channels
32 hardware resources, like queues, do not have a corresponding MC object and
99 queues ---------------------- | | Buffer pool |
109 Frames are transmitted and received through hardware frame queues, which can be
111 enqueues TX frames on egress queues and after transmission is complete a TX
114 When frames are available on ingress queues, a data availability notification
116 queues in the same channel have available frames, only one notification is sent.
119 Each network interface can have multiple Rx, Tx and confirmation queues affined
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