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/Documentation/leds/
Dledtrig-usbport.rst2 USB port LED trigger
5 This LED trigger can be used for signalling to the user a presence of USB device
13 Please note that this trigger allows selecting multiple USB ports for a single
18 1) Device with single USB LED and few physical ports
28 port may be handled by ohci-platform, ehci-platform and xhci-hcd. If there is
32 This trigger can be activated from user space on led class devices as shown
35 echo usbport > trigger
38 Documentation/ABI/testing/sysfs-class-led-trigger-usbport
40 Example use-case::
42 echo usbport > trigger
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Dledtrig-oneshot.rst2 One-shot LED Trigger
5 This is a LED trigger useful for signaling the user of an event where there are
6 no clear trap points to put standard led-on and led-off settings. Using this
7 trigger, the application needs only to signal the trigger when an event has
8 happened, then the trigger turns the LED on and then keeps it off for a
11 This trigger is meant to be usable both for sporadic and dense events. In the
12 first case, the trigger produces a clear single controlled blink for each
16 A one-shot LED only stays in a constant state when there are no events. An
20 The trigger can be activated from user space on led class devices as shown
23 echo oneshot > trigger
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/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-cti1 What: /sys/bus/coresight/devices/<cti-name>/enable
7 What: /sys/bus/coresight/devices/<cti-name>/powered
13 What: /sys/bus/coresight/devices/<cti-name>/ctmid
19 What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons
25 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name
31 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals
35 Description: (Read) Input trigger signals from connected device <N>
37 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types
41 Description: (Read) Functional types for the input trigger signals
44 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_signals
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Dsysfs-class-led-trigger-usbport4 Contact: linux-leds@vger.kernel.org
5 linux-usb@vger.kernel.org
7 Every dir entry represents a single USB port that can be
8 selected for the USB port trigger. Selecting ports makes trigger
Dsysfs-bus-intel_th-devices-msc1 What: /sys/bus/intel_th/devices/<intel_th_id>-msc<msc-id>/wrap
7 What: /sys/bus/intel_th/devices/<intel_th_id>-msc<msc-id>/mode
13 - "single", for contiguous buffer mode (high-order alloc);
14 - "multi", for multiblock mode;
15 - "ExI", for DCI handler mode;
16 - "debug", for debug mode;
17 - any of the currently loaded buffer sinks.
23 What: /sys/bus/intel_th/devices/<intel_th_id>-msc<msc-id>/nr_pages
27 Description: (RW) Configure MSC buffer size for "single" or "multi" modes.
29 In single mode, this is a single number of pages, has to be
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Dsysfs-driver-w1_therm7 (typical -55 degC to 125 degC), if not values will be trimmed
11 master level, refer to Documentation/w1/w1-generic.rst for
21 (WO) writing that file will either trigger a save of the
41 * '-xx': xx is kernel error when reading power status
54 power is lost. Trigger a 'save' to EEPROM command to keep
55 values after power-on. Read or write are :
59 * '-xx': xx is kernel error when reading the resolution
62 Some DS18B20 clones are fixed in 12-bit resolution, so the
80 * If no bulk read has been triggered, it will trigger
115 (RW) trigger a bulk read conversion. read the status
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Dsysfs-bus-coresight-devices-etb106 source for a single sink.
18 following the trigger event. The number of 32-bit words written
19 into the Trace RAM following the trigger event is equal to the
20 value stored in this register+1 (from ARM ETB-TRM).
Dsysfs-bus-coresight-devices-etm3x25 processor context ID to trigger on, etc. Individual fields in
34 addresses to trigger on. Inclusion or exclusion is specified
41 Description: (RW) Used in conjunction with @addr_idx. Specifies the single
42 address to trigger on, highly influenced by the configuration
49 Description: (RW) Used in conjunction with @addr_idx. Specifies the single
57 Description: (RW) Used in conjunction with @addr_idx. Specifies the single
112 Description: (RW) Used with the ctxid_idx, specify with context ID to trigger
225 Description: (RW) Holds the trace synchronization frequency value - must be
246 Description: (RW) Define the event that controls the trigger.
/Documentation/trace/coresight/
Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
4 CoreSight Embedded Cross Trigger (CTI & CTM).
11 --------------------
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
15 devices and interconnects them via the Cross Trigger Matrix (CTM) to other
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
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/Documentation/devicetree/bindings/leds/
Dregulator-led.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/regulator-led.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 Regulator LEDs are powered by a single regulator such that they can
20 - $ref: common.yaml#
27 const: regulator-led
29 vled-supply:
35 linux,default-trigger: true
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Dregister-bit-led.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/register-bit-led.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 Register bit leds are used with syscon multifunctional devices where single
14 bits in a certain register can turn on/off a single LED. The register bit LEDs
20 - $ref: /schemas/leds/common.yaml#
25 The unit-address is in the form of @<reg addr>,<bit offset>
26 pattern: '^led@[0-9a-f]+,[0-9a-f]{1,2}$'
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/Documentation/devicetree/bindings/timer/
Dnvidia,tegra-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
21 # Either a single combined interrupt or up to 14 individual interrupts
27 - if:
31 - items:
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/Documentation/driver-api/
Dreset.rst1 .. SPDX-License-Identifier: GPL-2.0-only
13 the `consumer driver interface <#consumer-driver-interface>`__ (`API reference
14 <#reset-consumer-api>`__), which allows peripheral drivers to request control
16 <#reset-controller-driver-interface>`__ (`API reference
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
25 --------
37 Most commonly this is a single bit in reset controller register space that
39 is self-clearing and can be used to trigger a predetermined pulse on the
41 In more complicated reset controls, a single trigger action can launch a
61 trigger reset pulses, or to query reset line status.
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/Documentation/admin-guide/media/
Dmgb4.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------
13 There are two types of parameters - global / PCI card related, found under
23 | 0 - No module present
24 | 1 - FPDL3
25 | 2 - GMSL
33 | 1 - FPDL3
34 | 2 - GMSL
42 PRODUCT-REVISION-SERIES-SERIAL
55 | 0 - single
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/Documentation/devicetree/bindings/mfd/
Dmax77650.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MAX77650 ultra low-power PMIC from Maxim Integrated.
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
13 MAX77650 is an ultra-low power PMIC providing battery charging and power
14 supply for low-power IoT and wearable applications.
16 The GPIO-controller module is represented as part of the top-level PMIC
17 node. The device exposes a single GPIO line.
19 For device-tree bindings of other sub-modules (regulator, power supply,
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/Documentation/devicetree/bindings/gpio/
Dsprd,gpio-eic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/sprd,gpio-eic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
20 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
23 The EIC-debounce sub-module provides up to 8 source input signal
[all …]
/Documentation/devicetree/bindings/arm/
Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
19 output hardware trigger signals. CTIs can have a maximum number of input and
20 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
30 In general the connections between CTI and components via the trigger signals
[all …]
/Documentation/arch/arm/
Dcluster-pm-race-avoidance.rst2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
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/Documentation/i2c/
Dsmbus-protocol.rst24 single data byte, the functions using SMBus protocol operation names execute
60 This sends a single bit to the device, at the place of the Rd/Wr bit::
72 This reads a single byte from a device, without specifying a device
87 This operation is the reverse of Receive Byte: it sends a single byte
102 This reads a single byte from a device, from a designated register.
133 This writes a single byte to a device, to a designated register. The
207 SMBus Block Write - Block Read Process Call
210 SMBus Block Write - Block Read Process Call was introduced in
238 * I2C bus drivers trigger SMBus Host Notify by a call to
240 * I2C drivers for devices which can trigger SMBus Host Notify will have
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Dslave-testunit-backend.rst1 .. SPDX-License-Identifier: GPL-2.0
7 by Wolfram Sang <wsa@sang-engineering.com> in 2020
9 This backend can be used to trigger test cases for I2C bus masters which
11 easy to obtain). Examples include multi-master testing, and SMBus Host Notify
21 # echo "slave-testunit 0x1030" > /sys/bus/i2c/devices/i2c-0/new_device
30 compatible = "slave-testunit";
35 After that, you will have the device listening. Reading will return a single
39 When writing, the device consists of 4 8-bit registers and, except for some
43 .. csv-table::
46 0x00, CMD, which test to trigger
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/Documentation/trace/
Devents.rst24 ---------------------------------
59 ---------------------------
82 - 0 - all events this file affects are disabled
83 - 1 - all events this file affects are enabled
84 - X - there is a mixture of events enabled and disabled
85 - ? - this file does not affect any event
88 ---------------
92 trace_event=[event-list]
94 event-list is a comma separated list of events. See section 2.1 for event
97 3. Defining an event-enabled tracepoint
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Dhistogram-design.rst1 .. SPDX-License-Identifier: GPL-2.0
20 generally be truncated - only enough to make the point is displayed.
28 of the hist trigger internals described in this document. Specific
35 can do with histograms - create one with a single key on a single
38 # echo 'hist:keys=pid' >> events/sched/sched_waking/trigger
60 pid as a key and with a single value, hitcount, which even if not
63 The hitcount value is a per-bucket value that's automatically
86 (in most cases - some hist_fields such as hitcount don't directly map
87 to an event field in the trace buffer - in these cases the function
89 indicates which type of field it is - key, value, variable, variable
[all …]
/Documentation/accel/qaic/
Dqaic.rst1 .. SPDX-License-Identifier: GPL-2.0-only
14 --------------------
21 non-empty and generate MSIs at a rate equivalent to the speed of the
23 workload is known to trigger this condition, and can generate in excess of 100k
41 Single MSI Mode
42 ---------------
47 useful to be able to fall back to a single MSI when needed.
59 never disabled, allowing each new entry to the FIFO to trigger a new interrupt.
72 QAIC handles and enforces the required little endianness and 64-bit alignment,
100 all times. QAIC will trigger KOBJ_ONLINE/OFFLINE uevents to advertise when the
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/Documentation/devicetree/bindings/interrupt-controller/
Dinterrupts.txt5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
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/Documentation/hwmon/
Dasb100.rst6 * Asus ASB100 and ASB100-A "Bach"
17 -----------
19 This driver implements support for the Asus ASB100 and ASB100-A "Bach".
30 these, the ASB100-A also implements a single PWM controller for fans 2 and
48 - 0x0001 => in0 (?)
49 - 0x0002 => in1 (?)
50 - 0x0004 => in2
51 - 0x0008 => in3
52 - 0x0010 => temp1 [1]_
53 - 0x0020 => temp2
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