Searched +full:speed +full:- +full:map (Results 1 – 25 of 83) sorted by relevance
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| /Documentation/devicetree/bindings/hwmon/ |
| D | gpio-fan.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/hwmon/gpio-fan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 const: gpio-fan
18 Specifies the pins that map to bits in the control value,
19 ordered MSB-->LSB.
23 alarm-gpios:
26 gpio-fan,speed-map:
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| D | moortec,mr75203.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
19 *) Temperature Sensor (TS) - used to monitor core temperature (e.g. mr74137).
20 *) Voltage Monitor (VM) - used to monitor voltage levels (e.g. mr74138).
21 *) Process Detector (PD) - used to assess silicon speed (e.g. mr74139).
22 *) Delay Chain - ring oscillator connected to the PD, used to measure IO
25 *) Pre Scaler - provides divide-by-X scaling of input voltage, which can then
26 be presented for VM for measurement within its range (e.g. mr76006 -
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| /Documentation/devicetree/bindings/pci/ |
| D | intel-gw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
27 - const: snps,dw-pcie
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| D | toshiba,visconti-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
16 - $ref: /schemas/pci/snps,dw-pcie.yaml#
20 const: toshiba,visconti-pcie
24 - description: Data Bus Interface (DBI) registers.
25 - description: PCIe configuration space region.
26 - description: Visconti specific additional registers.
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| D | ti,am65-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - ti,am654-pcie-rc
20 - ti,keystone-pcie
25 reg-names:
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| D | aardvark-pci.txt | 8 - compatible: Should be "marvell,armada-3700-pcie"
9 - reg: range of registers for the PCIe controller
10 - interrupts: the interrupt line of the PCIe controller
11 - #address-cells: set to <3>
12 - #size-cells: set to <2>
13 - device_type: set to "pci"
14 - ranges: ranges for the PCI memory and I/O regions
15 - #interrupt-cells: set to <1>
16 - msi-controller: indicates that the PCIe controller can itself
18 - msi-parent: pointer to the MSI controller to be used
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| D | ti,j721e-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-host
17 - const: ti,j784s4-pcie-host
18 - description: PCIe controller in AM64
20 - const: ti,am64-pcie-host
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| D | rcar-gen4-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Renesas Electronics Corp.
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen4 PCIe Host
11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 - $ref: snps,dw-pcie.yaml#
19 - enum:
20 - renesas,r8a779f0-pcie # R-Car S4-8
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| D | mediatek-pcie-gen3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
14 and compatible with Gen2, Gen1 speed.
19 +-----+
21 +-----+
24 port->irq
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| D | nvidia,tegra194-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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| D | rockchip-dw-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
17 snps,dw-pcie.yaml.
20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
21 - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
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| D | apple,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <kettenis@openbsd.org>
22 the standard "reset-gpios" and "max-link-speed" properties appear on
34 - enum:
35 - apple,t8103-pcie
36 - apple,t8112-pcie
37 - apple,t6000-pcie
38 - const: apple,pcie
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| D | qcom,pcie-sm8450.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - qcom,pcie-sm8450-pcie0
21 - qcom,pcie-sm8450-pcie1
27 reg-names:
30 - const: parf # Qualcomm specific registers
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| /Documentation/devicetree/bindings/regulator/ |
| D | maxim,max8952.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: regulator.yaml#
19 max8952,default-mode:
25 max8952,dvs-mode-microvolt:
35 max8952,en-gpio:
40 max8952,ramp-speed:
45 Voltage ramp speed, values map to:
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| /Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| D | realtek,usb2phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <stanley_chang@realtek.com>
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
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| D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| /Documentation/bpf/ |
| D | map_bloom_filter.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
9 - ``BPF_MAP_TYPE_BLOOM_FILTER`` was introduced in kernel version 5.16
11 ``BPF_MAP_TYPE_BLOOM_FILTER`` provides a BPF bloom filter map. Bloom
12 filters are a space-efficient probabilistic data structure used to
16 The bloom filter map does not have keys, only values. When the bloom
17 filter map is created, it must be created with a ``key_size`` of 0. The
18 bloom filter map supports two operations:
20 - push: adding an element to the map
21 - peek: determining whether an element is present in the map
24 bloom filter map and ``bpf_map_peek_elem`` to query the map. These
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad9467.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD9467 and similar High-Speed ADCs
10 - Michael Hennerich <michael.hennerich@analog.com>
13 The AD9467 and the parts similar with it, are high-speed analog-to-digital
18 All the parts support the register map described by Application Note AN-877
19 https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
21 https://www.analog.com/media/en/technical-documentation/data-sheets/AD9265.pdf
22 https://www.analog.com/media/en/technical-documentation/data-sheets/AD9434.pdf
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| /Documentation/iio/ |
| D | iio_dmabuf_api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 High-speed DMABUF interface for IIO
11 file-based interface, with read() and write() access calls through the
20 zero-copy fashion, for instance between IIO and the USB stack.
22 The userspace application can also memory-map the DMABUF objects, and
25 kernel and userspace. This is particularly useful for high-speed devices
27 It does however increase the userspace-kernelspace synchronization
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| /Documentation/arch/m68k/ |
| D | buddha-driver.rst | 8 ------------------------------------------------------------------------
10 Register map of the Buddha IDE controller and the
11 Buddha-part of the Catweasel Zorro-II version
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
36 otherwise your chance is only 1:16 to find the board :-).
38 The local memory-map is even active when mapped to $e8:
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| /Documentation/devicetree/bindings/net/can/ |
| D | cc770.txt | 8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
12 to map the registers of the controller. The size is usually 0x80.
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
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| /Documentation/networking/device_drivers/ethernet/ti/ |
| D | cpsw.rst | 1 .. SPDX-License-Identifier: GPL-2.0
26 - TX queues must be rated starting from txq0 that has highest priority
27 - Traffic classes are used starting from 0, that has highest priority
28 - CBS shapers should be used with rated queues
29 - The bandwidth for CBS shapers has to be set a little bit more then
32 - Real rates can differ, due to discreetness
33 - Map skb-priority to txq is not enough, also skb-priority to l2 prio
34 map has to be created with ip or vconfig tool
35 - Any l2/socket prio (0 - 7) for classes can be used, but for
37 - only 2 classes tested: A and B, but checked and can work with more,
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| /Documentation/hwmon/ |
| D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
80 ------------------
82 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
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