Searched +full:src +full:- +full:ref +full:- +full:clk +full:- +full:mhz (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: MediaTek XS-PHY Controller11 - Chunfeng Yun <chunfeng.yun@mediatek.com>14 The XS-PHY controller supports physical layer functionality for USB3.118 ----------------------------------45 pattern: "^xs-phy@[0-9a-f]+$"49 - enum:50 - mediatek,mt3611-xsphy[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: MediaTek T-PHY Controller11 - Chunfeng Yun <chunfeng.yun@mediatek.com>14 The T-PHY controller supports physical layer functionality for a number of17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:19 -----------------------------------67 pattern: "^t-phy(@[0-9a-f]+)?$"[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NXP i.MX8MQ MIPI CSI-2 receiver10 - Martin Kepplinger <martin.kepplinger@puri.sm>12 description: |-13 This binding covers the CSI-2 RX PHY and host controller included in the20 - fsl,imx8mq-mipi-csi227 - description: core is the RX Controller Core Clock input. This clock[all …]