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/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
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Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
17 A hart context is a privilege mode in a hardware execution thread. For example,
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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/Documentation/hwmon/
Dsl28cpld.rst1 .. SPDX-License-Identifier: GPL-2.0-only
17 -----------
21 supervisor. In the future there might be other flavours and additional
24 The fan supervisor has a 7 bit counter register and a counter period of 1
25 second. If the 7 bit counter overflows, the supervisor will automatically
26 switch to x8 mode to support a wider input range at the loss of
30 -------------
/Documentation/arch/riscv/
Duabi.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Linux User ABI
7 ------------------------------------
14 #. Single-letter extensions come first, in canonical order.
17 #. All multi-letter extensions will be separated from other extensions by an
21 single-letter extensions and before any higher-privileged extensions.
29 #. Standard supervisor-level extensions (starting with 'S') will be listed
30 after standard unprivileged extensions. If multiple supervisor-level
33 #. Standard machine-level extensions (starting with 'Zxm') will be listed
34 after any lower-privileged, standard extensions. If multiple machine-level
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/Documentation/devicetree/bindings/riscv/
Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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/Documentation/devicetree/bindings/timer/
Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
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/Documentation/virt/kvm/x86/
Dhypercalls.rst1 .. SPDX-License-Identifier: GPL-2.0
8 KVM Hypercalls have a three-byte sequence of either the vmcall or the vmmcall
18 R2-R7 are used for parameters 1-6. In addition, R1 is used for hypercall
25 refer to Documentation/virt/kvm/s390/s390-diag.rst.
28 It uses R3-R10 and hypercall number in R11. R4-R11 are used as output registers.
31 KVM hypercalls uses 4 byte opcode, that are patched with 'hypercall-instructions'
33 For more information refer to Documentation/virt/kvm/ppc-pv.rst
37 number in $2 (v0). Up to four arguments may be placed in $4-$7 (a0-a3) and
50 ------------------------
58 ----------------
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/Documentation/arch/arm/nwfpe/
Dtodo.rst6 POW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - power
7 RPW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse power
8 POL{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - polar angle (arctan2)
10 LOG{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base 10
11 LGN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base e
12 EXP{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - exponent
13 SIN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - sine
14 COS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - cosine
15 TAN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - tangent
16 ASN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arcsine
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Dnetwinder-fpe.rst14 {P|M|Z} = {round to +infinity,round to -infinity,round to zero},
20 ------------------------------------------------------------
22 LDF/STF - load and store floating
30 LFM/SFM - load and store multiple floating
47 ----------------------------------------------------------------
62 RFC/WFC are fully implemented. RFC/WFC are supervisor only instructions, and
63 presently check the CPU mode, and do an invalid instruction trap if not called
64 from supervisor mode.
76 ---------------------------------------------------
80 ADF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - add
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/Documentation/userspace-api/
Dseccomp_filter.rst25 to time-of-check-time-of-use (TOCTOU) attacks that are common in system
46 An additional seccomp mode is added and is enabled using the same
65 call will return -1 and set errno to ``EINVAL``.
73 true, ``-EACCES`` will be returned. This requirement ensures that filter
82 The above call returns 0 on success and non-zero on error.
106 task without executing the system call. ``siginfo->si_call_addr``
108 ``siginfo->si_syscall`` and ``siginfo->si_arch`` will indicate which
111 instruction). The return value register will contain an arch-
112 dependent value -- if resuming execution, set it to something
114 it with ``-ENOSYS`` could overwrite some useful information.)
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/Documentation/ABI/testing/
Dsysfs-class-firmware-attributes1 What: /sys/class/firmware-attributes/*/attributes/*/
13 and will accept UTF-8 input.
21 - enumeration: a set of pre-defined valid values
22 - integer: a range of numerical values
23 - string
26 -----------------
27 - ordered-list - a set of ordered list valid values
54 "enumeration"-type specific properties:
59 semi-colon (``;``).
61 "integer"-type specific properties:
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/Documentation/devicetree/bindings/
Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
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/Documentation/virt/kvm/
Dppc-pv.rst1 .. SPDX-License-Identifier: GPL-2.0
35 'hypercall-instructions'. This property contains at most 4 opcodes that make
43 r0 - volatile
53 r12 - volatile
74 page that contains parts of supervisor visible register state. The guest can
79 MMU is enabled. The second parameter indicates the address in real mode, if
80 applicable to the target. For now, we always map the page to -4096. This way we
84 ld rX, -4096(0)
133 - MSR_EE
134 - MSR_RI
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Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
139 -----------------
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/Documentation/arch/powerpc/
Dultravisor.rst1 .. SPDX-License-Identifier: GPL-2.0
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
19 When enabled, PEF adds a new higher privileged mode, called Ultravisor
20 mode, to POWER architecture. Along with the new mode there is new
22 for short). Ultravisor mode is the highest privileged mode in POWER
25 +------------------+
29 +------------------+
30 | Supervisor |
31 +------------------+
33 +------------------+
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Dpapr_hcalls.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Hypercall Op-codes (hcalls)
10 Virtualization on 64-bit Power Book3S Platforms is based on the PAPR
11 specification [1]_ which describes the run-time environment for a guest
15 - **IBM PowerVM (PHYP)**: IBM's proprietary hypervisor that supports AIX,
16 IBM-i and Linux as supported guests (termed as Logical Partitions
19 - **Qemu/KVM**: Supports PPC64 linux guests running on a PPC64 linux host.
23 a *pSeries guest*. A pseries guest runs in a supervisor mode (HV=0) and must
39 and any in-arguments for the hcall are provided in registers *r4-r12*. If values
41 in Big-endian byte order.
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/Documentation/devicetree/bindings/cpu/
Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/Documentation/admin-guide/
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
45 If set to native, use the device's native backlight mode.
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