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/Documentation/devicetree/bindings/regulator/
Dqcom,rpm-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/qcom,rpm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 The regulator node houses sub-nodes for each regulator within the device.
16 Each sub-node is identified using the node's name, with valid values listed
28 l29, lvs1, lvs2, lvs3, lvs4, lvs5, lvs6, lvs7, usb-switch, hdmi-switch,
37 - Bjorn Andersson <andersson@kernel.org>
42 - qcom,rpm-pm8058-regulators
43 - qcom,rpm-pm8901-regulators
[all …]
/Documentation/devicetree/bindings/iio/frequency/
Dadi,admfm2000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/iio/frequency/adi,admfm2000.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kim Seer Paller <kimseer.paller@analog.com>
14 Dual microwave down converter module with input RF and LO frequency ranges
15 from 0.5 to 32 GHz and an output IF frequency range from 0.1 to 8 GHz.
22 - adi,admfm2000
24 '#address-cells':
27 '#size-cells':
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Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.
21 - adi,adrf6780
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
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Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,admv1014.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 24 GHz to 44 GHz frequency range.
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
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Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,admv1013.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 24 GHz to 44 GHz frequency range.
21 - adi,admv1013
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
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/Documentation/userspace-api/media/rc/
Dlirc-get-features.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
13 LIRC_GET_FEATURES - Get the underlying hardware device's features
41 .. _LIRC-CAN-REC-RAW:
47 .. _LIRC-CAN-REC-PULSE:
52 :ref:`LIRC_MODE_PULSE <lirc-mode-pulse>` can only be used for transmitting.
54 .. _LIRC-CAN-REC-MODE2:
59 :ref:`LIRC_MODE_MODE2 <lirc-mode-MODE2>` is used. This also implies
60 that :ref:`LIRC_MODE_SCANCODE <lirc-mode-SCANCODE>` is also supported,
62 :ref:`lirc_set_rec_mode` to switch modes.
64 .. _LIRC-CAN-REC-LIRCCODE:
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/Documentation/devicetree/bindings/soc/qcom/
Dqcom,rpm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Bjorn Andersson <andersson@kernel.org>
21 - qcom,rpm-apq8064
22 - qcom,rpm-msm8660
23 - qcom,rpm-msm8960
24 - qcom,rpm-ipq8064
25 - qcom,rpm-mdm9615
33 interrupt-names:
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/Documentation/devicetree/bindings/net/
Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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Dti,cpsw-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI SoC Ethernet Switch Controller (CPSW)
10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
15 communication and can be configured as an ethernet switch. It provides the
24 - const: ti,cpsw-switch
[all …]
Dcpsw.txt1 TI SoC Ethernet Switch Controller Device Tree Bindings
2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
[all …]
/Documentation/devicetree/bindings/i2c/
Dnuvoton,npcm7xx-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 slave mode. Each controller can switch between master and slave at run time
12 (i.e. IPMB mode). HW FIFO for TX and RX are supported.
15 - Tali Perry <tali.perry1@gmail.com>
20 - nuvoton,npcm750-i2c
21 - nuvoton,npcm845-i2c
33 clock-frequency:
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/Documentation/devicetree/bindings/net/dsa/
Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LAN937x Ethernet Switch Series
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
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Dmicrochip,ksz.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
11 - Woojung Huh <Woojung.Huh@microchip.com>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
[all …]
Dvitesse,vsc73xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
18 The currently supported switch chips are
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
[all …]
Drenesas,rzn1-a5psw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1 Advanced 5 ports ethernet switch
10 - Clément Léger <clement.leger@bootlin.com>
13 The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and
17 - $ref: dsa.yaml#/$defs/ethernet-ports
22 - enum:
23 - renesas,r9a06g032-a5psw
[all …]
Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP SJA1105 Automotive Ethernet Switch Family
10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
11 least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
16 - Vladimir Oltean <vladimir.oltean@nxp.com>
21 - nxp,sja1105e
22 - nxp,sja1105t
23 - nxp,sja1105p
[all …]
/Documentation/devicetree/bindings/usb/
Dsmsc,usb3503.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SMSC USB3503 High-Speed Hub Controller
10 - Dongjin Kim <tobetter@gmail.com>
15 - smsc,usb3503
16 - smsc,usb3503a
17 - smsc,usb3803
22 connect-gpios:
27 intn-gpios:
[all …]
/Documentation/devicetree/bindings/input/touchscreen/
Dcypress,cy8ctma340.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Javier Martinez Canillas <javier@dowhile0.org>
15 - Linus Walleij <linus.walleij@linaro.org>
18 - $ref: touchscreen.yaml#
26 - const: cypress,cy8ctma340
27 - const: cypress,cy8ctst341
28 - const: cypress,cyttsp-spi
31 - const: cypress,cyttsp-i2c
[all …]
/Documentation/networking/dsa/
Dsja1105.rst2 NXP SJA1105 switch driver
8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
[all …]
/Documentation/hwmon/
Dlm85.rst79 - Philip Pokorny <ppokorny@penguincomputing.com>,
80 - Frodo Looijaard <frodol@dds.nl>,
81 - Richard Barrington <rich_b_nz@clear.net.nz>,
82 - Margit Schubert-While <margitsw@t-online.de>,
83 - Justin Thiessen <jthiessen@penguincomputing.com>
86 -----------
92 The LM85 uses the 2-wire interface compatible with the SMBUS 2.0
94 temperatures and five (5) voltages. It has four (4) 16-bit counters for
127 ----------------
133 for 3-wire and 2-wire mode. For this reason, the 2-wire fan modes are not
[all …]
/Documentation/networking/
Dbonding.rst1 .. SPDX-License-Identifier: GPL-2.0
11 Corrections, HA extensions: 2000/10/03-15:
13 - Willy Tarreau <willy at meta-x.org>
14 - Constantine Gavrilov <const-g at xpert.com>
15 - Chad N. Tindel <ctindel at ieee dot org>
16 - Janice Girouard <girouard at us dot ibm dot com>
17 - Jay Vosburgh <fubar at us dot ibm dot com>
22 - Mitch Williams <mitch.a.williams at intel.com>
29 The behavior of the bonded interfaces depends upon the mode; generally
35 the original tools from extreme-linux and beowulf sites will not work
[all …]
/Documentation/admin-guide/media/
Dvivid.rst1 .. SPDX-License-Identifier: GPL-2.0
13 Each input can be a webcam, TV capture device, S-Video capture device or an HDMI
14 capture device. Each output can be an S-Video output device or an HDMI output
23 - Support for read()/write(), MMAP, USERPTR and DMABUF streaming I/O.
24 - A large list of test patterns and variations thereof
25 - Working brightness, contrast, saturation and hue controls
26 - Support for the alpha color component
27 - Full colorspace support, including limited/full RGB range
28 - All possible control types are present
29 - Support for various pixel aspect ratios and video aspect ratios
[all …]
/Documentation/misc-devices/
Doxsemi-tornado.rst1 .. SPDX-License-Identifier: GPL-2.0
11 frequency by dividing it by the clock prescaler, which can be set to any
12 value from 1 to 63.875 in increments of 0.125, and then the usual 16-bit
13 divisor is used as with the original 8250, to divide the frequency by a
15 that can take any value from 4 to 16 to divide the frequency further and
20 set to 33.875, meaning that the frequency to be used as the reference
21 for the usual 16-bit divisor is 115313.653, which is close enough to the
22 frequency of 115200 used by the original 8250 for the same values to be
28 [OX954]_ [OX958]_. To switch away from the default value of 33.875 for
29 the prescaler the enhanced mode has to be explicitly enabled though, by
[all …]
/Documentation/devicetree/bindings/input/
Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 - $ref: input.yaml#
16 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
17 additional Hall-effect and inductive sensing capabilities.
24 - azoteq,iqs269a
25 - azoteq,iqs269a-00
26 - azoteq,iqs269a-d0
[all …]
/Documentation/admin-guide/pm/
Dintel_pstate.rst1 .. SPDX-License-Identifier: GPL-2.0
22 Documentation/admin-guide/pm/cpufreq.rst if you have not done that yet.]
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
25 than just an operating frequency or an operating performance point (see the
27 information about that). For this reason, the representation of P-states used
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
43 time the corresponding CPU is taken offline and need to be re-initialized when
47 only way to pass early-configuration-time parameters to it is via the kernel
58 active mode, it uses its own internal performance scaling governor algorithm or
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