Searched +full:system +full:- +full:on +full:- +full:a +full:- +full:chip (Results 1 – 25 of 257) sorted by relevance
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| /Documentation/hwmon/ |
| D | max16065.rst | 11 Addresses scanned: -
15 http://datasheets.maxim-ic.com/en/ds/MAX16065-MAX16066.pdf
21 Addresses scanned: -
25 http://datasheets.maxim-ic.com/en/ds/MAX16067.pdf
31 Addresses scanned: -
35 http://datasheets.maxim-ic.com/en/ds/MAX16068.pdf
41 Addresses scanned: -
45 http://datasheets.maxim-ic.com/en/ds/MAX16070-MAX16071.pdf
47 Author: Guenter Roeck <linux@roeck-us.net>
51 -----------
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| D | tmp513.rst | 1 .. SPDX-License-Identifier: GPL-2.0
22 Eric Tremblay <etremblay@distech-controls.com>
25 -----------
28 The TMP512 (dual-channel) and TMP513 (triple-channel) are system monitors
29 that include remote sensors, a local temperature sensor, and a high-side current
30 shunt monitor. These system monitors have the capability of measuring remote
31 temperatures, on-chip temperatures, and system voltage/power/current
34 The temperatures are measured in degrees Celsius with a range of
35 -40 to + 125 degrees with a resolution of 0.0625 degree C.
39 hysteresis value. The hysteresis is in degrees Celsius with a range of
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| D | adm1025.rst | 10 Addresses scanned: I2C 0x2c - 0x2e
18 Addresses scanned: I2C 0x2c - 0x2d
24 * Only two possible addresses (0x2c - 0x2d).
29 - Chen-Yuan Wu <gwu@esoft.com>,
30 - Jean Delvare <jdelvare@suse.de>
33 -----------
35 (This is from Analog Devices.) The ADM1025 is a complete system hardware
36 monitor for microprocessor-based systems, providing measurement and limit
37 comparison of various system parameters. Five voltage measurement inputs
39 the processor core voltage. The ADM1025 can monitor a sixth power-supply
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| D | wm831x.rst | 1 Kernel driver wm831x-hwmon
11 - http://www.wolfsonmicro.com/products/WM8310
12 - http://www.wolfsonmicro.com/products/WM8311
13 - http://www.wolfsonmicro.com/products/WM8312
18 -----------
21 monitor a range of system operating parameters, including the voltages
22 of the major supplies within the system. Currently the driver provides
26 ------------------
28 Voltages are sampled by a 12 bit ADC. Voltages in millivolts are 1.465
32 ----------------------
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| D | adt7462.rst | 17 -----------
19 This driver implements support for the Analog Devices ADT7462 chip family.
21 This chip is a bit of a beast. It has 8 counters for measuring fan speed. It
23 two. See the chip documentation for more details about the exact set of
24 configurations. This driver does not allow one to configure the chip; that is
25 left to the system designer.
27 A sophisticated control system for the PWM outputs is designed into the ADT7462
28 that allows fan speed to be adjusted automatically based on any of the three
43 ----------------
45 The ADT7462 have a 10-bit ADC and can therefore measure temperatures
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| D | pc87427.rst | 16 Thanks to Amir Habibi at Candelis for setting up a test system, and to
21 -----------
23 The National Semiconductor Super I/O chip includes complete hardware
28 This chip also has fan controlling features (up to 4 PWM outputs),
31 The driver assumes that no more than one chip is present, which seems
36 --------------
38 Fan rotation speeds are reported as 14-bit values from a gated clock
41 An alarm is triggered if the rotation speed drops below a programmable
47 -----------------
50 always off, always on, manual and automatic. The latter isn't supported
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| D | adt7475.rst | 12 Datasheet: Publicly available at the On Semiconductors website
20 Datasheet: Publicly available at the On Semiconductors website
28 Datasheet: Publicly available at the On Semiconductors website
36 Datasheet: Publicly available at the On Semiconductors website
39 - Jordan Crouse
40 - Hans de Goede
41 - Darrick J. Wong (documentation)
42 - Jean Delvare
46 -----------
49 ADT7476 and ADT7490 chip family. The ADT7473 and ADT7475 differ only in
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| /Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
13 creating a common ground for discussion, terms and their definitions
18 The individual DRAM chips on a memory stick. These devices commonly
25 A printed circuit board that aggregates multiple memory devices in
32 A physical connector on the motherboard that accepts a single memory
33 stick. Also called as "slot" on several datasheets.
37 A memory controller channel, responsible to communicate with a group of
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
50 of correcting more errors than on single mode.
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| D | sm501.rst | 9 The Silicon Motion SM501 multimedia companion chip is a multifunction device
11 asynchronous serial ports, audio functions, and a dual display video interface.
15 ----
23 chips via the platform device and driver system.
25 On detection of a device, the core initialises the chip (which may
29 The core re-uses the platform device system as the platform device
30 system provides enough features to support the drivers without the
31 need to create a new bus-type and the associated code to go with it.
35 ---------
37 Each peripheral has a view of the device which is implicitly narrowed to
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| /Documentation/devicetree/bindings/arm/ |
| D | syna.txt | 3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
9 Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
18 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
20 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
26 model = "Sony NSZ-GS7";
27 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
34 CPU control register allows various operations on CPUs, like resetting them
38 - compatible: should be "marvell,berlin-cpu-ctrl"
39 - reg: address and length of the register set
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | pmc.txt | 4 - compatible: "fsl,<chip>-pmc".
6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
7 compatible. "fsl,mpc8313-pmc" should also be listed for any chip
8 whose PMC is compatible, and implies deep-sleep capability.
10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
11 compatible. "fsl,mpc8536-pmc" should also be listed for any chip
12 whose PMC is compatible, and implies deep-sleep capability.
14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
15 compatible; all statements below that apply to "fsl,mpc8548-pmc" also
16 apply to "fsl,mpc8641d-pmc".
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| /Documentation/scsi/ |
| D | 53c700.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 This driver supports the 53c700 and 53c700-66 chips. It also supports
12 does sync (-66 and 710 only), disconnects and tag command queueing.
14 Since the 53c700 must be interfaced to a bus, you need to wrapper the
25 A compile time flag is::
29 define if the chipset must be supported in little endian mode on a big
30 endian architecture (used for the 700 on parisc).
33 Using the Chip Core Driver
36 In order to plumb the 53c700 chip core driver into a working SCSI
37 driver, you need to know three things about the way the chip is wired
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-hv_24x7 | 3 Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
4 Description: Read-only. Attribute group to describe the magic bits
5 that go into perf_event_attr.config for a particular pmu.
6 (See ABI/testing/sysfs-bus-event_source-devices-format).
8 Each attribute under this group defines a bit range of the
12 chip = "config:16-31"
13 core = "config:16-31"
14 domain = "config:0-3"
15 lpar = "config:0-15"
16 offset = "config:32-63"
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| /Documentation/devicetree/bindings/bus/ |
| D | socionext,uniphier-system-bus.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier System Bus
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
12 some control signals. It supports up to 8 banks (chip selects).
16 within each bank to the CPU-viewed address. The needed setup includes the
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
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| /Documentation/networking/device_drivers/atm/ |
| D | iphase.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ATM (i)Chip IA Linux Driver Source
9 --------------------------------------------------------------------------------
13 --------------------------------------------------------------------------------
18 This is the README file for the Interphase PCI ATM (i)Chip IA Linux driver
23 - A single VPI (VPI value of 0) is supported.
24 - Supports 4K VCs for the server board (with 512K control memory) and 1K
26 - UBR, ABR and CBR service categories are supported.
27 - Only AAL5 is supported.
28 - Supports setting of PCR on the VCs.
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| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr-channel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR channel with chip/rank topology description
10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
11 CK, etc.) that connect one or more LPDDR chips to a host system. The main
12 purpose of this node is to overall LPDDR topology of the system, including the
13 amount of individual LPDDR chips and the ranks per chip.
16 - Julius Werner <jwerner@chromium.org>
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| /Documentation/driver-api/gpio/ |
| D | drivers-on-gpio.rst | 6 the right in-kernel and userspace APIs/ABIs for the job, and that these
10 - leds-gpio: drivers/leds/leds-gpio.c will handle LEDs connected to GPIO
13 - ledtrig-gpio: drivers/leds/trigger/ledtrig-gpio.c will provide a LED trigger,
14 i.e. a LED will turn on/off in response to a GPIO line going high or low
15 (and that LED may in turn use the leds-gpio as per above).
17 - gpio-keys: drivers/input/keyboard/gpio_keys.c is used when your GPIO line
18 can generate interrupts in response to a key press. Also supports debounce.
20 - gpio-keys-polled: drivers/input/keyboard/gpio_keys_polled.c is used when your
22 by a timer.
24 - gpio_mouse: drivers/input/mouse/gpio_mouse.c is used to provide a mouse with
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| D | using-gpio.rst | 12 Documentation/driver-api/gpio/drivers-on-gpio.rst
14 For any kind of mass produced system you want to support, such as servers,
18 help to refine it, see Documentation/process/submitting-patches.rst.
20 In Linux GPIO lines also have a userspace ABI.
22 The userspace ABI is intended for one-off deployments. Examples are prototypes,
24 industrial automation, PLC-type use cases, door controllers, in short a piece
26 operators to have a deep knowledge of the equipment and knows about the
27 software-hardware interface to be set up. They should not have a natural fit
28 to any existing kernel subsystem and not be a good fit for an operating system,
29 because of not being reusable or abstract enough, or involving a lot of non
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| /Documentation/devicetree/bindings/rtc/ |
| D | isil,isl12057.txt | 1 Intersil ISL12057 I2C RTC/Alarm chip
3 ISL12057 is a trivial I2C device (it has simple device tree bindings,
4 consisting of a compatible field, an address and possibly an interrupt
8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
13 RTC alarm rings. In order to mark the device has a wakeup source and
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
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| /Documentation/devicetree/bindings/devfreq/event/ |
| D | samsung,exynos-nocp.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos NoC (Network on Chip) Probe
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
16 that the Network on Chip (NoC) probes detects are transported over the
18 packets with header or data on the data request response network, or as
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| /Documentation/devicetree/bindings/hwmon/ |
| D | ibm,occ-hwmon.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/hwmon/ibm,occ-hwmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: IBM On-Chip Controller (OCC) accessed from a service processor
10 - Eddie James <eajames@linux.ibm.com>
13 The POWER processor On-Chip Controller (OCC) helps manage power and
14 thermals for the system. A service processor or baseboard management
21 - ibm,p9-occ-hwmon
22 - ibm,p10-occ-hwmon
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| /Documentation/sound/soc/ |
| D | overview.rst | 5 The overall project goal of the ALSA System on Chip (ASoC) layer is to
6 provide better ALSA support for embedded system-on-chip processors (e.g.
9 had some limitations:-
12 CPU. This is not ideal and leads to code duplication - for example,
17 event). These are quite common events on portable devices and often require
18 machine specific code to re-route audio, enable amps, etc., after such an
22 recording) audio. This is fine for a PC, but tends to waste a lot of
23 power on portable devices. There was also no support for saving
31 features :-
33 * Codec independence. Allows reuse of codec drivers on other platforms
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| /Documentation/power/regulator/ |
| D | design.rst | 5 This document provides a brief, partially structured, overview of some
9 ------
11 - Errors in regulator configuration can have very serious consequences
12 for the system, potentially including lasting hardware damage.
13 - It is not possible to automatically determine the power configuration
14 of the system - software-equivalent variants of the same chip may
21 specific knowledge that these changes are safe to perform on this
22 particular system.
25 ------------------
27 - The overwhelming majority of devices in a system will have no
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| /Documentation/devicetree/bindings/fsi/ |
| D | ibm,p9-occ.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fsi/ibm,p9-occ.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: IBM FSI-attached On-Chip Controller (OCC)
10 - Eddie James <eajames@linux.ibm.com>
13 The POWER processor On-Chip Controller (OCC) helps manage power and
14 thermals for the system, accessed through the FSI-attached SBEFIFO
15 from a service processor.
20 - ibm,p9-occ
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| /Documentation/devicetree/bindings/watchdog/ |
| D | aspeed,ast2400-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/aspeed,ast2400-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
15 - aspeed,ast2400-wdt
16 - aspeed,ast2500-wdt
17 - aspeed,ast2600-wdt
29 aspeed,reset-type:
32 - cpu
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