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Searched full:timer1 (Results 1 – 17 of 17) sorted by relevance

/Documentation/devicetree/bindings/timer/
Dezchip,nps400-timer1.txt5 - compatible : should be "ezchip,nps400-timer1"
7 Clocks required for compatible = "ezchip,nps400-timer1":
13 compatible = "ezchip,nps400-timer1";
Dsnps,arc-timer.txt4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
6 TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)
24 timer1 {
Dcirrus,clps711x-timer.txt13 timer0 = &timer1;
14 timer1 = &timer2;
17 timer1: timer@80000300 {
Dactions,owl-timer.txt10 "timer0", "timer1", "timer2", "timer3"
20 interrupt-names = "timer0", "timer1";
Drealtek,otto-timer.yaml29 - description: timer1 registers
40 - description: timer1 interrupt
Darm,sp804.yaml56 be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
96 clock-names = "timer1", "timer2", "apb_pclk";
Dmarvell,orion-timer.txt6 - interrupts: should contain the interrupts for Timer0 and Timer1
Darm,mps2-timer.txt16 timer1: mps2-timer@40000000 {
Dingenic,tcu.yaml178 - const: timer1
289 clock-names = "timer0", "timer1", "timer2", "timer3",
Dti,timer-dm.yaml151 timer1: timer@0 {
/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic-timer.txt31 timer1: timer@42100 {
/Documentation/devicetree/bindings/reset/
Dnxp,lpc1850-rgu.txt34 33 Timer1
/Documentation/devicetree/bindings/soc/mobileye/
Dmobileye,eyeq5-olb.yaml67 timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,
100 const: timer1
/Documentation/devicetree/bindings/interrupt-controller/
Dbrcm,bcm2835-armctrl-ic.txt46 1: TIMER1
/Documentation/devicetree/bindings/pinctrl/
Dcirrus,madera.yaml70 spk-overheat-warn, timer1-sts, timer2-sts,
/Documentation/devicetree/bindings/clock/
Dst,stm32mp25-rcc.yaml112 - description: CK_SCMI_TIMG1 Peripheral bridge for timer1
/Documentation/devicetree/bindings/display/msm/
Ddsi-controller-main.yaml177 - timer1