Searched +full:tlb +full:- +full:split (Results 1 – 10 of 10) sorted by relevance
| /Documentation/admin-guide/mm/ |
| D | transhuge.rst | 26 requiring larger clear-page copy-page in page faults which is a
36 1) the TLB miss will run faster (especially with virtualization using
40 2) a single TLB entry will be mapping a much larger amount of virtual
41 memory in turn reducing the number of TLB misses. With
42 virtualization and nested pagetables the TLB can be mapped of
45 the two is using hugepages just because of the fact the TLB miss is
48 Modern kernels support "multi-size THP" (mTHP), which introduces the
50 but smaller than traditional PMD-size (as described above), in
51 increments of a power-of-2 number of pages. mTHP can back anonymous
53 PTE-mapped, but in many cases can still provide similar benefits to
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| D | hugetlbpage.rst | 13 256M and ppc64 supports 4K and 16M. A TLB is a cache of virtual-to-physical
15 Operating systems try to make best use of limited number of TLB resources.
93 Once a number of huge pages have been pre-allocated to the kernel huge page
169 indicates the current number of pre-allocated huge pages of the default size.
180 task that modifies ``nr_hugepages``. The default for the allowed nodes--when the
181 task has default memory policy--is all on-line nodes with memory. Allowed
206 requested by applications. Writing any non-zero value into this file
226 of the in-use huge pages to surplus huge pages. This will occur even if
228 this condition holds--that is, until ``nr_hugepages+nr_overcommit_hugepages`` is
229 increased sufficiently, or the surplus huge pages go out of use and are freed--
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| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| /Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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| /Documentation/arch/powerpc/ |
| D | kaslr-booke32.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 map or copy kernel to a proper place and relocate. Freescale Book-E
15 parts expect lowmem to be mapped by fixed TLB entries(TLB1). The TLB1
22 pass entropy via the /chosen/kaslr-seed node in device tree.
25 image. The memory will be split in 64M zones. We will use the lower 8
31 |--> 64M <--|
33 +---------------+ +----------------+---------------+
35 +---------------+ +----------------+---------------+
37 |-----> offset <-----|
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| /Documentation/admin-guide/hw-vuln/ |
| D | multihit.rst | 6 instruction fetch hits multiple entries in the instruction TLB. This can
13 -------------------
18 - non-Intel processors
20 - Some Atoms (Airmont, Bonnell, Goldmont, GoldmontPlus, Saltwell, Silvermont)
22 - Intel processors that have the PSCHANGE_MC_NO bit set in the
27 ------------
32 CVE-2018-12207 Machine Check Error Avoidance on Page Size Change
37 -------
42 the illusion of a very large memory for processors. This virtual space is split
47 processors include a structure, called TLB, that caches recent translations.
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| /Documentation/mm/ |
| D | highmem.rst | 23 VM space so that we don't have to pay the full TLB invalidation costs for
27 The traditional split for architectures using this approach is 3:1, 3GiB for
30 +--------+ 0xffffffff
32 +--------+ 0xc0000000
36 +--------+ 0x00000000
39 time, but because we need virtual address space for other things - including
40 temporary maps to access the rest of the physical memory - the actual direct
54 * kmap_local_page(), kmap_local_folio() - These functions are used to create
64 These mappings are thread-local and CPU-local, meaning that the mapping
68 CPU-hotplug until the mapping is disposed.
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| /Documentation/virt/kvm/ |
| D | api.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
139 -----------------
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| /Documentation/RCU/ |
| D | RTFP.txt | 4 This document describes RCU-related publications, and is followed by
19 with short-lived threads, such as the K42 research operating system.
20 However, Linux has long-lived tasks, so more is needed.
23 serialization, which is an RCU-like mechanism that relies on the presence
27 that these overheads were not so expensive in the mid-80s. Nonetheless,
28 passive serialization appears to be the first deferred-destruction
30 has lapsed, so this approach may be used in non-GPL software, if desired.
34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
36 this paper helped inspire the update-side batching used in the later
38 a description of Argus that noted that use of out-of-date values can
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
73 Documentation/firmware-guide/acpi/debug.rst for more information about
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