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/Documentation/devicetree/bindings/mfd/
Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
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Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
16 - basic timers consist of a 16-bit auto-reload counter driven by a
20 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
24 const: st,stm32-timers
32 clock-names:
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Dmax77650.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MAX77650 ultra low-power PMIC from Maxim Integrated.
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
13 MAX77650 is an ultra-low power PMIC providing battery charging and power
14 supply for low-power IoT and wearable applications.
16 The GPIO-controller module is represented as part of the top-level PMIC
19 For device-tree bindings of other sub-modules (regulator, power supply,
21 sub-system directories.
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/Documentation/devicetree/bindings/arm/
Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
19 output hardware trigger signals. CTIs can have a maximum number of input and
20 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
30 In general the connections between CTI and components via the trigger signals
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/Documentation/devicetree/bindings/spi/
Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
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/Documentation/devicetree/bindings/leds/
Dleds-lm3697.txt1 * Texas Instruments - LM3697 Highly Efficient White LED Driver
3 The LM3697 11-bit LED driver provides high-
10 - compatible:
12 - reg : I2C slave address
13 - #address-cells : 1
14 - #size-cells : 0
17 - enable-gpios : GPIO pin to enable/disable the device
18 - vled-supply : LED supply
21 - reg : 0 - LED is Controlled by bank A
22 1 - LED is Controlled by bank B
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Dleds-lp8860.txt1 * Texas Instruments - lp8860 4-Channel LED Driver
3 The LP8860-Q1 is an high-efficiency LED
4 driver with boost controller. It has 4 high-precision
9 - compatible :
11 - reg : I2C slave address
12 - #address-cells : 1
13 - #size-cells : 0
16 - enable-gpios : gpio pin to enable (active high)/disable the device.
17 - vled-supply : LED supply
20 - reg : 0
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Dcommon.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
25 led-sources:
30 $ref: /schemas/types.yaml#/definitions/uint32-array
35 from the header include/dt-bindings/leds/common.h. If there is no
42 the header include/dt-bindings/leds/common.h. If there is no matching
48 function-enumerator:
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Dleds-mt6323.txt5 PMIC controller that is being defined as one kind of Muti-Function Device (MFD)
15 - compatible : Must be one of
16 - "mediatek,mt6323-led"
17 - "mediatek,mt6331-led"
18 - "mediatek,mt6332-led"
19 - address-cells : Must be 1
20 - size-cells : Must be 0
22 Each led is represented as a child node of the mediatek,mt6323-led that
27 - reg : LED channel number (0..3)
30 - label : See Documentation/devicetree/bindings/leds/common.txt
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Dleds-lm36274.txt1 * Texas Instruments LM36274 4-Channel LCD Backlight Driver w/Integrated Bias
3 The LM36274 is an integrated four-channel WLED driver and LCD bias supply.
5 up to 29V total output voltage. The 11-bit LED current is programmable via
9 Documentation/devicetree/bindings/mfd/ti-lmu.txt
12 Documentation/devicetree/bindings/regulator/lm363x-regulator.txt
15 - compatible:
16 "ti,lm36274-backlight"
17 - reg : 0
18 - #address-cells : 1
19 - #size-cells : 0
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Dleds-pca955x.txt1 * NXP - pca955x LED driver
5 be input or output, and output pins can also be pulse-width controlled.
8 - compatible : should be one of :
14 - #address-cells: must be 1
15 - #size-cells: must be 0
16 - reg: I2C slave address. depends on the model.
19 - gpio-controller: allows pins to be used as GPIOs.
20 - #gpio-cells: must be 2.
21 - gpio-line-names: define the names of the GPIO lines
23 LED sub-node properties:
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Dleds-netxbig.txt5 - compatible: "lacie,netxbig-leds".
6 - gpio-ext: Phandle for the gpio-ext bus.
9 - timers: Timer array. Each timer entry is represented by three integers:
10 Mode (gpio-ext bus), delay_on and delay_off.
12 Each LED is represented as a sub-node of the netxbig-leds device.
14 Required sub-node properties:
15 - mode-addr: Mode register address on gpio-ext bus.
16 - mode-val: Mode to value mapping. Each entry is represented by two integers:
17 A mode and the corresponding value on the gpio-ext bus.
18 - bright-addr: Brightness register address on gpio-ext bus.
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Dleds-tlc591xx.txt4 - compatible: should be "ti,tlc59116" or "ti,tlc59108"
5 - #address-cells: must be 1
6 - #size-cells: must be 0
7 - reg: typically 0x68
9 Each led is represented as a sub-node of the ti,tlc59116.
12 LED sub-node properties:
13 - reg: number of LED line, 0 to 15 or 0 to 7
14 - label: (optional) name of LED
15 - linux,default-trigger : (optional)
20 #address-cells = <1>;
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/Documentation/firmware-guide/acpi/apei/
Deinj.rst1 .. SPDX-License-Identifier: GPL-2.0
15 which shows that the BIOS is exposing an EINJ table - it is the
43 - available_error_type
51 0x00000002 Processor Uncorrectable non-fatal
54 0x00000010 Memory Uncorrectable non-fatal
57 0x00000080 PCI Express Uncorrectable non-fatal
60 0x00000400 Platform Uncorrectable non-fatal
67 - error_type
72 - error_inject
74 Write any integer to this file to trigger the error injection. Make
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/Documentation/leds/
Dleds-blinkm.rst5 The leds-blinkm driver supports the devices of the BlinkM family.
7 They are RGB-LED modules driven by a (AT)tiny microcontroller and
8 communicate through I2C. The default address of these modules is
10 daisy-chain up to 127 BlinkMs on an I2C bus.
16 The interface this driver provides is 3-fold:
23 blinkm-<i2c-bus-nr>-<i2c-device-nr>:rgb:indicator
25 $ ls -h /sys/class/leds/blinkm-1-9:rgb:indicator
26 …brightness device max_brightness multi_index multi_intensity power subsystem trigger uevent
45 blinkm-<i2c-bus-nr>-<i2c-device-nr>-<color>
47 $ ls -h /sys/class/leds/blinkm-6-*
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/Documentation/devicetree/bindings/gpio/
Dsprd,gpio-eic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/sprd,gpio-eic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
20 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
23 The EIC-debounce sub-module provides up to 8 source input signal
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Dgpio-altera.txt4 - compatible:
5 - "altr,pio-1.0"
6 - reg: Physical base address and length of the controller's registers.
7 - #gpio-cells : Should be 2
8 - The first cell is the gpio offset number.
9 - The second cell is reserved and is currently unused.
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - interrupt-controller: Mark the device node as an interrupt controller
12 - #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
13 - The first cell is the GPIO offset number within the GPIO controller.
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/Documentation/devicetree/bindings/iio/adc/
Datmel,sama5d2-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/atmel,sama5d2-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugen Hristev <eugen.hristev@microchip.com>
15 - atmel,sama5d2-adc
16 - microchip,sam9x60-adc
17 - microchip,sama7g5-adc
28 clock-names:
31 vref-supply: true
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/Documentation/devicetree/bindings/dma/ti/
Dk3-bcdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/dma/ti/k3-bcdma.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Peter Ujfalusi <peter.ujfalusi@gmail.com>
16 mode channels of K3 UDMA-P.
23 Split channels can be used to service PSI-L based peripherals.
24 The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
25 with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
34 - ti,am62a-dmss-bcdma-csirx
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/Documentation/ABI/testing/
Ddebugfs-driver-dcc9 What: /sys/kernel/debug/dcc/.../trigger
14 triggers. The trigger can be invoked by writing '1'
27 What: /sys/kernel/debug/dcc/.../[list-number]/config
35 write, read-write, and loop type. The lists need to
45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config
50 The address to be read.
53 The addresses word count, starting from address <1>.
65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config
70 The address to be written.
78 iii) Read-write instruction
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/Documentation/devicetree/bindings/input/
Dtca8418_keypad.txt1 This binding is based on the matrix-keymap binding with the following
4 keypad,num-rows and keypad,num-columns are required.
7 - compatible: "ti,tca8418"
8 - reg: the I2C address
9 - interrupts: IRQ line number, should trigger on falling edge
10 - linux,keymap: Keys definitions, see keypad-matrix.
/Documentation/input/
Dgameport-programming.rst19 If your hardware supports more than one io address, and your driver can
22 0x201 address is smaller.
25 0x218 would be the address of first choice.
27 If your hardware supports a gameport address that is not mapped to ISA io
34 Please also consider enabling the gameport on the card in the ->open()
35 callback if the io is mapped to ISA space - this way it'll occupy the io
37 ->close() callback. You also can select the io address in the ->open()
61 gameport.trigger = my_trigger;
70 the driver doesn't have to measure them the old way - an ADC is built into
86 return -(mode != GAMEPORT_MODE_COOKED);
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/Documentation/i2c/
Dslave-testunit-backend.rst1 .. SPDX-License-Identifier: GPL-2.0
7 by Wolfram Sang <wsa@sang-engineering.com> in 2020
9 This backend can be used to trigger test cases for I2C bus masters which
11 easy to obtain). Examples include multi-master testing, and SMBus Host Notify
19 Instantiating the device is regular. Example for bus 0, address 0x30::
21 # echo "slave-testunit 0x1030" > /sys/bus/i2c/devices/i2c-0/new_device
30 compatible = "slave-testunit";
39 When writing, the device consists of 4 8-bit registers and, except for some
43 .. csv-table::
46 0x00, CMD, which test to trigger
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/Documentation/devicetree/bindings/mips/cavium/
Dciu3.txt4 - compatible: "cavium,octeon-7890-ciu3"
8 - interrupt-controller: This is an interrupt controller.
10 - reg: The base address of the CIU's register bank.
12 - #interrupt-cells: Must be <2>. The first cell is source number.
17 interrupt-controller@1010000000000 {
18 compatible = "cavium,octeon-7890-ciu3";
19 interrupt-controller;
22 * 2) Trigger type: (4 == level, 1 == edge)
24 #address-cells = <0>;
25 #interrupt-cells = <2>;
/Documentation/trace/
Dhistogram.rst15 2. Histogram Trigger Command
18 A histogram trigger command is an event trigger command that
24 The format of a hist trigger is as follows::
33 numeric fields - on an event hit, the value(s) will be added to a
35 in place of an explicit value field - this is simply a count of
45 useful for providing more fine-grained summaries of event data.
50 key. If a hist trigger is given a name using the 'name' parameter,
52 name, and trigger hits will update this common data. Only triggers
54 'compatible' if the fields named in the trigger share the same
63 attached to an event, there will be a table for each trigger in the
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