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/Documentation/devicetree/bindings/sound/
Dqcom,wcd937x-sdw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd937x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire slave devices. This bindings is for the
24 qcom,tx-port-mapping:
26 Specifies static port mapping between device and host tx ports.
27 In the order of the device port index which are adc1_port, adc23_port,
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Dqcom,wcd939x-sdw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd939x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire devices. This bindings is for the devices.
23 qcom,tx-port-mapping:
25 Specifies static port mapping between device and host tx ports.
26 In the order of the device port index.
[all …]
Dqcom,wcd938x-sdw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,wcd938x-sdw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire slave devices. This bindings is for the
24 qcom,tx-port-mapping:
26 Specifies static port mapping between slave and master tx ports.
27 In the order of slave port index.
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Dqcom,wcd939x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9390/WCD9395 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire devices.
15 The WCD9390/WCD9395 IC has a functionally separate USB-C Mux subsystem
17 The Audio Headphone and Microphone data path between the Codec and the USB-C Mux
18 subsystems are external to the IC, thus requiring DT port-endpoint graph description
19 to handle USB-C altmode & orientation switching for Audio Accessory Mode.
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Dqcom,wcd938x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire slave devices.
17 - $ref: dai-common.yaml#
18 - $ref: qcom,wcd93xx-common.yaml#
23 - qcom,wcd9380-codec
24 - qcom,wcd9385-codec
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Dqcom,wcd937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9370/WCD9375 Codec is a standalone Hi-Fi audio codec IC.
14 It has RX and TX Soundwire slave devices.
17 - $ref: dai-common.yaml#
18 - $ref: qcom,wcd93xx-common.yaml#
23 - const: qcom,wcd9370-codec
24 - items:
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Drockchip,i2s-tdm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,i2s-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
18 - $ref: dai-common.yaml#
23 - rockchip,px30-i2s-tdm
24 - rockchip,rk1808-i2s-tdm
25 - rockchip,rk3308-i2s-tdm
26 - rockchip,rk3568-i2s-tdm
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/Documentation/devicetree/bindings/hsi/
Domap-ssi.txt9 - compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
10 - reg-names: Contains the values "sys" and "gdd" (in this order).
11 - reg: Contains a matching register specifier for each entry
12 in reg-names.
13 - interrupt-names: Contains the value "gdd_mpu".
14 - interrupts: Contains matching interrupt information for each entry
15 in interrupt-names.
16 - ranges: Represents the bus address mapping between the main
18 - clock-names: Must include the following entries:
22 - clocks: Contains a matching clock specifier for each entry in
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/Documentation/devicetree/bindings/ata/
Dsata_highbank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 activity LEDs and for mapping the ComboPHYs.
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
41 calxeda,led-order:
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/Documentation/devicetree/bindings/net/
Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
Dcavium-pip.txt10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
27 - #address-cells: Must be <1>.
29 - #size-cells: Must be <0>.
31 Properties for PIP port which is a child the PIP interface:
32 - compatible: "cavium,octeon-3860-pip-port"
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/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
15 pagetable, and only supports 4K size page mapping. Generation two uses the
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
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/Documentation/netlink/specs/
Ddevlink.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 protocol: genetlink-legacy
10 -
12 name: sb-pool-type
14 -
16 -
18 -
20 name: port-type
22 -
24 -
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Drt_link.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 name: rt-link
4 protocol: netlink-raw
11 -
12 name: ifinfo-flags
15 -
17 -
19 -
21 -
23 -
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/Documentation/devicetree/bindings/net/dsa/
Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14 describing a port needs to have a valid phandle referencing the internal PHY
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
[all …]
/Documentation/networking/
Dmulti-pf-netdev.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Multi-PF Netdev
11 - `Background`_
12 - `Overview`_
13 - `mlx5 implementation`_
14 - `Channels distribution`_
15 - `Observability`_
16 - `Steering`_
17 - `Mutually exclusive features`_
22 The Multi-PF NIC technology enables several CPUs within a multi-socket server to connect directly to
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Dscaling.rst1 .. SPDX-License-Identifier: GPL-2.0
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
28 (multi-queue). On reception, a NIC can send different packets to different
33 generally known as “Receive-side Scaling” (RSS). The goal of RSS and
35 Multi-queue distribution can also be used for traffic prioritization, but
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Dtimestamping.rst1 .. SPDX-License-Identifier: GPL-2.0
43 -------------------------------------------------------------
59 -------------------------------------------------------------------
72 ----------------------------------------------------------------------
110 Request tx timestamps generated by the network adapter. This flag
114 Request tx timestamps when data leaves the kernel. These timestamps
121 Request tx timestamps prior to entering the packet scheduler. Kernel
135 Request tx timestamps when all data in the send buffer has been
138 over-report measurement, because the timestamp is generated when all
181 is derived from a per-socket u32 counter (that wraps). For datagram
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/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
Dcounters.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
13 - `Overview`_
14 - `Groups`_
15 - `Types`_
16 - `Descriptions`_
27 ----------------------------------------
29 ---------------------------------------- ---------------------------------------- |
32 | ------------------- --------------- | | ------------------- --------------- | |
34 | ------------------- --------------- | | ------------------- --------------- | |
36 | ------------------- | | ------------------- | |
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/Documentation/devicetree/bindings/display/ti/
Dti,am65x-dss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
16 ports and two video planes. In AM65x DSS, the first video port
17 supports 1 OLDI TX and in AM625 DSS, the first video port output is
18 internally routed to 2 OLDI TXes. The second video port supports DPI
25 - ti,am625-dss
[all …]
/Documentation/networking/device_drivers/ethernet/intel/
Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
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/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
Dethernet-driver.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Copyright: |copy| 2017-2018 NXP
24 - network interfaces
25 - queues, channels
26 - buffer pools
27 - MAC/PHY
45 -----------------------
47 -----------------------
53 ---------- ---------- -----------
55 ---------- ---------- -----------
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/Documentation/networking/device_drivers/ethernet/freescale/
Ddpaa.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
[all …]
/Documentation/driver-api/
Dpin-control.rst9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
30 be sparse - i.e. there may be gaps in the space with numbers where no
60 .. code-block:: c
97 See ``arch/arm/mach-ux500/Kconfig`` for an example.
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/Documentation/networking/devlink/
Ddevlink-port.rst1 .. SPDX-License-Identifier: GPL-2.0
6 Devlink Port
9 ``devlink-port`` is a port that exists on the device. It has a logically
10 separate ingress/egress point of the device. A devlink port can be any one
11 of many flavours. A devlink port flavour along with port attributes
12 describe what a port represents.
14 A device driver that intends to publish a devlink port sets the
15 devlink port attributes and registers the devlink port.
17 Devlink port flavours are described below.
19 .. list-table:: List of devlink port flavours
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