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/Documentation/networking/device_drivers/ethernet/huawei/
Dhinic.rst1 .. SPDX-License-Identifier: GPL-2.0
11 The driver supports a range of link-speed devices (10GbE, 25GbE, 40GbE, etc.).
14 Some HiNIC devices support SR-IOV. This driver is used for Physical Function
17 HiNIC devices support MSI-X interrupt vector for each Tx/Rx queue and
21 TCP Transmit Segmentation Offload(TSO), Receive-Side Scaling(RSS) and
28 19e5:1822 - HiNIC PF
34 hinic_dev - Implement a Logical Network device that is independent from
37 hinic_hwdev - Implement the HW details of the device and include the components
55 Asynchronous Event Queues(AEQs) - The event queues for receiving messages from
58 Application Programmable Interface commands(API CMD) - Interface for sending
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/Documentation/networking/device_drivers/ethernet/intel/
Didpf.rst1 .. SPDX-License-Identifier: GPL-2.0+
17 For questions related to hardware requirements, refer to the documentation
18 supplied with your Intel adapter. All hardware requirements listed apply to use
24 For information on how to identify your adapter, and for the latest Intel
25 network drivers, refer to the Intel Support website:
33 -------
42 ---------------------
43 Link messages will not be displayed to the console if the distribution is
44 restricting system messages. In order to see network driver link messages on
45 your console, set dmesg to eight by entering the following::
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Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
25 For questions related to hardware requirements, refer to the documentation
26 supplied with your Intel adapter. All hardware requirements listed apply to use
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Diavf.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2013-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Additional Configurations
16 - Known Issues/Troubleshooting
17 - Support
28 CONFIG_PCI_MSI to be enabled.
30 The guest OS loading the iavf driver must support MSI-X interrupts.
44 For information on how to identify your adapter, and for the latest NVM/FW
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Dice.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
24 For questions related to hardware requirements, refer to the documentation
25 supplied with your Intel adapter. All hardware requirements listed apply to use
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
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/Documentation/devicetree/bindings/net/
Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
23 - snps,dwmac
24 - snps,dwmac-3.40a
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Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
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Dintel,ixp4xx-hss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx HSS makes use of the IXP4xx NPE (Network
15 Processing Engine) and the IXP4xx Queue Manager to process
20 const: intel,ixp4xx-hss
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
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Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
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/Documentation/networking/devlink/
Dmlx5.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 - Validation
18 * - ``enable_roce``
19 - driverinit
20 - Type: Boolean
26 * - ``io_eq_size``
27 - driverinit
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Ddevlink-port.rst1 .. SPDX-License-Identifier: GPL-2.0
9 ``devlink-port`` is a port that exists on the device. It has a logically
14 A device driver that intends to publish a devlink port sets the
19 .. list-table:: List of devlink port flavours
22 * - Flavour
23 - Description
24 * - ``DEVLINK_PORT_FLAVOUR_PHYSICAL``
25 - Any kind of physical port. This can be an eswitch physical port or any
27 * - ``DEVLINK_PORT_FLAVOUR_DSA``
28 - This indicates a DSA interconnect port.
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/Documentation/networking/device_drivers/ethernet/freescale/
Ddpaa.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
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/Documentation/virt/gunyah/
Dmessage-queue.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Message Queues
5 Message queue is a simple low-capacity IPC channel between two virtual machines.
7 message queue is unidirectional and buffered in the hypervisor. A full-duplex
8 IPC channel requires a pair of queues.
12 use case for message queues, and creates messages queues between itself and VMs
19 involves 2 message queues. Message queue 1 allows VM_A to send messages to VM_B.
20 Message queue 2 allows VM_B to send messages to VM_A.
22 1. VM_A sends a message of up to 240 bytes in length. It makes a hypercall
23 with the message to request the hypervisor to add the message to
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/Documentation/networking/device_drivers/ethernet/google/
Dgve.rst1 .. SPDX-License-Identifier: GPL-2.0+
9 The GVE driver binds to a single PCI device id used by the virtual
12 +--------------+----------+---------+
16 +--------------+----------+---------+
18 +--------------+----------+---------+
19 |Sub-vendor ID | `0x1AE0` | Google |
20 +--------------+----------+---------+
21 |Sub-device ID | `0x0058` | |
22 +--------------+----------+---------+
24 +--------------+----------+---------+
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/Documentation/devicetree/bindings/firmware/
Dgunyah-hypervisor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/gunyah-hypervisor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Prakruthi Deepak Heragu <quic_pheragu@quicinc.com>
11 - Elliot Berman <quic_eberman@quicinc.com>
14 Gunyah virtual machines use this information to determine the capability IDs
15 of the message queues used to communicate with the Gunyah Resource Manager.
16 …See also: https://github.com/quic/gunyah-resource-manager/blob/develop/src/vm_creation/dto_constru…
20 const: gunyah-hypervisor
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/Documentation/networking/
Dnapi.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
14 The host then schedules a NAPI instance to process the events.
19 but there is an option to use :ref:`separate kernel threads<threaded>`
23 of event (packet Rx and Tx) processing.
30 of the NAPI instance while the method is the driver-specific event
31 handler. The method will typically free Tx packets that have been
37 -----------
40 from the system. The instances are attached to the netdevice passed
46 to not be invoked. napi_disable() waits for ownership of the NAPI
47 instance to be released.
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Dmultiqueue.rst1 .. SPDX-License-Identifier: GPL-2.0
11 ---------------------------------------------------------
15 Base drivers are required to use the new alloc_etherdev_mq() or
16 alloc_netdev_mq() functions to allocate the subqueues for the device. The
18 the subqueue memory, as well as netdev configuration of where the queues
21 The base driver will also need to manage the queues as it does the global
22 netdev->queue_lock today. Therefore base drivers should use the
23 netif_{start|stop|wake}_subqueue() functions to manage each queue while the
24 device is still operational. netdev->queue_lock is still used when the device
33 A new round-robin qdisc, sch_multiq also supports multiple hardware queues. The
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Dscaling.rst1 .. SPDX-License-Identifier: GPL-2.0
12 networking stack to increase parallelism and improve performance for
13 multi-processor systems.
17 - RSS: Receive Side Scaling
18 - RPS: Receive Packet Steering
19 - RFS: Receive Flow Steering
20 - Accelerated Receive Flow Steering
21 - XPS: Transmit Packet Steering
27 Contemporary NICs support multiple receive and transmit descriptor queues
28 (multi-queue). On reception, a NIC can send different packets to different
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Ddevmem.rst1 .. SPDX-License-Identifier: GPL-2.0
16 -----------
22 - Distributed training, where ML accelerators, such as GPUs on different hosts,
25 - Distributed raw block storage applications transfer large amounts of data with
28 Typically the Device-to-Device data transfers in the network are implemented as
29 the following low-level operations: Device-to-Host copy, Host-to-Host network
30 transfer, and Host-to-Device copy.
36 Devmem TCP optimizes this use case by implementing socket APIs that enable
37 the user to receive incoming network packets directly into device memory.
39 Packet payloads go directly from the NIC to device memory.
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Daf_xdp.rst1 .. SPDX-License-Identifier: GPL-2.0
18 redirect ingress frames to other XDP enabled netdevs, using the
20 XDP programs to redirect frames to a memory buffer in a user-space
25 TX ring. A socket can receive packets on the RX ring and it can send
26 packets on the TX ring. These rings are registered and sized with the
28 to have at least one of these rings for each socket. An RX or TX
29 descriptor ring points to a data buffer in a memory area called a
30 UMEM. RX and TX can share the same UMEM so that a packet does not have
31 to be copied between RX and TX. Moreover, if a packet needs to be kept
32 for a while due to a possible retransmit, the descriptor that points
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/Documentation/networking/device_drivers/ethernet/ti/
Dcpsw.rst1 .. SPDX-License-Identifier: GPL-2.0
26 - TX queues must be rated starting from txq0 that has highest priority
27 - Traffic classes are used starting from 0, that has highest priority
28 - CBS shapers should be used with rated queues
29 - The bandwidth for CBS shapers has to be set a little bit more then
30 potential incoming rate, thus, rate of all incoming tx queues has
31 to be a little less
32 - Real rates can differ, due to discreetness
33 - Map skb-priority to txq is not enough, also skb-priority to l2 prio
34 map has to be created with ip or vconfig tool
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/Documentation/devicetree/bindings/mailbox/
Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
15 external to the various processor subsystems and is connected on an
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
20 output interrupt lines. An output interrupt line is routed to an interrupt
22 going to a specific processor's interrupt controller. The interrupt line
26 interrupt configuration registers, and have a rx and tx interrupt source per
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/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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/Documentation/devicetree/bindings/soc/ti/
Dkeystone-navigator-qmss.txt5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
10 reading descriptor address to a particular memory mapped location. The PDSPs
12 Linking RAM registers are used to link the descriptors which are stored in
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
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/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
Doverview.rst16 DPAA2 is a hardware architecture designed for high-speeed network
23 DPAA2 hardware resources. The MC provides an object-based abstraction for
24 software drivers to use the DPAA2 hardware.
25 The MC uses DPAA2 hardware resources such as queues, buffer pools, and
26 network ports to create functional objects/devices such as network
28 The MC provides memory-mapped I/O command interfaces (MC portals)
29 which DPAA2 software drivers use to operate on DPAA2 objects.
34 +--------------------------------------+
38 +-----------------------------|--------+
41 | config,use,destroy)
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