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/Documentation/devicetree/bindings/phy/
Drealtek,usb2phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Realtek DHC SoCs USB 2.0 PHY
11 - Stanley Chang <stanley_chang@realtek.com>
14 Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoCs.
15 The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs
17 controller.
19 RTD1295/RTD1619 SoCs USB
20 The USB architecture includes three XHCI controllers.
[all …]
Drealtek,usb3phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Realtek DHC SoCs USB 3.0 PHY
11 - Stanley Chang <stanley_chang@realtek.com>
14 Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs.
15 The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs
17 controller.
19 RTD1295/RTD1619 SoCs USB
20 The USB architecture includes three XHCI controllers.
[all …]
Dmarvell,armada-cp110-utmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Konstantin Porotchkin <kostap@marvell.com>
14 On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
15 Each of two exiting UTMI PHYs could be connected to either USB host or USB device
16 controller.
17 The USB device controller can only be connected to a single UTMI PHY port
18 0.H----- USB HOST0
[all …]
Dallwinner,sun8i-h3-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H3 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-h3-usb-phy
20 - allwinner,sun50i-h616-usb-phy
[all …]
Dallwinner,sun6i-a31-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun6i-a31-usb-phy
22 - description: PHY Control registers
[all …]
Dallwinner,sun8i-r40-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-r40-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner R40 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-r40-usb-phy
22 - description: PHY Control registers
[all …]
Dallwinner,sun8i-a83t-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-a83t-usb-phy
22 - description: PHY Control registers
[all …]
Dallwinner,sun4i-a10-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun4i-a10-usb-phy
20 - allwinner,sun7i-a20-usb-phy
[all …]
Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
[all …]
/Documentation/devicetree/bindings/usb/
Ds3c2410-usb.txt1 Samsung S3C2410 and compatible SoC USB controller
6 - compatible: should be "samsung,s3c2410-ohci" for USB host controller
7 - reg: address and length of the controller memory mapped region
8 - interrupts: interrupt number for the USB OHCI controller
9 - clocks: Should reference the bus and host clocks
10 - clock-names: Should contain two strings
11 "usb-bus-host" for the USB bus clock
12 "usb-host" for the USB host clock
17 compatible = "samsung,s3c2410-ohci";
21 clock-names = "usb-bus-host", "usb-host";
Dam33xx-usb.txt3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
8 at least a control module node, USB node and a PHY node. The second USB
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
15 Module" block. A second offset and length for the USB wake up control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
18 the USB wake up control register.
20 USB PHY
[all …]
Dtwlxxxx-usb.txt1 USB COMPARATOR OF TWL CHIPS
3 TWL6030 USB COMPARATOR
4 - compatible : Should be "ti,twl6030-usb"
5 - interrupts : Two interrupt numbers to the cpu should be specified. First
7 the controller has to act as host and the second interrupt number is the
8 usb interrupt number that raises VBUS interrupts when the controller has to
10 - usb-supply : phandle to the regulator device tree node. It should be vusb
13 twl6030-usb {
14 compatible = "ti,twl6030-usb";
19 &twl6030-usb {
[all …]
Dlpc32xx-udc.txt1 * NXP LPC32xx SoC USB Device Controller (UDC)
4 - compatible: Must be "nxp,lpc3220-udc"
5 - reg: Physical base address of the controller and length of memory mapped
7 - interrupts: The USB interrupts:
8 * USB Device Low Priority Interrupt
9 * USB Device High Priority Interrupt
10 * USB Device DMA Interrupt
11 * External USB Transceiver Interrupt (OTG ATX)
12 - transceiver: phandle of the associated ISP1301 device - this is necessary for
13 the UDC controller for connecting to the USB physical layer
[all …]
Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP USB2 ChipIdea USB controller
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
[all …]
Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 xHCI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
14 exposed by the Tegra XUSB pad controller.
20 - description: NVIDIA Tegra124
[all …]
Dnxp,isp1760.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nxp,isp1760.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP ISP1760 family controller
10 - Sebastian Siewior <bigeasy@linutronix.de>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 NXP ISP1760 family, which includes ISP1760/1761/1763 devicetree controller
20 - nxp,usb-isp1760
21 - nxp,usb-isp1761
[all …]
Dohci-st.txt1 ST USB OHCI controller
5 - compatible : must be "st,st-ohci-300x"
6 - reg : physical base addresses of the controller and length of memory mapped
8 - interrupts : one OHCI controller interrupt should be described here
9 - clocks : phandle list of usb clocks
10 - clock-names : should be "ic" for interconnect clock and "clk48"
11 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - phys : phandle for the PHY device
14 - phy-names : should be "usb"
16 - resets : phandle to the powerdown and reset controller for the USB IP
[all …]
Dda8xx-usb.txt3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms.
7 - compatible : Should be set to "ti,da830-musb".
9 - reg: Offset and length of the USB controller register set.
11 - interrupts: The USB interrupt number.
13 - interrupt-names: Should be set to "mc".
15 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg".
17 - phys: Phandle for the PHY device
19 - phy-names: Should be "usb-phy"
21 - dmas: specifies the dma channels
23 - dma-names: specifies the names of the channels. Use "rxN" for receive
[all …]
Dehci-st.txt1 ST USB EHCI controller
4 - compatible : must be "st,st-ehci-300x"
5 - reg : physical base addresses of the controller and length of memory mapped
7 - interrupts : one EHCI interrupt should be described here
8 - pinctrl-names : a pinctrl state named "default" must be defined
9 - pinctrl-0 : phandle referencing pin configuration of the USB controller
10 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
11 - clocks : phandle list of usb clocks
12 - clock-names : should be "ic" for interconnect clock and "clk48"
13 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
/Documentation/devicetree/bindings/dma/
Drenesas,usb-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,usb-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas USB DMA Controller
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 - $ref: dma-controller.yaml#
18 - enum:
19 - renesas,r8a7742-usb-dmac # RZ/G1H
20 - renesas,r8a7743-usb-dmac # RZ/G1M
[all …]
/Documentation/usb/
Dehci.rst5 27-Dec-2002
7 The EHCI driver is used to talk to high speed USB 2.0 devices using
8 USB 2.0-capable host controller hardware. The USB 2.0 standard is
9 compatible with the USB 1.1 standard. It defines three transfer speeds:
11 - "High Speed" 480 Mbit/sec (60 MByte/sec)
12 - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
13 - "Low Speed" 1.5 Mbit/sec
15 USB 1.1 only addressed full speed and low speed. High speed devices
16 can be used on USB 1.1 systems, but they slow down to USB 1.1 speeds.
18 USB 1.1 devices may also be used on USB 2.0 systems. When plugged
[all …]
Dohci.rst5 23-Aug-2002
7 The "ohci-hcd" driver is a USB Host Controller Driver (HCD) that is derived
8 from the "usb-ohci" driver from the 2.4 kernel series. The "usb-ohci" code
12 It supports the "Open Host Controller Interface" (OHCI), which standardizes
13 hardware register protocols used to talk to USB 1.1 host controllers. As
14 compared to the earlier "Universal Host Controller Interface" (UHCI) from
15 Intel, it pushes more intelligence into the hardware. USB 1.1 controllers
20 - improved robustness; bugfixes; and less overhead
21 - supports the updated and simplified usbcore APIs
22 - interrupt transfers can be larger, and can be queued
[all …]
/Documentation/driver-api/usb/
Dwriting_musb_glue_layer.rst10 The Linux MUSB subsystem is part of the larger Linux USB subsystem. It
11 provides support for embedded USB Device Controllers (UDC) that do not
12 use Universal Host Controller Interface (UHCI) or Open Host Controller
15 Instead, these embedded UDC rely on the USB On-the-Go (OTG)
17 reference design used in most cases is the Multipoint USB Highspeed
18 Dual-Role Controller (MUSB HDRC) found in the Mentor Graphics Inventra™
21 As a self-taught exercise I have written an MUSB glue layer for the
24 ``drivers/usb/musb/jz4740.c``. In this documentation I will walk through the
28 .. _musb-basics:
33 To get started on the topic, please read USB On-the-Go Basics (see
[all …]
Dgadget.rst2 USB Gadget API for Linux
11 This document presents a Linux-USB "Gadget" kernel mode API, for use
12 within peripherals and other USB devices that embed Linux. It provides
17 - Supports USB 2.0, for high speed devices which can stream data at
20 - Handles devices with dozens of endpoints just as well as ones with
21 just two fixed-function ones. Gadget drivers can be written so
24 - Flexible enough to expose more complex USB device capabilities such
28 - USB "On-The-Go" (OTG) support, in conjunction with updates to the
29 Linux-USB host side.
31 - Sharing data structures and API models with the Linux-USB host side
[all …]
/Documentation/devicetree/bindings/net/
Dmicrochip,lan95xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip SMSC9500/LAN9530/LAN9730 USB Ethernet Controllers
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 Device tree properties for hard wired SMSC95xx compatible USB Ethernet
14 controller.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - usb424,9500 # SMSC9500 USB Ethernet Device
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