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/Documentation/devicetree/bindings/mtd/
Dmtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
21 User-defined MTD device name. Can be used to assign user friendly
26 '#address-cells':
29 '#size-cells':
36 - compatible
39 "@[0-9a-f]+$":
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Dnand-macronix.txt2 -----------------------------------
4 Macronix NANDs support randomizer operation for scrambling user data,
11 For more high-reliability concern, if subpage write is not available
17 - randomizer enable: should be "mxic,enable-randomizer-otp"
21 nand: nand-controller@unit-address {
25 mxic,enable-randomizer-otp;
/Documentation/devicetree/bindings/nvmem/
Dmicrochip,lan9662-otpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,lan9662-otpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN9662 OTP Controller (OTPC)
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 OTP controller drives a NVMEM memory where system specific data
15 user specific data could be stored.
18 - $ref: nvmem.yaml#
23 - items:
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Dmicrochip,sama7g5-otpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip SAMA7G5 OTP Controller (OTPC)
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
13 OTP controller drives a NVMEM memory where system specific data
15 settings, chip identifiers) or user specific data could be stored.
18 - $ref: nvmem.yaml#
19 - $ref: nvmem-deprecated-cells.yaml#
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/Documentation/devicetree/bindings/nvmem/layouts/
Dkontron,sl28-vpd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/kontron,sl28-vpd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVMEM layout of the Kontron SMARC-sAL28 vital product data
10 - Michael Walle <michael@walle.cc>
15 on-board ethernet devices are derived from this base MAC address by
22 const: kontron,sl28-vpd
24 serial-number:
30 base-mac-address:
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Donie,tlv-layout.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/onie,tlv-layout.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 infrastructure shall provide a non-volatile memory with a table whose the
26 const: onie,tlv-layout
28 product-name:
32 part-number:
36 serial-number:
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/Documentation/ABI/testing/
Dsysfs-platform-silicom1 What: /sys/devices/platform/silicom-platform/uc_version
4 Contact: Henry Shi <henrys@silicom-usa.com>
9 What: /sys/devices/platform/silicom-platform/power_cycle
12 Contact: Henry Shi <henrys@silicom-usa.com>
14 This file allow user to power cycle the platform.
19 0 - default value.
21 What: /sys/devices/platform/silicom-platform/efuse_status
24 Contact: Henry Shi <henrys@silicom-usa.com>
27 OTP status:
29 0 - not programmed.
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/Documentation/ABI/stable/
Dsysfs-bus-nvmem6 This read/write attribute allows users to set read-write
7 devices as read-only and back to read-write from userspace.
8 This can be used to unlock and relock write-protection of
11 Read returns '0' or '1' for read-write or read-only modes
23 This file allows user to read/write the raw NVMEM contents.
46 This read-only attribute allows user to read the NVMEM
48 "OTP", "Battery backed", "FRAM".
/Documentation/devicetree/bindings/clock/
Drenesas,5p35023.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
14 is designed for low-power, consumer, and high-performance PCI
19 An internal OTP memory allows the user to store the configuration
20 in the device. After power up, the user can change the device register
29 …renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3…
34 - renesas,5p35023
39 '#clock-cells':
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/Documentation/security/keys/
Dtrusted-encrypted.rst7 and in both cases all keys are created in the kernel, and user space sees,
10 system. All user level blobs, are displayed and loaded in hex ASCII for
33 (2) TEE (Trusted Execution Environment: OP-TEE based on Arm TrustZone)
35 Rooted to Hardware Unique Key (HUK) which is generally burnt in on-chip
41 mode, trust is rooted to the OTPMK, a never-disclosed 256-bit key
45 (4) DCP (Data Co-Processor: crypto accelerator of various i.MX SoCs)
47 Rooted to a one-time programmable key (OTP) that is generally burnt
48 in the on-chip fuses and is accessible to the DCP encryption engine only.
49 DCP provides two keys that can be used as root of trust: the OTP key
51 the OTP key can be done via a module parameter (dcp_use_otp_key).
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/Documentation/devicetree/bindings/iio/adc/
Dst,stm32-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
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/Documentation/admin-guide/
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
73 Documentation/firmware-guide/acpi/debug.rst for more information about
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