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Searched refs:enable_bit (Results 1 – 25 of 43) sorted by relevance

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/drivers/clk/ti/
Dclkt_dflt.c146 *other_bit = clk->enable_bit; in omap2_clk_dflt_find_companion()
172 *idlest_bit = clk->enable_bit; in omap2_clk_dflt_find_idlest()
222 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_enable()
224 v |= (1 << clk->enable_bit); in omap2_dflt_clk_enable()
252 v |= (1 << clk->enable_bit); in omap2_dflt_clk_disable()
254 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_disable()
279 v ^= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
281 v &= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
Dinterface.c44 clk_hw->enable_bit = bit_idx; in _register_interface()
67 u8 enable_bit = 0; in _of_ti_interface_clk_setup() local
73 enable_bit = reg.bit; in _of_ti_interface_clk_setup()
83 enable_bit, ops); in _of_ti_interface_clk_setup()
Dgate.c108 clk_hw->enable_bit = bit_idx; in _register_gate()
134 u8 enable_bit = 0; in _of_ti_gate_clk_setup() local
142 enable_bit = reg.bit; in _of_ti_gate_clk_setup()
160 enable_bit, clk_gate_flags, ops, hw_ops); in _of_ti_gate_clk_setup()
179 gate->enable_bit = gate->enable_reg.bit; in _of_ti_composite_gate_clk_setup()
Dclkt_iclk.c37 v |= (1 << clk->enable_bit); in omap2_clkt_iclk_allow_idle()
52 v &= ~(1 << clk->enable_bit); in omap2_clkt_iclk_deny_idle()
75 *idlest_bit = clk->enable_bit; in omap2430_clk_i2chs_find_idlest()
Dclk-3xxx.c153 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; in am35xx_clk_find_idlest()
176 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) in am35xx_clk_find_companion()
177 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
179 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
Dclkctrl.c148 if (!clk->enable_bit) in _omap4_clkctrl_clk_enable()
154 val |= clk->enable_bit; in _omap4_clkctrl_clk_enable()
178 if (!clk->enable_bit) in _omap4_clkctrl_clk_disable()
211 if (val & clk->enable_bit) in _omap4_clkctrl_clk_is_enabled()
344 clk_hw->enable_bit = data->bit; in _ti_clkctrl_setup_gate()
663 hw->enable_bit = MODULEMODE_SWCTRL; in _ti_omap4_clkctrl_setup()
665 hw->enable_bit = MODULEMODE_HWCTRL; in _ti_omap4_clkctrl_setup()
Dapll.c379 clk_hw->enable_bit = ti_clk_get_legacy_bit_shift(node); in of_omap2_apll_setup()
380 ad->enable_mask = 0x3 << clk_hw->enable_bit; in of_omap2_apll_setup()
381 ad->autoidle_mask = 0x3 << clk_hw->enable_bit; in of_omap2_apll_setup()
/drivers/clk/
Dclk-max9485.c73 u8 enable_bit; member
115 clk_hw->enable_bit, in max9485_clk_prepare()
116 clk_hw->enable_bit); in max9485_clk_prepare()
123 max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0); in max9485_clk_unprepare()
206 u8 enable_bit; member
213 .enable_bit = MAX9485_MCLK_ENABLE,
231 .enable_bit = MAX9485_CLKOUT1_ENABLE,
240 .enable_bit = MAX9485_CLKOUT2_ENABLE,
321 drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit; in max9485_i2c_probe()
/drivers/regulator/
Dtps6586x-regulator.c59 int enable_bit[2]; member
128 .enable_bit[0] = (ebit0), \
130 .enable_bit[1] = (ebit1),
153 .enable_bit[0] = (ebit0), \
155 .enable_bit[1] = (ebit1),
274 ri->enable_bit[0] == ri->enable_bit[1]) in tps6586x_regulator_preinit()
285 if (!(val2 & (1 << ri->enable_bit[1]))) in tps6586x_regulator_preinit()
292 if (!(val1 & (1 << ri->enable_bit[0]))) { in tps6586x_regulator_preinit()
294 1 << ri->enable_bit[0]); in tps6586x_regulator_preinit()
300 1 << ri->enable_bit[1]); in tps6586x_regulator_preinit()
Dmc13xxx.h16 int enable_bit; member
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
Dmc13xxx-regulator-core.c36 mc13xxx_regulators[id].enable_bit, in mc13xxx_regulator_enable()
37 mc13xxx_regulators[id].enable_bit); in mc13xxx_regulator_enable()
49 mc13xxx_regulators[id].enable_bit, 0); in mc13xxx_regulator_disable()
63 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13xxx_regulator_is_enabled()
Dmc13783-regulator.c330 u32 en_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_enable()
339 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_enable()
355 dis_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_disable()
357 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_disable()
380 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13783_gpo_regulator_is_enabled()
Dda903x-regulator.c82 int enable_bit; member
141 1 << info->enable_bit); in da903x_enable()
150 1 << info->enable_bit); in da903x_disable()
164 return !!(reg_val & (1 << info->enable_bit)); in da903x_is_enabled()
326 .enable_bit = (ebit), \
348 .enable_bit = (ebit), \
Dmc13892-regulator.c337 u32 en_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
338 u32 mask = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
362 dis_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_disable()
364 return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit, in mc13892_gpo_regulator_disable()
386 return (val & mc13892_regulators[id].enable_bit) != 0; in mc13892_gpo_regulator_is_enabled()
Danatop-regulator.c290 u32 enable_bit; in anatop_regulator_probe() local
295 &enable_bit)) { in anatop_regulator_probe()
301 rdesc->enable_mask = BIT(enable_bit); in anatop_regulator_probe()
/drivers/clk/renesas/
Dclk-sh73a0.c89 u32 enable_bit = name[3] - '0'; in sh73a0_cpg_register_clock() local
92 switch (enable_bit) { in sh73a0_cpg_register_clock()
108 if (readl(base + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
111 if (enable_bit == 1 || enable_bit == 2) in sh73a0_cpg_register_clock()
/drivers/sh/clk/
Dcpg.c41 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); in sh_clk_mstp_enable()
56 (read(mapped_status) & (1 << clk->enable_bit)) && i; in sh_clk_mstp_enable()
61 clk->enable_reg, clk->enable_bit); in sh_clk_mstp_enable()
70 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); in sh_clk_mstp_disable()
123 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
139 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
140 value |= (idx << clk->enable_bit); in sh_clk_div_set_rate()
/drivers/thermal/intel/int340x_thermal/
Dprocessor_thermal_mbox.c117 int enable_bit, int time_window) in processor_thermal_mbox_interrupt_config() argument
143 data |= BIT(enable_bit); in processor_thermal_mbox_interrupt_config()
145 data &= ~BIT(enable_bit); in processor_thermal_mbox_interrupt_config()
/drivers/xen/xen-pciback/
Dconf_space_capability.c193 u16 enable_bit; /* bit for enabling MSI/MSI-X */ member
197 .enable_bit = PCI_MSI_FLAGS_ENABLE,
201 .enable_bit = PCI_MSIX_FLAGS_ENABLE,
238 if (new_value & field_config->enable_bit) { in msi_msix_flags_write()
/drivers/clk/ingenic/
Dx1830-cgu.c130 .enable_bit = 0,
153 .enable_bit = 0,
176 .enable_bit = 0,
199 .enable_bit = 0,
Dcgu.c239 if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) in ingenic_pll_set_rate()
257 if (pll_info->enable_bit < 0) in ingenic_pll_enable()
271 ctl |= BIT(pll_info->enable_bit); in ingenic_pll_enable()
290 if (pll_info->enable_bit < 0) in ingenic_pll_disable()
296 ctl &= ~BIT(pll_info->enable_bit); in ingenic_pll_disable()
310 if (pll_info->enable_bit < 0) in ingenic_pll_is_enabled()
315 return !!(ctl & BIT(pll_info->enable_bit)); in ingenic_pll_is_enabled()
Djz4760-cgu.c110 .enable_bit = 8,
134 .enable_bit = 7,
/drivers/watchdog/
DiTCO_wdt.c159 u32 enable_bit; in no_reboot_bit() local
164 enable_bit = 0x00000010; in no_reboot_bit()
167 enable_bit = 0x00000020; in no_reboot_bit()
172 enable_bit = 0x00000002; in no_reboot_bit()
176 return enable_bit; in no_reboot_bit()
/drivers/clk/spear/
Dclk-aux-synth.c38 .enable_bit = AUX_SYNT_ENB,
179 aux->masks->enable_bit, 0, lock); in clk_register_aux()
/drivers/tty/serial/
Dmsm_serial.c173 u32 enable_bit; member
274 val &= ~dma->enable_bit; in msm_stop_dma()
344 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE; in msm_request_tx_dma()
346 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE; in msm_request_tx_dma()
396 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE; in msm_request_rx_dma()
398 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE; in msm_request_rx_dma()
473 val &= ~dma->enable_bit; in msm_complete_tx_dma()
540 val |= dma->enable_bit; in msm_handle_tx_dma()
576 val &= ~dma->enable_bit; in msm_complete_rx_dma()
675 val |= dma->enable_bit; in msm_start_rx_dma()

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