1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/include/asm/kvm_host.h:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
13
14 #include <linux/android_kabi.h>
15 #include <linux/arm-smccc.h>
16 #include <linux/bitmap.h>
17 #include <linux/types.h>
18 #include <linux/jump_label.h>
19 #include <linux/kvm_types.h>
20 #include <linux/maple_tree.h>
21 #include <linux/percpu.h>
22 #include <linux/psci.h>
23 #include <asm/arch_gicv3.h>
24 #include <asm/barrier.h>
25 #include <asm/cpufeature.h>
26 #include <asm/cputype.h>
27 #include <asm/daifflags.h>
28 #include <asm/fpsimd.h>
29 #include <asm/kvm.h>
30 #include <asm/kvm_asm.h>
31 #include <asm/vncr_mapping.h>
32
33 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
34
35 #define KVM_HALT_POLL_NS_DEFAULT 500000
36
37 #include <kvm/arm_vgic.h>
38 #include <kvm/arm_arch_timer.h>
39 #include <kvm/arm_pmu.h>
40
41 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
42
43 #define KVM_VCPU_MAX_FEATURES 7
44 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1)
45
46 #define KVM_REQ_SLEEP \
47 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
48 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
49 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
50 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3)
51 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
52 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5)
53 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6)
54 #define KVM_REQ_RESYNC_PMU_EL0 KVM_ARCH_REQ(7)
55 #define KVM_REQ_NESTED_S2_UNMAP KVM_ARCH_REQ(8)
56
57 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
58 KVM_DIRTY_LOG_INITIALLY_SET)
59
60 #define KVM_HAVE_MMU_RWLOCK
61
62 /*
63 * Mode of operation configurable with kvm-arm.mode early param.
64 * See Documentation/admin-guide/kernel-parameters.txt for more information.
65 */
66 enum kvm_mode {
67 KVM_MODE_DEFAULT,
68 KVM_MODE_PROTECTED,
69 KVM_MODE_NV,
70 KVM_MODE_NONE,
71 };
72 #ifdef CONFIG_KVM
73 enum kvm_mode kvm_get_mode(void);
74 #else
kvm_get_mode(void)75 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
76 #endif
77
78 extern unsigned int __ro_after_init kvm_sve_max_vl;
79 extern unsigned int __ro_after_init kvm_host_sve_max_vl;
80 int __init kvm_arm_init_sve(void);
81
82 u32 __attribute_const__ kvm_target_cpu(void);
83 void kvm_reset_vcpu(struct kvm_vcpu *vcpu);
84 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
85
86 /* Head holds page head and it's order. */
87 struct kvm_hyp_memcache {
88 phys_addr_t head;
89 unsigned long nr_pages;
90 unsigned long flags;
91 void *mapping; /* struct pkvm_mapping *, only used from EL1 */
92 ANDROID_KABI_RESERVE(1);
93 ANDROID_KABI_RESERVE(2);
94 };
95
push_hyp_memcache(struct kvm_hyp_memcache * mc,phys_addr_t * p,phys_addr_t (* to_pa)(void * virt),unsigned long order)96 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
97 phys_addr_t *p,
98 phys_addr_t (*to_pa)(void *virt),
99 unsigned long order)
100 {
101 *p = mc->head;
102 mc->head = (to_pa(p) & PAGE_MASK) |
103 FIELD_PREP(~PAGE_MASK, order);
104 mc->nr_pages++;
105 }
106
pop_hyp_memcache(struct kvm_hyp_memcache * mc,void * (* to_va)(phys_addr_t phys),unsigned long * order)107 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
108 void *(*to_va)(phys_addr_t phys),
109 unsigned long *order)
110 {
111 phys_addr_t *p = to_va(mc->head & PAGE_MASK);
112
113 if (!mc->nr_pages)
114 return NULL;
115
116 *order = FIELD_GET(~PAGE_MASK, mc->head);
117
118 mc->head = *p;
119 mc->nr_pages--;
120
121 return p;
122 }
123
__topup_hyp_memcache(struct kvm_hyp_memcache * mc,unsigned long min_pages,void * (* alloc_fn)(void * arg,unsigned long order),phys_addr_t (* to_pa)(void * virt),void * arg,unsigned long order)124 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
125 unsigned long min_pages,
126 void *(*alloc_fn)(void *arg, unsigned long order),
127 phys_addr_t (*to_pa)(void *virt),
128 void *arg,
129 unsigned long order)
130 {
131 while (mc->nr_pages < min_pages) {
132 phys_addr_t *p = alloc_fn(arg, order);
133
134 if (!p)
135 return -ENOMEM;
136 push_hyp_memcache(mc, p, to_pa, order);
137 }
138
139 return 0;
140 }
141
__free_hyp_memcache(struct kvm_hyp_memcache * mc,void (* free_fn)(void * virt,void * arg,unsigned long order),void * (* to_va)(phys_addr_t phys),void * arg)142 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
143 void (*free_fn)(void *virt, void *arg, unsigned long order),
144 void *(*to_va)(phys_addr_t phys),
145 void *arg)
146 {
147 unsigned long order;
148 void *p;
149
150 while (mc->nr_pages) {
151 p = pop_hyp_memcache(mc, to_va, &order);
152 free_fn(p, arg, order);
153 }
154 }
155
156 #define HYP_MEMCACHE_ACCOUNT_KMEMCG BIT(1)
157 #define HYP_MEMCACHE_ACCOUNT_STAGE2 BIT(2)
158
159 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
160 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages, unsigned long order);
161 int topup_hyp_memcache_gfp(struct kvm_hyp_memcache *mc, unsigned long min_pages,
162 unsigned long order, gfp_t gfp);
163
init_hyp_memcache(struct kvm_hyp_memcache * mc)164 static inline void init_hyp_memcache(struct kvm_hyp_memcache *mc)
165 {
166 memset(mc, 0, sizeof(*mc));
167 }
168
init_hyp_stage2_memcache(struct kvm_hyp_memcache * mc)169 static inline void init_hyp_stage2_memcache(struct kvm_hyp_memcache *mc)
170 {
171 init_hyp_memcache(mc);
172 mc->flags = HYP_MEMCACHE_ACCOUNT_KMEMCG | HYP_MEMCACHE_ACCOUNT_STAGE2;
173 }
174
175 struct kvm_vmid {
176 atomic64_t id;
177 };
178
179 struct kvm_s2_mmu {
180 struct kvm_vmid vmid;
181
182 /*
183 * stage2 entry level table
184 *
185 * Two kvm_s2_mmu structures in the same VM can point to the same
186 * pgd here. This happens when running a guest using a
187 * translation regime that isn't affected by its own stage-2
188 * translation, such as a non-VHE hypervisor running at vEL2, or
189 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the
190 * canonical stage-2 page tables.
191 */
192 phys_addr_t pgd_phys;
193 struct kvm_pgtable *pgt;
194
195 /*
196 * VTCR value used on the host. For a non-NV guest (or a NV
197 * guest that runs in a context where its own S2 doesn't
198 * apply), its T0SZ value reflects that of the IPA size.
199 *
200 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to
201 * the guest.
202 */
203 u64 vtcr;
204
205 /* The last vcpu id that ran on each physical CPU */
206 int __percpu *last_vcpu_ran;
207
208 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0
209 /*
210 * Memory cache used to split
211 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It
212 * is used to allocate stage2 page tables while splitting huge
213 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
214 * influences both the capacity of the split page cache, and
215 * how often KVM reschedules. Be wary of raising CHUNK_SIZE
216 * too high.
217 *
218 * Protected by kvm->slots_lock.
219 */
220 struct kvm_mmu_memory_cache split_page_cache;
221 uint64_t split_page_chunk_size;
222
223 struct kvm_arch *arch;
224
225 /*
226 * For a shadow stage-2 MMU, the virtual vttbr used by the
227 * host to parse the guest S2.
228 * This either contains:
229 * - the virtual VTTBR programmed by the guest hypervisor with
230 * CnP cleared
231 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid
232 *
233 * We also cache the full VTCR which gets used for TLB invalidation,
234 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted
235 * to be cached in a TLB" to the letter.
236 */
237 u64 tlb_vttbr;
238 u64 tlb_vtcr;
239
240 /*
241 * true when this represents a nested context where virtual
242 * HCR_EL2.VM == 1
243 */
244 bool nested_stage2_enabled;
245
246 /*
247 * true when this MMU needs to be unmapped before being used for a new
248 * purpose.
249 */
250 bool pending_unmap;
251
252 /*
253 * 0: Nobody is currently using this, check vttbr for validity
254 * >0: Somebody is actively using this.
255 */
256 atomic_t refcnt;
257 };
258
259 struct kvm_arch_memory_slot {
260 };
261
262 /**
263 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
264 *
265 * @std_bmap: Bitmap of standard secure service calls
266 * @std_hyp_bmap: Bitmap of standard hypervisor service calls
267 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
268 */
269 struct kvm_smccc_features {
270 unsigned long std_bmap;
271 unsigned long std_hyp_bmap;
272 unsigned long vendor_hyp_bmap;
273 };
274
275 struct kvm_pinned_page {
276 union {
277 struct rb_node node;
278 struct list_head list_node;
279 };
280 struct page *page;
281 u64 ipa;
282 u64 __subtree_last;
283 u8 order;
284 };
285
286 struct kvm_pinned_page
287 *kvm_pinned_pages_iter_first(struct rb_root_cached *root, u64 start, u64 end);
288 struct kvm_pinned_page
289 *kvm_pinned_pages_iter_next(struct kvm_pinned_page *ppage, u64 start, u64 end);
290 void kvm_pinned_pages_remove(struct kvm_pinned_page *ppage,
291 struct rb_root_cached *root);
292
293 typedef unsigned int pkvm_handle_t;
294
295 struct kvm_protected_vm {
296 pkvm_handle_t handle;
297 struct kvm_hyp_memcache stage2_teardown_mc;
298 struct rb_root_cached pinned_pages;
299 struct kvm_hyp_memcache teardown_iommu_mc;
300 gpa_t pvmfw_load_addr;
301 bool enabled;
302 u32 ffa_support;
303 bool smc_forwarded;
304 };
305
306 struct kvm_mpidr_data {
307 u64 mpidr_mask;
308 DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx);
309 };
310
kvm_mpidr_index(struct kvm_mpidr_data * data,u64 mpidr)311 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr)
312 {
313 unsigned long index = 0, mask = data->mpidr_mask;
314 unsigned long aff = mpidr & MPIDR_HWID_BITMASK;
315
316 bitmap_gather(&index, &aff, &mask, fls(mask));
317
318 return index;
319 }
320
321 struct kvm_sysreg_masks;
322
323 enum fgt_group_id {
324 __NO_FGT_GROUP__,
325 HFGxTR_GROUP,
326 HDFGRTR_GROUP,
327 HDFGWTR_GROUP = HDFGRTR_GROUP,
328 HFGITR_GROUP,
329 HAFGRTR_GROUP,
330
331 /* Must be last */
332 __NR_FGT_GROUP_IDS__
333 };
334
335 struct kvm_arch {
336 struct kvm_s2_mmu mmu;
337
338 /*
339 * Fine-Grained UNDEF, mimicking the FGT layout defined by the
340 * architecture. We track them globally, as we present the
341 * same feature-set to all vcpus.
342 *
343 * Index 0 is currently spare.
344 */
345 u64 fgu[__NR_FGT_GROUP_IDS__];
346
347 /*
348 * Stage 2 paging state for VMs with nested S2 using a virtual
349 * VMID.
350 */
351 struct kvm_s2_mmu *nested_mmus;
352 size_t nested_mmus_size;
353 int nested_mmus_next;
354
355 /* Interrupt controller */
356 struct vgic_dist vgic;
357
358 /* Timers */
359 struct arch_timer_vm_data timer_data;
360
361 /* Mandated version of PSCI */
362 u32 psci_version;
363
364 /* Protects VM-scoped configuration data */
365 struct mutex config_lock;
366
367 /*
368 * If we encounter a data abort without valid instruction syndrome
369 * information, report this to user space. User space can (and
370 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
371 * supported.
372 */
373 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0
374 /* Memory Tagging Extension enabled for the guest */
375 #define KVM_ARCH_FLAG_MTE_ENABLED 1
376 /* At least one vCPU has ran in the VM */
377 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2
378 /* The vCPU feature set for the VM is configured */
379 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED 3
380 /* PSCI SYSTEM_SUSPEND enabled for the guest */
381 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 4
382 /* VM counter offset */
383 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET 5
384 /* Timer PPIs made immutable */
385 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE 6
386 /* Initial ID reg values loaded */
387 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED 7
388 /* Fine-Grained UNDEF initialised */
389 #define KVM_ARCH_FLAG_FGU_INITIALIZED 8
390 /* SVE exposed to guest */
391 #define KVM_ARCH_FLAG_GUEST_HAS_SVE 9
392 /* Guest has bought into the MMIO guard extension */
393 #define KVM_ARCH_FLAG_MMIO_GUARD 10
394 unsigned long flags;
395
396 /* VM-wide vCPU feature set */
397 DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES);
398
399 /* MPIDR to vcpu index mapping, optional */
400 struct kvm_mpidr_data *mpidr_data;
401
402 /*
403 * VM-wide PMU filter, implemented as a bitmap and big enough for
404 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
405 */
406 unsigned long *pmu_filter;
407 struct arm_pmu *arm_pmu;
408
409 cpumask_var_t supported_cpus;
410
411 /* PMCR_EL0.N value for the guest */
412 u8 pmcr_n;
413
414 /* Iterator for idreg debugfs */
415 u8 idreg_debugfs_iter;
416
417 /* Hypercall features firmware registers' descriptor */
418 struct kvm_smccc_features smccc_feat;
419 struct maple_tree smccc_filter;
420
421 /*
422 * Emulated CPU ID registers per VM
423 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it
424 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
425 *
426 * These emulated idregs are VM-wide, but accessed from the context of a vCPU.
427 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock.
428 */
429 #define IDREG_IDX(id) (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id))
430 #define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1)
431 u64 id_regs[KVM_ARM_ID_REG_NUM];
432
433 u64 ctr_el0;
434
435 /* Masks for VNCR-baked sysregs */
436 struct kvm_sysreg_masks *sysreg_masks;
437
438 /*
439 * For an untrusted host VM, 'pkvm.handle' is used to lookup
440 * the associated pKVM instance in the hypervisor.
441 */
442 struct kvm_protected_vm pkvm;
443 };
444
445 struct kvm_vcpu_fault_info {
446 u64 esr_el2; /* Hyp Syndrom Register */
447 u64 far_el2; /* Hyp Fault Address Register */
448 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
449 u64 disr_el1; /* Deferred [SError] Status Register */
450 };
451
452 /*
453 * VNCR() just places the VNCR_capable registers in the enum after
454 * __VNCR_START__, and the value (after correction) to be an 8-byte offset
455 * from the VNCR base. As we don't require the enum to be otherwise ordered,
456 * we need the terrible hack below to ensure that we correctly size the
457 * sys_regs array, no matter what.
458 *
459 * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful
460 * treasure trove of bit hacks:
461 * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax
462 */
463 #define __MAX__(x,y) ((x) ^ (((x) ^ (y)) & -((x) < (y))))
464 #define VNCR(r) \
465 __before_##r, \
466 r = __VNCR_START__ + ((VNCR_ ## r) / 8), \
467 __after_##r = __MAX__(__before_##r - 1, r)
468
469 enum vcpu_sysreg {
470 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
471 MPIDR_EL1, /* MultiProcessor Affinity Register */
472 CLIDR_EL1, /* Cache Level ID Register */
473 CSSELR_EL1, /* Cache Size Selection Register */
474 TPIDR_EL0, /* Thread ID, User R/W */
475 TPIDRRO_EL0, /* Thread ID, User R/O */
476 TPIDR_EL1, /* Thread ID, Privileged */
477 CNTKCTL_EL1, /* Timer Control Register (EL1) */
478 PAR_EL1, /* Physical Address Register */
479 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
480 OSLSR_EL1, /* OS Lock Status Register */
481 DISR_EL1, /* Deferred Interrupt Status Register */
482
483 /* Performance Monitors Registers */
484 PMCR_EL0, /* Control Register */
485 PMSELR_EL0, /* Event Counter Selection Register */
486 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
487 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
488 PMCCNTR_EL0, /* Cycle Counter Register */
489 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
490 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
491 PMCCFILTR_EL0, /* Cycle Count Filter Register */
492 PMCNTENSET_EL0, /* Count Enable Set Register */
493 PMINTENSET_EL1, /* Interrupt Enable Set Register */
494 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
495 PMUSERENR_EL0, /* User Enable Register */
496
497 /* Pointer Authentication Registers in a strict increasing order. */
498 APIAKEYLO_EL1,
499 APIAKEYHI_EL1,
500 APIBKEYLO_EL1,
501 APIBKEYHI_EL1,
502 APDAKEYLO_EL1,
503 APDAKEYHI_EL1,
504 APDBKEYLO_EL1,
505 APDBKEYHI_EL1,
506 APGAKEYLO_EL1,
507 APGAKEYHI_EL1,
508
509 /* Memory Tagging Extension registers */
510 RGSR_EL1, /* Random Allocation Tag Seed Register */
511 GCR_EL1, /* Tag Control Register */
512 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */
513
514 POR_EL0, /* Permission Overlay Register 0 (EL0) */
515
516 /* FP/SIMD/SVE */
517 SVCR,
518 FPMR,
519
520 /* 32bit specific registers. */
521 DACR32_EL2, /* Domain Access Control Register */
522 IFSR32_EL2, /* Instruction Fault Status Register */
523 FPEXC32_EL2, /* Floating-Point Exception Control Register */
524 DBGVCR32_EL2, /* Debug Vector Catch Register */
525
526 /* EL2 registers */
527 SCTLR_EL2, /* System Control Register (EL2) */
528 ACTLR_EL2, /* Auxiliary Control Register (EL2) */
529 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */
530 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */
531 HACR_EL2, /* Hypervisor Auxiliary Control Register */
532 ZCR_EL2, /* SVE Control Register (EL2) */
533 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */
534 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */
535 TCR_EL2, /* Translation Control Register (EL2) */
536 SPSR_EL2, /* EL2 saved program status register */
537 ELR_EL2, /* EL2 exception link register */
538 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */
539 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */
540 ESR_EL2, /* Exception Syndrome Register (EL2) */
541 FAR_EL2, /* Fault Address Register (EL2) */
542 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */
543 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */
544 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */
545 VBAR_EL2, /* Vector Base Address Register (EL2) */
546 RVBAR_EL2, /* Reset Vector Base Address Register */
547 CONTEXTIDR_EL2, /* Context ID Register (EL2) */
548 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
549 SP_EL2, /* EL2 Stack Pointer */
550 CNTHP_CTL_EL2,
551 CNTHP_CVAL_EL2,
552 CNTHV_CTL_EL2,
553 CNTHV_CVAL_EL2,
554
555 __VNCR_START__, /* Any VNCR-capable reg goes after this point */
556
557 VNCR(SCTLR_EL1),/* System Control Register */
558 VNCR(ACTLR_EL1),/* Auxiliary Control Register */
559 VNCR(CPACR_EL1),/* Coprocessor Access Control */
560 VNCR(ZCR_EL1), /* SVE Control */
561 VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */
562 VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */
563 VNCR(TCR_EL1), /* Translation Control Register */
564 VNCR(TCR2_EL1), /* Extended Translation Control Register */
565 VNCR(ESR_EL1), /* Exception Syndrome Register */
566 VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */
567 VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */
568 VNCR(FAR_EL1), /* Fault Address Register */
569 VNCR(MAIR_EL1), /* Memory Attribute Indirection Register */
570 VNCR(VBAR_EL1), /* Vector Base Address Register */
571 VNCR(CONTEXTIDR_EL1), /* Context ID Register */
572 VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */
573 VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */
574 VNCR(ELR_EL1),
575 VNCR(SP_EL1),
576 VNCR(SPSR_EL1),
577 VNCR(TFSR_EL1), /* Tag Fault Status Register (EL1) */
578 VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */
579 VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */
580 VNCR(HCR_EL2), /* Hypervisor Configuration Register */
581 VNCR(HSTR_EL2), /* Hypervisor System Trap Register */
582 VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */
583 VNCR(VTCR_EL2), /* Virtualization Translation Control Register */
584 VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */
585 VNCR(HCRX_EL2), /* Extended Hypervisor Configuration Register */
586
587 /* Permission Indirection Extension registers */
588 VNCR(PIR_EL1), /* Permission Indirection Register 1 (EL1) */
589 VNCR(PIRE0_EL1), /* Permission Indirection Register 0 (EL1) */
590
591 VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */
592
593 VNCR(HFGRTR_EL2),
594 VNCR(HFGWTR_EL2),
595 VNCR(HFGITR_EL2),
596 VNCR(HDFGRTR_EL2),
597 VNCR(HDFGWTR_EL2),
598 VNCR(HAFGRTR_EL2),
599
600 VNCR(CNTVOFF_EL2),
601 VNCR(CNTV_CVAL_EL0),
602 VNCR(CNTV_CTL_EL0),
603 VNCR(CNTP_CVAL_EL0),
604 VNCR(CNTP_CTL_EL0),
605
606 VNCR(ICH_HCR_EL2),
607
608 NR_SYS_REGS /* Nothing after this line! */
609 };
610
611 struct kvm_sysreg_masks {
612 struct {
613 u64 res0;
614 u64 res1;
615 } mask[NR_SYS_REGS - __VNCR_START__];
616 };
617
618 struct kvm_cpu_context {
619 struct user_pt_regs regs; /* sp = sp_el0 */
620
621 u64 spsr_abt;
622 u64 spsr_und;
623 u64 spsr_irq;
624 u64 spsr_fiq;
625
626 struct user_fpsimd_state fp_regs;
627
628 u64 sys_regs[NR_SYS_REGS];
629
630 struct kvm_vcpu *__hyp_running_vcpu;
631
632 /* This pointer has to be 4kB aligned. */
633 u64 *vncr_array;
634 };
635
636 struct cpu_sve_state {
637 __u64 zcr_el1;
638
639 /*
640 * Ordering is important since __sve_save_state/__sve_restore_state
641 * relies on it.
642 */
643 __u32 fpsr;
644 __u32 fpcr;
645
646 /* Must be SVE_VQ_BYTES (128 bit) aligned. */
647 __u8 sve_regs[];
648 };
649
650 /*
651 * This structure is instantiated on a per-CPU basis, and contains
652 * data that is:
653 *
654 * - tied to a single physical CPU, and
655 * - either have a lifetime that does not extend past vcpu_put()
656 * - or is an invariant for the lifetime of the system
657 *
658 * Use host_data_ptr(field) as a way to access a pointer to such a
659 * field.
660 */
661 struct kvm_host_data {
662 struct kvm_cpu_context host_ctxt;
663
664 /*
665 * Hyp VA.
666 * sve_state is only used in pKVM and if system_supports_sve().
667 */
668 struct cpu_sve_state *sve_state;
669
670 /* Used by pKVM only. */
671 u64 fpmr;
672
673 /* Ownership of the FP regs */
674 enum {
675 FP_STATE_FREE,
676 FP_STATE_HOST_OWNED,
677 FP_STATE_GUEST_OWNED,
678 } fp_owner;
679
680 /*
681 * host_debug_state contains the host registers which are
682 * saved and restored during world switches.
683 */
684 struct {
685 /* {Break,watch}point registers */
686 struct kvm_guest_debug_arch regs;
687 /* Statistical profiling extension */
688 u64 pmscr_el1;
689 /* Self-hosted trace */
690 u64 trfcr_el1;
691 /* Values of trap registers for the host before guest entry. */
692 u64 mdcr_el2;
693 } host_debug_state;
694 };
695
696 struct kvm_host_psci_config {
697 /* PSCI version used by host. */
698 u32 version;
699 u32 smccc_version;
700
701 /* Function IDs used by host if version is v0.1. */
702 struct psci_0_1_function_ids function_ids_0_1;
703
704 bool psci_0_1_cpu_suspend_implemented;
705 bool psci_0_1_cpu_on_implemented;
706 bool psci_0_1_cpu_off_implemented;
707 bool psci_0_1_migrate_implemented;
708 };
709
710 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
711 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
712
713 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
714 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
715
716 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
717 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
718
719 struct vcpu_reset_state {
720 unsigned long pc;
721 unsigned long r0;
722 bool be;
723 bool reset;
724 };
725
726 struct kvm_hyp_req {
727 #define KVM_HYP_LAST_REQ 0
728 #define KVM_HYP_REQ_TYPE_MEM 1
729 #define KVM_HYP_REQ_TYPE_MAP 2
730 #define KVM_HYP_REQ_TYPE_SPLIT 3
731 u8 type;
732 union {
733 struct {
734 #define REQ_MEM_DEST_HYP_ALLOC 1
735 #define REQ_MEM_DEST_VCPU_MEMCACHE 2
736 #define REQ_MEM_DEST_HYP_IOMMU 3
737 u8 dest;
738 int nr_pages;
739 int sz_alloc; /* Size of the page. */
740 } mem;
741 struct {
742 unsigned long guest_ipa;
743 size_t size;
744 } map;
745 struct {
746 unsigned long guest_ipa;
747 size_t size;
748 } split;
749 };
750 };
751
752 #define KVM_HYP_REQ_MAX ((PAGE_SIZE >> 4) / sizeof(struct kvm_hyp_req))
753
754 /*
755 * Hypervisor version of kvm_pinned_page. Typically stored in per-vCPU hyp_req
756 * page. Packed to allow the biggest possible sglist. 40-bits PFN being the
757 * biggest PA_BITS value (52) - minimum PAGE_SHIFT (12).
758 */
759 struct kvm_hyp_pinned_page {
760 u64 pfn : 40;
761 u64 gfn : 40;
762 u8 order;
763 } __packed;
764
765 /*
766 * Get the kvm_hyp_pinned_page after @ppage for the array found in the shared page kvm_hyp_req.
767 * Also check the entry when @valid is set (useful to read the array).
768 */
769 static inline struct kvm_hyp_pinned_page *
next_kvm_hyp_pinned_page(struct kvm_hyp_req * page,struct kvm_hyp_pinned_page * ppage,bool valid)770 next_kvm_hyp_pinned_page(struct kvm_hyp_req *page, struct kvm_hyp_pinned_page *ppage, bool valid)
771 {
772 void *start = (void *)(page + KVM_HYP_REQ_MAX);
773 void *end = (void *)page + PAGE_SIZE;
774
775 if (WARN_ON(!PAGE_ALIGNED(page)))
776 return NULL;
777
778 if (!ppage)
779 ppage = (struct kvm_hyp_pinned_page *)start;
780 else
781 ppage++;
782
783 if (((void *)ppage + sizeof(*ppage)) >= end)
784 return NULL;
785
786 if (valid && (ppage->order == 0xFF))
787 return NULL;
788
789 return ppage;
790 }
791
792 /*
793 * De-serialize request from SMCCC return.
794 * See hyp-main.c for serialization.
795 */
796 /* Register a2. */
797 #define SMCCC_REQ_TYPE_MASK GENMASK_ULL(7, 0)
798 #define SMCCC_REQ_DEST_MASK GENMASK_ULL(15, 8)
799 /* Register a3. */
800 #define SMCCC_REQ_NR_PAGES_MASK GENMASK_ULL(31, 0)
801 #define SMCCC_REQ_SZ_ALLOC_MASK GENMASK_ULL(63, 32)
802
hyp_reqs_smccc_decode(struct arm_smccc_res * res,struct kvm_hyp_req * req)803 static inline void hyp_reqs_smccc_decode(struct arm_smccc_res *res,
804 struct kvm_hyp_req *req)
805 {
806 req->type = FIELD_GET(SMCCC_REQ_TYPE_MASK, res->a2);
807 req->mem.dest = FIELD_GET(SMCCC_REQ_DEST_MASK, res->a2);
808 req->mem.nr_pages = FIELD_GET(SMCCC_REQ_NR_PAGES_MASK, res->a3);
809 req->mem.sz_alloc = FIELD_GET(SMCCC_REQ_SZ_ALLOC_MASK, res->a3);
810 }
811
812 struct kvm_vcpu_arch {
813 struct kvm_cpu_context ctxt;
814
815 /*
816 * Guest floating point state
817 *
818 * The architecture has two main floating point extensions,
819 * the original FPSIMD and SVE. These have overlapping
820 * register views, with the FPSIMD V registers occupying the
821 * low 128 bits of the SVE Z registers. When the core
822 * floating point code saves the register state of a task it
823 * records which view it saved in fp_type.
824 */
825 void *sve_state;
826 enum fp_type fp_type;
827 unsigned int sve_max_vl;
828
829 /* Stage 2 paging state used by the hardware on next switch */
830 struct kvm_s2_mmu *hw_mmu;
831
832 /* Values of trap registers for the guest. */
833 u64 hcr_el2;
834 u64 hcrx_el2;
835 u64 mdcr_el2;
836
837 /* Exception Information */
838 struct kvm_vcpu_fault_info fault;
839
840 /* Configuration flags, set once and for all before the vcpu can run */
841 u8 cflags;
842
843 /* Input flags to the hypervisor code, potentially cleared after use */
844 u8 iflags;
845
846 /* State flags for kernel bookkeeping, unused by the hypervisor code */
847 u8 sflags;
848
849 /*
850 * Don't run the guest (internal implementation need).
851 *
852 * Contrary to the flags above, this is set/cleared outside of
853 * a vcpu context, and thus cannot be mixed with the flags
854 * themselves (or the flag accesses need to be made atomic).
855 */
856 bool pause;
857
858 /*
859 * We maintain more than a single set of debug registers to support
860 * debugging the guest from the host and to maintain separate host and
861 * guest state during world switches. vcpu_debug_state are the debug
862 * registers of the vcpu as the guest sees them.
863 *
864 * external_debug_state contains the debug values we want to debug the
865 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl.
866 *
867 * debug_ptr points to the set of debug registers that should be loaded
868 * onto the hardware when running the guest.
869 */
870 struct kvm_guest_debug_arch *debug_ptr;
871 struct kvm_guest_debug_arch vcpu_debug_state;
872 struct kvm_guest_debug_arch external_debug_state;
873
874 /* VGIC state */
875 struct vgic_cpu vgic_cpu;
876 struct arch_timer_cpu timer_cpu;
877 struct kvm_pmu pmu;
878
879 /*
880 * Guest registers we preserve during guest debugging.
881 *
882 * These shadow registers are updated by the kvm_handle_sys_reg
883 * trap handler if the guest accesses or updates them while we
884 * are using guest debug.
885 */
886 struct {
887 u32 mdscr_el1;
888 bool pstate_ss;
889 } guest_debug_preserved;
890
891 /* vcpu power state */
892 struct kvm_mp_state mp_state;
893 spinlock_t mp_state_lock;
894
895 union {
896 /* Cache some mmu pages needed inside spinlock regions */
897 struct kvm_mmu_memory_cache mmu_page_cache;
898 /* Pages to be donated to pkvm/EL2 if it runs out */
899 struct kvm_hyp_memcache stage2_mc;
900 };
901
902 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
903 u64 vsesr_el2;
904
905 /* Additional reset state */
906 struct vcpu_reset_state reset_state;
907
908 /* Guest PV state */
909 struct {
910 u64 last_steal;
911 gpa_t base;
912 } steal;
913
914 /* Per-vcpu CCSIDR override or NULL */
915 u32 *ccsidr;
916
917 /* mem cache for pvIOMMU usage in guests. */
918 struct kvm_hyp_memcache iommu_mc;
919
920 /* PAGE_SIZE bound list of requests from the hypervisor to the host. */
921 struct kvm_hyp_req *hyp_reqs;
922 };
923
924 /*
925 * Each 'flag' is composed of a comma-separated triplet:
926 *
927 * - the flag-set it belongs to in the vcpu->arch structure
928 * - the value for that flag
929 * - the mask for that flag
930 *
931 * __vcpu_single_flag() builds such a triplet for a single-bit flag.
932 * unpack_vcpu_flag() extract the flag value from the triplet for
933 * direct use outside of the flag accessors.
934 */
935 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f)
936
937 #define __unpack_flag(_set, _f, _m) _f
938 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__)
939
940 #define __build_check_flag(v, flagset, f, m) \
941 do { \
942 typeof(v->arch.flagset) *_fset; \
943 \
944 /* Check that the flags fit in the mask */ \
945 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
946 /* Check that the flags fit in the type */ \
947 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
948 } while (0)
949
950 #define __vcpu_get_flag(v, flagset, f, m) \
951 ({ \
952 __build_check_flag(v, flagset, f, m); \
953 \
954 READ_ONCE(v->arch.flagset) & (m); \
955 })
956
957 /*
958 * Note that the set/clear accessors must be preempt-safe in order to
959 * avoid nesting them with load/put which also manipulate flags...
960 */
961 #ifdef __KVM_NVHE_HYPERVISOR__
962 /* the nVHE hypervisor is always non-preemptible */
963 #define __vcpu_flags_preempt_disable()
964 #define __vcpu_flags_preempt_enable()
965 #else
966 #define __vcpu_flags_preempt_disable() preempt_disable()
967 #define __vcpu_flags_preempt_enable() preempt_enable()
968 #endif
969
970 #define __vcpu_set_flag(v, flagset, f, m) \
971 do { \
972 typeof(v->arch.flagset) *fset; \
973 \
974 __build_check_flag(v, flagset, f, m); \
975 \
976 fset = &v->arch.flagset; \
977 __vcpu_flags_preempt_disable(); \
978 if (HWEIGHT(m) > 1) \
979 *fset &= ~(m); \
980 *fset |= (f); \
981 __vcpu_flags_preempt_enable(); \
982 } while (0)
983
984 #define __vcpu_clear_flag(v, flagset, f, m) \
985 do { \
986 typeof(v->arch.flagset) *fset; \
987 \
988 __build_check_flag(v, flagset, f, m); \
989 \
990 fset = &v->arch.flagset; \
991 __vcpu_flags_preempt_disable(); \
992 *fset &= ~(m); \
993 __vcpu_flags_preempt_enable(); \
994 } while (0)
995
996 #define __vcpu_copy_flag(vt, vs, flagset, f, m) \
997 do { \
998 typeof(vs->arch.flagset) tmp, val; \
999 \
1000 __build_check_flag(vs, flagset, f, m); \
1001 \
1002 val = READ_ONCE(vs->arch.flagset); \
1003 val &= (m); \
1004 tmp = READ_ONCE(vt->arch.flagset); \
1005 tmp &= ~(m); \
1006 tmp |= val; \
1007 WRITE_ONCE(vt->arch.flagset, tmp); \
1008 } while (0)
1009
1010
1011 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__)
1012 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__)
1013 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
1014 #define vcpu_copy_flag(vt, vs, ...) __vcpu_copy_flag((vt), (vs), __VA_ARGS__)
1015
1016 /* KVM_ARM_VCPU_INIT completed */
1017 #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0))
1018 /* SVE config completed */
1019 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1))
1020 /* pKVM VCPU setup completed */
1021 #define VCPU_PKVM_FINALIZED __vcpu_single_flag(cflags, BIT(2))
1022
1023 /* Exception pending */
1024 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0))
1025 /*
1026 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
1027 * be set together with an exception...
1028 */
1029 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1))
1030 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
1031 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1))
1032 /* Cover both PENDING_EXCEPTION and EXCEPT_MASK for global operations */
1033 #define PC_UPDATE_REQ __vcpu_single_flag(iflags, GENMASK(3, 0))
1034
1035 /* Helpers to encode exceptions with minimum fuss */
1036 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK)
1037 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL)
1038 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
1039
1040 /*
1041 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
1042 * values:
1043 *
1044 * For AArch32 EL1:
1045 */
1046 #define EXCEPT_AA32_UND __vcpu_except_flags(0)
1047 #define EXCEPT_AA32_IABT __vcpu_except_flags(1)
1048 #define EXCEPT_AA32_DABT __vcpu_except_flags(2)
1049 /* For AArch64: */
1050 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0)
1051 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1)
1052 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2)
1053 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3)
1054 /* For AArch64 with NV: */
1055 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4)
1056 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5)
1057 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6)
1058 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7)
1059 /* Guest debug is live */
1060 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4))
1061 /* Save SPE context if active */
1062 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5))
1063 /* Save TRBE context if active */
1064 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6))
1065 /* vcpu running in HYP context (VHE-only) */
1066 #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7))
1067 /* pKVM host vcpu state is dirty, needs resync (nVHE-only) */
1068 #define PKVM_HOST_STATE_DIRTY __vcpu_single_flag(iflags, BIT(7))
1069
1070 /* Physical CPU not in supported_cpus */
1071 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2))
1072 /* WFIT instruction trapped */
1073 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3))
1074 /* vcpu system registers loaded on physical CPU */
1075 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4))
1076 /* Software step state is Active-pending */
1077 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5))
1078 /* PMUSERENR for the guest EL0 is on physical CPU */
1079 #define PMUSERENR_ON_CPU __vcpu_single_flag(sflags, BIT(6))
1080 /* WFI instruction trapped */
1081 #define IN_WFI __vcpu_single_flag(sflags, BIT(7))
1082
1083
1084 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
1085 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \
1086 sve_ffr_offset((vcpu)->arch.sve_max_vl))
1087
1088 #define vcpu_sve_zcr_elx(vcpu) \
1089 (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1)
1090
1091 #define sve_state_size(sve_max_vl) ({ \
1092 size_t __size_ret; \
1093 unsigned int __vq; \
1094 \
1095 if (WARN_ON(!sve_vl_valid(sve_max_vl))) { \
1096 __size_ret = 0; \
1097 } else { \
1098 __vq = sve_vq_from_vl(sve_max_vl); \
1099 __size_ret = SVE_SIG_REGS_SIZE(__vq); \
1100 } \
1101 \
1102 __size_ret; \
1103 })
1104
1105 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl)
1106
1107 #define vcpu_sve_state_size(vcpu) sve_state_size((vcpu)->arch.sve_max_vl)
1108
1109 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
1110 KVM_GUESTDBG_USE_SW_BP | \
1111 KVM_GUESTDBG_USE_HW | \
1112 KVM_GUESTDBG_SINGLESTEP)
1113
1114 #define kvm_has_sve(kvm) (system_supports_sve() && \
1115 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags))
1116
1117 #ifdef __KVM_NVHE_HYPERVISOR__
1118 #define vcpu_has_sve(vcpu) kvm_has_sve(kern_hyp_va((vcpu)->kvm))
1119 #else
1120 #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm)
1121 #endif
1122
1123 #ifdef CONFIG_ARM64_PTR_AUTH
1124 #define vcpu_has_ptrauth(vcpu) \
1125 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \
1126 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \
1127 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || \
1128 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC)))
1129 #else
1130 #define vcpu_has_ptrauth(vcpu) false
1131 #endif
1132
1133 #define vcpu_on_unsupported_cpu(vcpu) \
1134 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
1135
1136 #define vcpu_set_on_unsupported_cpu(vcpu) \
1137 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
1138
1139 #define vcpu_clear_on_unsupported_cpu(vcpu) \
1140 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
1141
1142 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs)
1143
1144 /*
1145 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
1146 * memory backed version of a register, and not the one most recently
1147 * accessed by a running VCPU. For example, for userspace access or
1148 * for system registers that are never context switched, but only
1149 * emulated.
1150 *
1151 * Don't bother with VNCR-based accesses in the nVHE code, it has no
1152 * business dealing with NV.
1153 */
___ctxt_sys_reg(const struct kvm_cpu_context * ctxt,int r)1154 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
1155 {
1156 #if !defined (__KVM_NVHE_HYPERVISOR__)
1157 if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) &&
1158 r >= __VNCR_START__ && ctxt->vncr_array))
1159 return &ctxt->vncr_array[r - __VNCR_START__];
1160 #endif
1161 return (u64 *)&ctxt->sys_regs[r];
1162 }
1163
1164 #define __ctxt_sys_reg(c,r) \
1165 ({ \
1166 BUILD_BUG_ON(__builtin_constant_p(r) && \
1167 (r) >= NR_SYS_REGS); \
1168 ___ctxt_sys_reg(c, r); \
1169 })
1170
1171 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
1172
1173 u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *, enum vcpu_sysreg);
1174 #define __vcpu_sys_reg(v,r) \
1175 (*({ \
1176 const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
1177 u64 *__r = __ctxt_sys_reg(ctxt, (r)); \
1178 if (vcpu_has_nv((v)) && (r) >= __VNCR_START__) \
1179 *__r = kvm_vcpu_sanitise_vncr_reg((v), (r)); \
1180 __r; \
1181 }))
1182
__vcpu_read_sys_reg_from_cpu(int reg,u64 * val)1183 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
1184 {
1185 /*
1186 * *** VHE ONLY ***
1187 *
1188 * System registers listed in the switch are not saved on every
1189 * exit from the guest but are only saved on vcpu_put.
1190 *
1191 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1192 * should never be listed below, because the guest cannot modify its
1193 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
1194 * thread when emulating cross-VCPU communication.
1195 */
1196 if (!has_vhe())
1197 return false;
1198
1199 switch (reg) {
1200 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
1201 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
1202 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
1203 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
1204 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
1205 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
1206 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
1207 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
1208 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
1209 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
1210 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
1211 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
1212 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
1213 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
1214 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
1215 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
1216 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
1217 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
1218 case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break;
1219 case PAR_EL1: *val = read_sysreg_par(); break;
1220 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
1221 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
1222 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
1223 case ZCR_EL1: *val = read_sysreg_s(SYS_ZCR_EL12); break;
1224 default: return false;
1225 }
1226
1227 return true;
1228 }
1229
__vcpu_write_sys_reg_to_cpu(u64 val,int reg)1230 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
1231 {
1232 /*
1233 * *** VHE ONLY ***
1234 *
1235 * System registers listed in the switch are not restored on every
1236 * entry to the guest but are only restored on vcpu_load.
1237 *
1238 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1239 * should never be listed below, because the MPIDR should only be set
1240 * once, before running the VCPU, and never changed later.
1241 */
1242 if (!has_vhe())
1243 return false;
1244
1245 switch (reg) {
1246 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
1247 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
1248 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
1249 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
1250 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
1251 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
1252 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
1253 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
1254 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
1255 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
1256 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
1257 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
1258 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
1259 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
1260 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
1261 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
1262 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
1263 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
1264 case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
1265 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
1266 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
1267 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
1268 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
1269 case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break;
1270 default: return false;
1271 }
1272
1273 return true;
1274 }
1275
1276 struct kvm_vm_stat {
1277 struct kvm_vm_stat_generic generic;
1278 atomic64_t protected_hyp_mem;
1279 atomic64_t protected_shared_mem;
1280 };
1281
1282 struct kvm_vcpu_stat {
1283 struct kvm_vcpu_stat_generic generic;
1284 u64 hvc_exit_stat;
1285 u64 wfe_exit_stat;
1286 u64 wfi_exit_stat;
1287 u64 mmio_exit_user;
1288 u64 mmio_exit_kernel;
1289 u64 signal_exits;
1290 u64 exits;
1291 };
1292
1293 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
1294 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
1295 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
1296 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
1297
1298 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
1299 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
1300
1301 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
1302 struct kvm_vcpu_events *events);
1303
1304 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
1305 struct kvm_vcpu_events *events);
1306
1307 void kvm_arm_halt_guest(struct kvm *kvm);
1308 void kvm_arm_resume_guest(struct kvm *kvm);
1309
1310 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid)
1311
1312 #ifndef __KVM_NVHE_HYPERVISOR__
1313 #define kvm_call_hyp_nvhe_smccc(f, ...) \
1314 ({ \
1315 struct arm_smccc_res res; \
1316 \
1317 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
1318 ##__VA_ARGS__, &res); \
1319 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
1320 \
1321 res; \
1322 })
1323
1324 #define kvm_call_hyp_nvhe(f, ...) \
1325 ({ \
1326 struct arm_smccc_res res; \
1327 \
1328 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
1329 ##__VA_ARGS__, &res); \
1330 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
1331 \
1332 res.a1; \
1333 })
1334
1335 /*
1336 * The couple of isb() below are there to guarantee the same behaviour
1337 * on VHE as on !VHE, where the eret to EL1 acts as a context
1338 * synchronization event.
1339 */
1340 #define kvm_call_hyp(f, ...) \
1341 do { \
1342 if (has_vhe()) { \
1343 f(__VA_ARGS__); \
1344 isb(); \
1345 } else { \
1346 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
1347 } \
1348 } while(0)
1349
1350 #define kvm_call_hyp_ret(f, ...) \
1351 ({ \
1352 typeof(f(__VA_ARGS__)) ret; \
1353 \
1354 if (has_vhe()) { \
1355 ret = f(__VA_ARGS__); \
1356 isb(); \
1357 } else { \
1358 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
1359 } \
1360 \
1361 ret; \
1362 })
1363 #else /* __KVM_NVHE_HYPERVISOR__ */
1364 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
1365 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
1366 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
1367 #endif /* __KVM_NVHE_HYPERVISOR__ */
1368
1369 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
1370 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
1371
1372 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
1373 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
1374 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
1375 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
1376 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
1377 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
1378 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
1379
1380 void kvm_sys_regs_create_debugfs(struct kvm *kvm);
1381 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
1382
1383 int __init kvm_sys_reg_table_init(void);
1384 struct sys_reg_desc;
1385 int __init populate_sysreg_config(const struct sys_reg_desc *sr,
1386 unsigned int idx);
1387 int __init populate_nv_trap_config(void);
1388
1389 bool lock_all_vcpus(struct kvm *kvm);
1390 void unlock_all_vcpus(struct kvm *kvm);
1391
1392 void kvm_calculate_traps(struct kvm_vcpu *vcpu);
1393
1394 /* MMIO helpers */
1395 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
1396 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
1397
1398 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
1399 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
1400
1401 /*
1402 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
1403 * arrived in guest context. For arm64, any event that arrives while a vCPU is
1404 * loaded is considered to be "in guest".
1405 */
kvm_arch_pmi_in_guest(struct kvm_vcpu * vcpu)1406 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
1407 {
1408 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
1409 }
1410
1411 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
1412 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
1413 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
1414
1415 bool kvm_arm_pvtime_supported(void);
1416 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
1417 struct kvm_device_attr *attr);
1418 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
1419 struct kvm_device_attr *attr);
1420 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
1421 struct kvm_device_attr *attr);
1422
1423 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
1424 int __init kvm_arm_vmid_alloc_init(void);
1425 void __init kvm_arm_vmid_alloc_free(void);
1426 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
1427 void kvm_arm_vmid_clear_active(void);
1428
kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)1429 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
1430 {
1431 vcpu_arch->steal.base = INVALID_GPA;
1432 }
1433
kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)1434 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
1435 {
1436 return (vcpu_arch->steal.base != INVALID_GPA);
1437 }
1438
1439 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
1440
1441 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
1442
1443 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
1444
1445 /*
1446 * How we access per-CPU host data depends on the where we access it from,
1447 * and the mode we're in:
1448 *
1449 * - VHE and nVHE hypervisor bits use their locally defined instance
1450 *
1451 * - the rest of the kernel use either the VHE or nVHE one, depending on
1452 * the mode we're running in.
1453 *
1454 * Unless we're in protected mode, fully deprivileged, and the nVHE
1455 * per-CPU stuff is exclusively accessible to the protected EL2 code.
1456 * In this case, the EL1 code uses the *VHE* data as its private state
1457 * (which makes sense in a way as there shouldn't be any shared state
1458 * between the host and the hypervisor).
1459 *
1460 * Yes, this is all totally trivial. Shoot me now.
1461 */
1462 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
1463 #define host_data_ptr(f) (&this_cpu_ptr(&kvm_host_data)->f)
1464 #else
1465 #define host_data_ptr(f) \
1466 (static_branch_unlikely(&kvm_protected_mode_initialized) ? \
1467 &this_cpu_ptr(&kvm_host_data)->f : \
1468 &this_cpu_ptr_hyp_sym(kvm_host_data)->f)
1469 #endif
1470
1471 /* Check whether the FP regs are owned by the guest */
guest_owns_fp_regs(void)1472 static inline bool guest_owns_fp_regs(void)
1473 {
1474 return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED;
1475 }
1476
1477 /* Check whether the FP regs are owned by the host */
host_owns_fp_regs(void)1478 static inline bool host_owns_fp_regs(void)
1479 {
1480 return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED;
1481 }
1482
kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)1483 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
1484 {
1485 /* The host's MPIDR is immutable, so let's set it up at boot time */
1486 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
1487 }
1488
kvm_system_needs_idmapped_vectors(void)1489 static inline bool kvm_system_needs_idmapped_vectors(void)
1490 {
1491 return cpus_have_final_cap(ARM64_SPECTRE_V3A);
1492 }
1493
kvm_arch_sync_events(struct kvm * kvm)1494 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
1495
1496 void kvm_arm_init_debug(void);
1497 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
1498 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
1499 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
1500 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
1501
1502 #define __vcpu_save_guest_debug_regs(vcpu) \
1503 do { \
1504 u64 val = vcpu_read_sys_reg(vcpu, MDSCR_EL1); \
1505 \
1506 (vcpu)->arch.guest_debug_preserved.mdscr_el1 = val; \
1507 } while(0)
1508
1509 #define __vcpu_restore_guest_debug_regs(vcpu) \
1510 do { \
1511 u64 val = (vcpu)->arch.guest_debug_preserved.mdscr_el1; \
1512 \
1513 vcpu_write_sys_reg(vcpu, val, MDSCR_EL1); \
1514 } while (0)
1515
1516 #define kvm_vcpu_os_lock_enabled(vcpu) \
1517 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK))
1518
1519 #define kvm_vcpu_needs_debug_regs(vcpu) \
1520 ((vcpu)->guest_debug || kvm_vcpu_os_lock_enabled(vcpu))
1521
1522 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1523 struct kvm_device_attr *attr);
1524 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1525 struct kvm_device_attr *attr);
1526 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1527 struct kvm_device_attr *attr);
1528
1529 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1530 struct kvm_arm_copy_mte_tags *copy_tags);
1531 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
1532 struct kvm_arm_counter_offset *offset);
1533 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm,
1534 struct reg_mask_range *range);
1535
1536 /* Guest/host FPSIMD coordination helpers */
1537 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1538 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1539 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1540 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1541 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1542
kvm_pmu_counter_deferred(struct perf_event_attr * attr)1543 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1544 {
1545 return (!has_vhe() && attr->exclude_host);
1546 }
1547
1548 /* Flags for host debug state */
1549 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
1550 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
1551
1552 #ifdef CONFIG_KVM
1553 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr);
1554 void kvm_clr_pmu_events(u64 clr);
1555 bool kvm_set_pmuserenr(u64 val);
1556 #else
kvm_set_pmu_events(u64 set,struct perf_event_attr * attr)1557 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {}
kvm_clr_pmu_events(u64 clr)1558 static inline void kvm_clr_pmu_events(u64 clr) {}
kvm_set_pmuserenr(u64 val)1559 static inline bool kvm_set_pmuserenr(u64 val)
1560 {
1561 return false;
1562 }
1563 #endif
1564
1565 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu);
1566 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu);
1567
1568 int __init kvm_set_ipa_limit(void);
1569 u32 kvm_get_pa_bits(struct kvm *kvm);
1570
1571 #define __KVM_HAVE_ARCH_VM_ALLOC
1572 struct kvm *kvm_arch_alloc_vm(void);
1573
1574 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS
1575
1576 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE
1577
1578 #define kvm_vm_is_protected(kvm) (is_protected_kvm_enabled() && (kvm)->arch.pkvm.enabled)
1579
1580 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm)
1581
1582 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1583 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1584
1585 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1586
1587 #define kvm_has_mte(kvm) \
1588 (system_supports_mte() && \
1589 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1590
1591 #define kvm_supports_32bit_el0() \
1592 (system_supports_32bit_el0() && \
1593 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1594
1595 #define kvm_vm_has_ran_once(kvm) \
1596 (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags))
1597
__vcpu_has_feature(const struct kvm_arch * ka,int feature)1598 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature)
1599 {
1600 return test_bit(feature, ka->vcpu_features);
1601 }
1602
1603 #define kvm_vcpu_has_feature(k, f) __vcpu_has_feature(&(k)->arch, (f))
1604 #define vcpu_has_feature(v, f) __vcpu_has_feature(&(v)->kvm->arch, (f))
1605
1606 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED)
1607
1608 int kvm_trng_call(struct kvm_vcpu *vcpu);
1609 #ifdef CONFIG_KVM
1610 extern phys_addr_t hyp_mem_base;
1611 extern phys_addr_t hyp_mem_size;
1612 void __init kvm_hyp_reserve(void);
1613 #else
kvm_hyp_reserve(void)1614 static inline void kvm_hyp_reserve(void) { }
1615 #endif
1616
1617 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1618 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1619
__vm_id_reg(struct kvm_arch * ka,u32 reg)1620 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg)
1621 {
1622 switch (reg) {
1623 case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7):
1624 return &ka->id_regs[IDREG_IDX(reg)];
1625 case SYS_CTR_EL0:
1626 return &ka->ctr_el0;
1627 default:
1628 WARN_ON_ONCE(1);
1629 return NULL;
1630 }
1631 }
1632
1633 #define kvm_read_vm_id_reg(kvm, reg) \
1634 ({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; })
1635
1636 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val);
1637
1638 #define __expand_field_sign_unsigned(id, fld, val) \
1639 ((u64)SYS_FIELD_VALUE(id, fld, val))
1640
1641 #define __expand_field_sign_signed(id, fld, val) \
1642 ({ \
1643 u64 __val = SYS_FIELD_VALUE(id, fld, val); \
1644 sign_extend64(__val, id##_##fld##_WIDTH - 1); \
1645 })
1646
1647 #define get_idreg_field_unsigned(kvm, id, fld) \
1648 ({ \
1649 u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id); \
1650 FIELD_GET(id##_##fld##_MASK, __val); \
1651 })
1652
1653 #define get_idreg_field_signed(kvm, id, fld) \
1654 ({ \
1655 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \
1656 sign_extend64(__val, id##_##fld##_WIDTH - 1); \
1657 })
1658
1659 #define get_idreg_field_enum(kvm, id, fld) \
1660 get_idreg_field_unsigned(kvm, id, fld)
1661
1662 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit) \
1663 (get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit))
1664
1665 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit) \
1666 (get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit))
1667
1668 #define kvm_cmp_feat(kvm, id, fld, op, limit) \
1669 (id##_##fld##_SIGNED ? \
1670 kvm_cmp_feat_signed(kvm, id, fld, op, limit) : \
1671 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit))
1672
1673 #define kvm_has_feat(kvm, id, fld, limit) \
1674 kvm_cmp_feat(kvm, id, fld, >=, limit)
1675
1676 #define kvm_has_feat_enum(kvm, id, fld, val) \
1677 kvm_cmp_feat_unsigned(kvm, id, fld, ==, val)
1678
1679 #define kvm_has_feat_range(kvm, id, fld, min, max) \
1680 (kvm_cmp_feat(kvm, id, fld, >=, min) && \
1681 kvm_cmp_feat(kvm, id, fld, <=, max))
1682
1683 /* Check for a given level of PAuth support */
1684 #define kvm_has_pauth(k, l) \
1685 ({ \
1686 bool pa, pi, pa3; \
1687 \
1688 pa = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l); \
1689 pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP); \
1690 pi = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l); \
1691 pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP); \
1692 pa3 = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l); \
1693 pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP); \
1694 \
1695 (pa + pi + pa3) == 1; \
1696 })
1697
1698 #define kvm_has_fpmr(k) \
1699 (system_supports_fpmr() && \
1700 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP))
1701
1702 /* Allocator interface IDs. */
1703 #define HYP_ALLOC_MGT_HEAP_ID 0
1704 #define HYP_ALLOC_MGT_IOMMU_ID 1
1705
1706 unsigned long __pkvm_reclaim_hyp_alloc_mgt(unsigned long nr_pages);
1707 int __pkvm_topup_hyp_alloc_mgt_mc(unsigned long id, struct kvm_hyp_memcache *mc);
1708 int __pkvm_topup_hyp_alloc_mgt_gfp(unsigned long id, unsigned long nr_pages,
1709 unsigned long sz_alloc, gfp_t gfp);
1710
1711 struct kvm_iommu_driver {
1712 int (*init_driver)(void);
1713 void (*remove_driver)(void);
1714 pkvm_handle_t (*get_iommu_id_by_of)(struct device_node *np);
1715 int (*get_device_iommu_num_ids)(struct device *dev);
1716 int (*get_device_iommu_id)(struct device *dev, u32 id,
1717 pkvm_handle_t *out_iommu, u32 *out_sid);
1718 void *(*guest_alloc)(void *flags, unsigned long order);
1719 void (*guest_free)(void *addr, void *flags, unsigned long order);
1720 ANDROID_KABI_RESERVE(1);
1721 ANDROID_KABI_RESERVE(2);
1722 ANDROID_KABI_RESERVE(3);
1723 ANDROID_KABI_RESERVE(4);
1724 ANDROID_KABI_RESERVE(5);
1725 ANDROID_KABI_RESERVE(6);
1726 ANDROID_KABI_RESERVE(7);
1727 ANDROID_KABI_RESERVE(8);
1728 };
1729
1730 struct kvm_iommu_ops;
1731 int kvm_iommu_register_driver(struct kvm_iommu_driver *kern_ops);
1732 int kvm_iommu_init_hyp(struct kvm_iommu_ops *hyp_ops,
1733 struct kvm_hyp_memcache *atomic_mc);
1734 int kvm_iommu_init_driver(void);
1735 void kvm_iommu_remove_driver(void);
1736 pkvm_handle_t kvm_get_iommu_id_by_of(struct device_node *np);
1737
1738 struct page *kvm_iommu_cma_alloc(void);
1739 bool kvm_iommu_cma_release(struct page *p);
1740
1741 int pkvm_iommu_suspend(struct device *dev);
1742 int pkvm_iommu_resume(struct device *dev);
1743
1744 int kvm_iommu_guest_alloc_mc(struct kvm_hyp_memcache *mc, u32 pgsize, u32 nr_pages);
1745 void kvm_iommu_guest_free_mc(struct kvm_hyp_memcache *mc);
1746
1747 struct kvm_iommu_sg {
1748 phys_addr_t phys;
1749 size_t pgsize;
1750 unsigned int pgcount;
1751 };
1752
1753
1754 #define kvm_iommu_sg_nents_size(n) (PAGE_ALIGN((n) * sizeof(struct kvm_iommu_sg)))
1755
kvm_iommu_sg_nents_round(unsigned int nents)1756 static inline unsigned int kvm_iommu_sg_nents_round(unsigned int nents)
1757 {
1758 return kvm_iommu_sg_nents_size(nents) / sizeof(struct kvm_iommu_sg);
1759 }
1760
kvm_iommu_sg_alloc(unsigned int nents,gfp_t gfp)1761 static inline struct kvm_iommu_sg *kvm_iommu_sg_alloc(unsigned int nents, gfp_t gfp)
1762 {
1763 return alloc_pages_exact(kvm_iommu_sg_nents_size(nents), gfp);
1764 }
1765
kvm_iommu_sg_free(struct kvm_iommu_sg * sg,unsigned int nents)1766 static inline void kvm_iommu_sg_free(struct kvm_iommu_sg *sg, unsigned int nents)
1767 {
1768 free_pages_exact(sg, kvm_iommu_sg_nents_size(nents));
1769 }
1770
1771
1772 #ifndef __KVM_NVHE_HYPERVISOR__
1773 int kvm_iommu_attach_dev(pkvm_handle_t iommu_id, pkvm_handle_t domain_id,
1774 unsigned int endpoint, unsigned int pasid,
1775 unsigned int ssid_bits, unsigned long flags);
1776 int kvm_iommu_detach_dev(pkvm_handle_t iommu_id, pkvm_handle_t domain_id,
1777 unsigned int endpoint, unsigned int pasid);
1778 int kvm_iommu_alloc_domain(pkvm_handle_t domain_id, int type);
1779 int kvm_iommu_free_domain(pkvm_handle_t domain_id);
1780 int kvm_iommu_map_pages(pkvm_handle_t domain_id, unsigned long iova,
1781 phys_addr_t paddr, size_t pgsize, size_t pgcount,
1782 int prot, gfp_t gfp, size_t *total_mapped);
1783 size_t kvm_iommu_unmap_pages(pkvm_handle_t domain_id, unsigned long iova,
1784 size_t pgsize, size_t pgcount);
1785 phys_addr_t kvm_iommu_iova_to_phys(pkvm_handle_t domain_id, unsigned long iova);
1786 size_t kvm_iommu_map_sg(pkvm_handle_t domain_id, struct kvm_iommu_sg *sg,
1787 unsigned long iova, unsigned int nent,
1788 unsigned int prot, gfp_t gfp);
1789 #endif
1790
1791 int kvm_iommu_share_hyp_sg(struct kvm_iommu_sg *sg, unsigned int nents);
1792 int kvm_iommu_unshare_hyp_sg(struct kvm_iommu_sg *sg, unsigned int nents);
1793 int kvm_iommu_device_num_ids(struct device *dev);
1794 int kvm_iommu_device_id(struct device *dev, u32 idx,
1795 pkvm_handle_t *out_iommu, u32 *out_sid);
1796 #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE_GROUP
1797
kvm_host_pa(void * addr)1798 static inline phys_addr_t kvm_host_pa(void *addr)
1799 {
1800 return __pa(addr);
1801 }
1802
kvm_host_va(phys_addr_t phys)1803 static inline void *kvm_host_va(phys_addr_t phys)
1804 {
1805 return __va(phys);
1806 }
1807 #endif /* __ARM64_KVM_HOST_H__ */
1808