1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2020-2024 Intel Corporation
4 */
5
6 #ifndef __IVPU_DRV_H__
7 #define __IVPU_DRV_H__
8
9 #include <drm/drm_device.h>
10 #include <drm/drm_drv.h>
11 #include <drm/drm_managed.h>
12 #include <drm/drm_mm.h>
13 #include <drm/drm_print.h>
14
15 #include <linux/pci.h>
16 #include <linux/xarray.h>
17 #include <uapi/drm/ivpu_accel.h>
18
19 #include "ivpu_mmu_context.h"
20 #include "ivpu_ipc.h"
21
22 #define DRIVER_NAME "intel_vpu"
23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
24 #define DRIVER_DATE "20230117"
25
26 #define PCI_DEVICE_ID_MTL 0x7d1d
27 #define PCI_DEVICE_ID_ARL 0xad1d
28 #define PCI_DEVICE_ID_LNL 0x643e
29 #define PCI_DEVICE_ID_PTL_P 0xb03e
30
31 #define IVPU_HW_IP_37XX 37
32 #define IVPU_HW_IP_40XX 40
33 #define IVPU_HW_IP_50XX 50
34 #define IVPU_HW_IP_60XX 60
35
36 #define IVPU_HW_IP_REV_LNL_B0 4
37
38 #define IVPU_HW_BTRS_MTL 1
39 #define IVPU_HW_BTRS_LNL 2
40
41 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
42 /* SSID 1 is used by the VPU to represent reserved context */
43 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1
44 #define IVPU_USER_CONTEXT_MIN_SSID 2
45 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)
46
47 #define IVPU_MIN_DB 1
48 #define IVPU_MAX_DB 255
49
50 #define IVPU_JOB_ID_JOB_MASK GENMASK(7, 0)
51 #define IVPU_JOB_ID_CONTEXT_MASK GENMASK(31, 8)
52
53 #define IVPU_NUM_PRIORITIES 4
54 #define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
55
56 #define IVPU_CMDQ_MIN_ID 1
57 #define IVPU_CMDQ_MAX_ID 255
58
59 #define IVPU_PLATFORM_SILICON 0
60 #define IVPU_PLATFORM_SIMICS 2
61 #define IVPU_PLATFORM_FPGA 3
62 #define IVPU_PLATFORM_INVALID 8
63
64 #define IVPU_SCHED_MODE_AUTO -1
65
66 #define IVPU_DBG_REG BIT(0)
67 #define IVPU_DBG_IRQ BIT(1)
68 #define IVPU_DBG_MMU BIT(2)
69 #define IVPU_DBG_FILE BIT(3)
70 #define IVPU_DBG_MISC BIT(4)
71 #define IVPU_DBG_FW_BOOT BIT(5)
72 #define IVPU_DBG_PM BIT(6)
73 #define IVPU_DBG_IPC BIT(7)
74 #define IVPU_DBG_BO BIT(8)
75 #define IVPU_DBG_JOB BIT(9)
76 #define IVPU_DBG_JSM BIT(10)
77 #define IVPU_DBG_KREF BIT(11)
78 #define IVPU_DBG_RPM BIT(12)
79 #define IVPU_DBG_MMU_MAP BIT(13)
80
81 #define ivpu_err(vdev, fmt, ...) \
82 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
83
84 #define ivpu_err_ratelimited(vdev, fmt, ...) \
85 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
86
87 #define ivpu_warn(vdev, fmt, ...) \
88 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
89
90 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
91 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
92
93 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
94
95 #define ivpu_dbg(vdev, type, fmt, args...) do { \
96 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
97 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
98 } while (0)
99
100 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
101
102 #define IVPU_PRINT_WA(wa_name) do { \
103 if (IVPU_WA(wa_name)) \
104 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
105 } while (0)
106
107 struct ivpu_wa_table {
108 bool punit_disabled;
109 bool clear_runtime_mem;
110 bool interrupt_clear_with_0;
111 bool disable_clock_relinquish;
112 bool disable_d0i3_msg;
113 bool wp0_during_power_up;
114 };
115
116 struct ivpu_hw_info;
117 struct ivpu_mmu_info;
118 struct ivpu_fw_info;
119 struct ivpu_ipc_info;
120 struct ivpu_pm_info;
121
122 struct ivpu_device {
123 struct drm_device drm;
124 void __iomem *regb;
125 void __iomem *regv;
126 u32 platform;
127 u32 irq;
128
129 struct ivpu_wa_table wa;
130 struct ivpu_hw_info *hw;
131 struct ivpu_mmu_info *mmu;
132 struct ivpu_fw_info *fw;
133 struct ivpu_ipc_info *ipc;
134 struct ivpu_pm_info *pm;
135
136 struct ivpu_mmu_context gctx;
137 struct ivpu_mmu_context rctx;
138 struct mutex context_list_lock; /* Protects user context addition/removal */
139 struct xarray context_xa;
140 struct xa_limit context_xa_limit;
141 struct work_struct context_abort_work;
142
143 struct xarray db_xa;
144 struct xa_limit db_limit;
145 u32 db_next;
146
147 struct mutex bo_list_lock; /* Protects bo_list */
148 struct list_head bo_list;
149
150 struct mutex submitted_jobs_lock; /* Protects submitted_jobs */
151 struct xarray submitted_jobs_xa;
152 struct ivpu_ipc_consumer job_done_consumer;
153
154 atomic64_t unique_id_counter;
155
156 ktime_t busy_start_ts;
157 ktime_t busy_time;
158
159 struct {
160 int boot;
161 int jsm;
162 int tdr;
163 int autosuspend;
164 int d0i3_entry_msg;
165 int state_dump_msg;
166 } timeout;
167 };
168
169 /*
170 * file_priv has its own refcount (ref) that allows user space to close the fd
171 * without blocking even if VPU is still processing some jobs.
172 */
173 struct ivpu_file_priv {
174 struct kref ref;
175 struct ivpu_device *vdev;
176 struct mutex lock; /* Protects cmdq */
177 struct xarray cmdq_xa;
178 struct ivpu_mmu_context ctx;
179 struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
180 struct list_head ms_instance_list;
181 struct ivpu_bo *ms_info_bo;
182 struct xa_limit job_limit;
183 u32 job_id_next;
184 struct xa_limit cmdq_limit;
185 u32 cmdq_id_next;
186 bool has_mmu_faults;
187 bool bound;
188 bool aborted;
189 };
190
191 extern int ivpu_dbg_mask;
192 extern u8 ivpu_pll_min_ratio;
193 extern u8 ivpu_pll_max_ratio;
194 extern int ivpu_sched_mode;
195 extern bool ivpu_disable_mmu_cont_pages;
196 extern bool ivpu_force_snoop;
197
198 #define IVPU_TEST_MODE_FW_TEST BIT(0)
199 #define IVPU_TEST_MODE_NULL_HW BIT(1)
200 #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
201 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
202 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
203 #define IVPU_TEST_MODE_PREEMPTION_DISABLE BIT(6)
204 #define IVPU_TEST_MODE_HWS_EXTRA_EVENTS BIT(7)
205 #define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8)
206 extern int ivpu_test_mode;
207
208 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
209 void ivpu_file_priv_put(struct ivpu_file_priv **link);
210
211 int ivpu_boot(struct ivpu_device *vdev);
212 int ivpu_shutdown(struct ivpu_device *vdev);
213 void ivpu_prepare_for_reset(struct ivpu_device *vdev);
214
ivpu_revision(struct ivpu_device * vdev)215 static inline u8 ivpu_revision(struct ivpu_device *vdev)
216 {
217 return to_pci_dev(vdev->drm.dev)->revision;
218 }
219
ivpu_device_id(struct ivpu_device * vdev)220 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
221 {
222 return to_pci_dev(vdev->drm.dev)->device;
223 }
224
ivpu_hw_ip_gen(struct ivpu_device * vdev)225 static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
226 {
227 switch (ivpu_device_id(vdev)) {
228 case PCI_DEVICE_ID_MTL:
229 case PCI_DEVICE_ID_ARL:
230 return IVPU_HW_IP_37XX;
231 case PCI_DEVICE_ID_LNL:
232 return IVPU_HW_IP_40XX;
233 case PCI_DEVICE_ID_PTL_P:
234 return IVPU_HW_IP_50XX;
235 default:
236 dump_stack();
237 ivpu_err(vdev, "Unknown NPU IP generation\n");
238 return 0;
239 }
240 }
241
ivpu_hw_btrs_gen(struct ivpu_device * vdev)242 static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
243 {
244 switch (ivpu_device_id(vdev)) {
245 case PCI_DEVICE_ID_MTL:
246 case PCI_DEVICE_ID_ARL:
247 return IVPU_HW_BTRS_MTL;
248 case PCI_DEVICE_ID_LNL:
249 case PCI_DEVICE_ID_PTL_P:
250 return IVPU_HW_BTRS_LNL;
251 default:
252 dump_stack();
253 ivpu_err(vdev, "Unknown buttress generation\n");
254 return 0;
255 }
256 }
257
to_ivpu_device(struct drm_device * dev)258 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
259 {
260 return container_of(dev, struct ivpu_device, drm);
261 }
262
ivpu_get_context_count(struct ivpu_device * vdev)263 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
264 {
265 struct xa_limit ctx_limit = vdev->context_xa_limit;
266
267 return (ctx_limit.max - ctx_limit.min + 1);
268 }
269
ivpu_get_platform(struct ivpu_device * vdev)270 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
271 {
272 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
273 return vdev->platform;
274 }
275
ivpu_is_silicon(struct ivpu_device * vdev)276 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
277 {
278 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
279 }
280
ivpu_is_simics(struct ivpu_device * vdev)281 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
282 {
283 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
284 }
285
ivpu_is_fpga(struct ivpu_device * vdev)286 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
287 {
288 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA;
289 }
290
ivpu_is_force_snoop_enabled(struct ivpu_device * vdev)291 static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
292 {
293 return ivpu_force_snoop;
294 }
295
296 #endif /* __IVPU_DRV_H__ */
297