1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 *
7 * Author: Rob Clark <robdclark@gmail.com>
8 */
9
10 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
11 #include <linux/debugfs.h>
12 #include <linux/kthread.h>
13 #include <linux/seq_file.h>
14
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_file.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_framebuffer.h>
20
21 #include "msm_drv.h"
22 #include "dpu_kms.h"
23 #include "dpu_hwio.h"
24 #include "dpu_hw_catalog.h"
25 #include "dpu_hw_intf.h"
26 #include "dpu_hw_ctl.h"
27 #include "dpu_hw_dspp.h"
28 #include "dpu_hw_dsc.h"
29 #include "dpu_hw_merge3d.h"
30 #include "dpu_hw_cdm.h"
31 #include "dpu_formats.h"
32 #include "dpu_encoder_phys.h"
33 #include "dpu_crtc.h"
34 #include "dpu_trace.h"
35 #include "dpu_core_irq.h"
36 #include "disp/msm_disp_snapshot.h"
37
38 #define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\
39 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
40
41 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
42 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
43
44 #define DPU_ERROR_ENC_RATELIMITED(e, fmt, ...) DPU_ERROR_RATELIMITED("enc%d " fmt,\
45 (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
46
47 /*
48 * Two to anticipate panels that can do cmd/vid dynamic switching
49 * plan is to create all possible physical encoder types, and switch between
50 * them at runtime
51 */
52 #define NUM_PHYS_ENCODER_TYPES 2
53
54 #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
55 (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
56
57 #define MAX_CHANNELS_PER_ENC 2
58
59 #define IDLE_SHORT_TIMEOUT 1
60
61 #define MAX_HDISPLAY_SPLIT 1080
62
63 /* timeout in frames waiting for frame done */
64 #define DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES 5
65
66 /**
67 * enum dpu_enc_rc_events - events for resource control state machine
68 * @DPU_ENC_RC_EVENT_KICKOFF:
69 * This event happens at NORMAL priority.
70 * Event that signals the start of the transfer. When this event is
71 * received, enable MDP/DSI core clocks. Regardless of the previous
72 * state, the resource should be in ON state at the end of this event.
73 * @DPU_ENC_RC_EVENT_FRAME_DONE:
74 * This event happens at INTERRUPT level.
75 * Event signals the end of the data transfer after the PP FRAME_DONE
76 * event. At the end of this event, a delayed work is scheduled to go to
77 * IDLE_PC state after IDLE_TIMEOUT time.
78 * @DPU_ENC_RC_EVENT_PRE_STOP:
79 * This event happens at NORMAL priority.
80 * This event, when received during the ON state, leave the RC STATE
81 * in the PRE_OFF state. It should be followed by the STOP event as
82 * part of encoder disable.
83 * If received during IDLE or OFF states, it will do nothing.
84 * @DPU_ENC_RC_EVENT_STOP:
85 * This event happens at NORMAL priority.
86 * When this event is received, disable all the MDP/DSI core clocks, and
87 * disable IRQs. It should be called from the PRE_OFF or IDLE states.
88 * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
89 * PRE_OFF is expected when PRE_STOP was executed during the ON state.
90 * Resource state should be in OFF at the end of the event.
91 * @DPU_ENC_RC_EVENT_ENTER_IDLE:
92 * This event happens at NORMAL priority from a work item.
93 * Event signals that there were no frame updates for IDLE_TIMEOUT time.
94 * This would disable MDP/DSI core clocks and change the resource state
95 * to IDLE.
96 */
97 enum dpu_enc_rc_events {
98 DPU_ENC_RC_EVENT_KICKOFF = 1,
99 DPU_ENC_RC_EVENT_FRAME_DONE,
100 DPU_ENC_RC_EVENT_PRE_STOP,
101 DPU_ENC_RC_EVENT_STOP,
102 DPU_ENC_RC_EVENT_ENTER_IDLE
103 };
104
105 /*
106 * enum dpu_enc_rc_states - states that the resource control maintains
107 * @DPU_ENC_RC_STATE_OFF: Resource is in OFF state
108 * @DPU_ENC_RC_STATE_PRE_OFF: Resource is transitioning to OFF state
109 * @DPU_ENC_RC_STATE_ON: Resource is in ON state
110 * @DPU_ENC_RC_STATE_MODESET: Resource is in modeset state
111 * @DPU_ENC_RC_STATE_IDLE: Resource is in IDLE state
112 */
113 enum dpu_enc_rc_states {
114 DPU_ENC_RC_STATE_OFF,
115 DPU_ENC_RC_STATE_PRE_OFF,
116 DPU_ENC_RC_STATE_ON,
117 DPU_ENC_RC_STATE_IDLE
118 };
119
120 /**
121 * struct dpu_encoder_virt - virtual encoder. Container of one or more physical
122 * encoders. Virtual encoder manages one "logical" display. Physical
123 * encoders manage one intf block, tied to a specific panel/sub-panel.
124 * Virtual encoder defers as much as possible to the physical encoders.
125 * Virtual encoder registers itself with the DRM Framework as the encoder.
126 * @base: drm_encoder base class for registration with DRM
127 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
128 * @enabled: True if the encoder is active, protected by enc_lock
129 * @commit_done_timedout: True if there has been a timeout on commit after
130 * enabling the encoder.
131 * @num_phys_encs: Actual number of physical encoders contained.
132 * @phys_encs: Container of physical encoders managed.
133 * @cur_master: Pointer to the current master in this mode. Optimization
134 * Only valid after enable. Cleared as disable.
135 * @cur_slave: As above but for the slave encoder.
136 * @hw_pp: Handle to the pingpong blocks used for the display. No.
137 * pingpong blocks can be different than num_phys_encs.
138 * @hw_dsc: Handle to the DSC blocks used for the display.
139 * @dsc_mask: Bitmask of used DSC blocks.
140 * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
141 * for partial update right-only cases, such as pingpong
142 * split where virtual pingpong does not generate IRQs
143 * @crtc: Pointer to the currently assigned crtc. Normally you
144 * would use crtc->state->encoder_mask to determine the
145 * link between encoder/crtc. However in this case we need
146 * to track crtc in the disable() hook which is called
147 * _after_ encoder_mask is cleared.
148 * @connector: If a mode is set, cached pointer to the active connector
149 * @enc_lock: Lock around physical encoder
150 * create/destroy/enable/disable
151 * @frame_busy_mask: Bitmask tracking which phys_enc we are still
152 * busy processing current command.
153 * Bit0 = phys_encs[0] etc.
154 * @frame_done_timeout_ms: frame done timeout in ms
155 * @frame_done_timeout_cnt: atomic counter tracking the number of frame
156 * done timeouts
157 * @frame_done_timer: watchdog timer for frame done event
158 * @disp_info: local copy of msm_display_info struct
159 * @idle_pc_supported: indicate if idle power collaps is supported
160 * @rc_lock: resource control mutex lock to protect
161 * virt encoder over various state changes
162 * @rc_state: resource controller state
163 * @delayed_off_work: delayed worker to schedule disabling of
164 * clks and resources after IDLE_TIMEOUT time.
165 * @topology: topology of the display
166 * @idle_timeout: idle timeout duration in milliseconds
167 * @wide_bus_en: wide bus is enabled on this interface
168 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
169 */
170 struct dpu_encoder_virt {
171 struct drm_encoder base;
172 spinlock_t enc_spinlock;
173
174 bool enabled;
175 bool commit_done_timedout;
176
177 unsigned int num_phys_encs;
178 struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
179 struct dpu_encoder_phys *cur_master;
180 struct dpu_encoder_phys *cur_slave;
181 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
182 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
183
184 unsigned int dsc_mask;
185
186 bool intfs_swapped;
187
188 struct drm_crtc *crtc;
189 struct drm_connector *connector;
190
191 struct mutex enc_lock;
192 DECLARE_BITMAP(frame_busy_mask, MAX_PHYS_ENCODERS_PER_VIRTUAL);
193
194 atomic_t frame_done_timeout_ms;
195 atomic_t frame_done_timeout_cnt;
196 struct timer_list frame_done_timer;
197
198 struct msm_display_info disp_info;
199
200 bool idle_pc_supported;
201 struct mutex rc_lock;
202 enum dpu_enc_rc_states rc_state;
203 struct delayed_work delayed_off_work;
204 struct msm_display_topology topology;
205
206 u32 idle_timeout;
207
208 bool wide_bus_en;
209
210 /* DSC configuration */
211 struct drm_dsc_config *dsc;
212 };
213
214 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
215
216 static u32 dither_matrix[DITHER_MATRIX_SZ] = {
217 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
218 };
219
dpu_encoder_get_drm_fmt(struct dpu_encoder_phys * phys_enc)220 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc)
221 {
222 struct drm_encoder *drm_enc;
223 struct dpu_encoder_virt *dpu_enc;
224 struct drm_display_info *info;
225 struct drm_display_mode *mode;
226
227 drm_enc = phys_enc->parent;
228 dpu_enc = to_dpu_encoder_virt(drm_enc);
229 info = &dpu_enc->connector->display_info;
230 mode = &phys_enc->cached_mode;
231
232 if (drm_mode_is_420_only(info, mode))
233 return DRM_FORMAT_YUV420;
234
235 return DRM_FORMAT_RGB888;
236 }
237
dpu_encoder_needs_periph_flush(struct dpu_encoder_phys * phys_enc)238 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc)
239 {
240 struct drm_encoder *drm_enc;
241 struct dpu_encoder_virt *dpu_enc;
242 struct msm_display_info *disp_info;
243 struct msm_drm_private *priv;
244 struct drm_display_mode *mode;
245
246 drm_enc = phys_enc->parent;
247 dpu_enc = to_dpu_encoder_virt(drm_enc);
248 disp_info = &dpu_enc->disp_info;
249 priv = drm_enc->dev->dev_private;
250 mode = &phys_enc->cached_mode;
251
252 return phys_enc->hw_intf->cap->type == INTF_DP &&
253 msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]], mode);
254 }
255
dpu_encoder_is_widebus_enabled(const struct drm_encoder * drm_enc)256 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
257 {
258 const struct dpu_encoder_virt *dpu_enc;
259 struct msm_drm_private *priv = drm_enc->dev->dev_private;
260 const struct msm_display_info *disp_info;
261 int index;
262
263 dpu_enc = to_dpu_encoder_virt(drm_enc);
264 disp_info = &dpu_enc->disp_info;
265 index = disp_info->h_tile_instance[0];
266
267 if (disp_info->intf_type == INTF_DP)
268 return msm_dp_wide_bus_available(priv->dp[index]);
269 else if (disp_info->intf_type == INTF_DSI)
270 return msm_dsi_wide_bus_enabled(priv->dsi[index]);
271
272 return false;
273 }
274
dpu_encoder_is_dsc_enabled(const struct drm_encoder * drm_enc)275 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc)
276 {
277 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
278
279 return dpu_enc->dsc ? true : false;
280 }
281
dpu_encoder_get_crc_values_cnt(const struct drm_encoder * drm_enc)282 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
283 {
284 struct dpu_encoder_virt *dpu_enc;
285 int i, num_intf = 0;
286
287 dpu_enc = to_dpu_encoder_virt(drm_enc);
288
289 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
290 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
291
292 if (phys->hw_intf && phys->hw_intf->ops.setup_misr
293 && phys->hw_intf->ops.collect_misr)
294 num_intf++;
295 }
296
297 return num_intf;
298 }
299
dpu_encoder_setup_misr(const struct drm_encoder * drm_enc)300 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc)
301 {
302 struct dpu_encoder_virt *dpu_enc;
303
304 int i;
305
306 dpu_enc = to_dpu_encoder_virt(drm_enc);
307
308 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
309 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
310
311 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr)
312 continue;
313
314 phys->hw_intf->ops.setup_misr(phys->hw_intf);
315 }
316 }
317
dpu_encoder_get_crc(const struct drm_encoder * drm_enc,u32 * crcs,int pos)318 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos)
319 {
320 struct dpu_encoder_virt *dpu_enc;
321
322 int i, rc = 0, entries_added = 0;
323
324 if (!drm_enc->crtc) {
325 DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index);
326 return -EINVAL;
327 }
328
329 dpu_enc = to_dpu_encoder_virt(drm_enc);
330
331 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
332 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
333
334 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr)
335 continue;
336
337 rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]);
338 if (rc)
339 return rc;
340 entries_added++;
341 }
342
343 return entries_added;
344 }
345
_dpu_encoder_setup_dither(struct dpu_hw_pingpong * hw_pp,unsigned bpc)346 static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
347 {
348 struct dpu_hw_dither_cfg dither_cfg = { 0 };
349
350 if (!hw_pp->ops.setup_dither)
351 return;
352
353 switch (bpc) {
354 case 6:
355 dither_cfg.c0_bitdepth = 6;
356 dither_cfg.c1_bitdepth = 6;
357 dither_cfg.c2_bitdepth = 6;
358 dither_cfg.c3_bitdepth = 6;
359 dither_cfg.temporal_en = 0;
360 break;
361 default:
362 hw_pp->ops.setup_dither(hw_pp, NULL);
363 return;
364 }
365
366 memcpy(&dither_cfg.matrix, dither_matrix,
367 sizeof(u32) * DITHER_MATRIX_SZ);
368
369 hw_pp->ops.setup_dither(hw_pp, &dither_cfg);
370 }
371
dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)372 static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)
373 {
374 switch (intf_mode) {
375 case INTF_MODE_VIDEO:
376 return "INTF_MODE_VIDEO";
377 case INTF_MODE_CMD:
378 return "INTF_MODE_CMD";
379 case INTF_MODE_WB_BLOCK:
380 return "INTF_MODE_WB_BLOCK";
381 case INTF_MODE_WB_LINE:
382 return "INTF_MODE_WB_LINE";
383 default:
384 return "INTF_MODE_UNKNOWN";
385 }
386 }
387
dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys * phys_enc,enum dpu_intr_idx intr_idx)388 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
389 enum dpu_intr_idx intr_idx)
390 {
391 DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, intr=%d\n",
392 DRMID(phys_enc->parent),
393 dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),
394 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1,
395 phys_enc->hw_wb ? phys_enc->hw_wb->idx - WB_0 : -1,
396 phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
397
398 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc,
399 DPU_ENCODER_FRAME_EVENT_ERROR);
400 }
401
402 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id,
403 u32 irq_idx, struct dpu_encoder_wait_info *info);
404
dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys * phys_enc,unsigned int irq_idx,void (* func)(void * arg),struct dpu_encoder_wait_info * wait_info)405 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
406 unsigned int irq_idx,
407 void (*func)(void *arg),
408 struct dpu_encoder_wait_info *wait_info)
409 {
410 u32 irq_status;
411 int ret;
412
413 if (!wait_info) {
414 DPU_ERROR("invalid params\n");
415 return -EINVAL;
416 }
417 /* note: do master / slave checking outside */
418
419 /* return EWOULDBLOCK since we know the wait isn't necessary */
420 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
421 DRM_ERROR("encoder is disabled id=%u, callback=%ps, IRQ=[%d, %d]\n",
422 DRMID(phys_enc->parent), func,
423 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx));
424 return -EWOULDBLOCK;
425 }
426
427 if (irq_idx == 0) {
428 DRM_DEBUG_KMS("skip irq wait id=%u, callback=%ps\n",
429 DRMID(phys_enc->parent), func);
430 return 0;
431 }
432
433 DRM_DEBUG_KMS("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, pending_cnt=%d\n",
434 DRMID(phys_enc->parent), func,
435 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx), phys_enc->hw_pp->idx - PINGPONG_0,
436 atomic_read(wait_info->atomic_cnt));
437
438 ret = dpu_encoder_helper_wait_event_timeout(
439 DRMID(phys_enc->parent),
440 irq_idx,
441 wait_info);
442
443 if (ret <= 0) {
444 irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx);
445 if (irq_status) {
446 unsigned long flags;
447
448 DRM_DEBUG_KMS("IRQ=[%d, %d] not triggered id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
449 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
450 DRMID(phys_enc->parent), func,
451 phys_enc->hw_pp->idx - PINGPONG_0,
452 atomic_read(wait_info->atomic_cnt));
453 local_irq_save(flags);
454 func(phys_enc);
455 local_irq_restore(flags);
456 ret = 0;
457 } else {
458 ret = -ETIMEDOUT;
459 DRM_DEBUG_KMS("IRQ=[%d, %d] timeout id=%u, callback=%ps, pp=%d, atomic_cnt=%d\n",
460 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
461 DRMID(phys_enc->parent), func,
462 phys_enc->hw_pp->idx - PINGPONG_0,
463 atomic_read(wait_info->atomic_cnt));
464 }
465 } else {
466 ret = 0;
467 trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
468 func, DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
469 phys_enc->hw_pp->idx - PINGPONG_0,
470 atomic_read(wait_info->atomic_cnt));
471 }
472
473 return ret;
474 }
475
dpu_encoder_get_vsync_count(struct drm_encoder * drm_enc)476 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc)
477 {
478 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
479 struct dpu_encoder_phys *phys = dpu_enc ? dpu_enc->cur_master : NULL;
480 return phys ? atomic_read(&phys->vsync_cnt) : 0;
481 }
482
dpu_encoder_get_linecount(struct drm_encoder * drm_enc)483 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc)
484 {
485 struct dpu_encoder_virt *dpu_enc;
486 struct dpu_encoder_phys *phys;
487 int linecount = 0;
488
489 dpu_enc = to_dpu_encoder_virt(drm_enc);
490 phys = dpu_enc ? dpu_enc->cur_master : NULL;
491
492 if (phys && phys->ops.get_line_count)
493 linecount = phys->ops.get_line_count(phys);
494
495 return linecount;
496 }
497
dpu_encoder_helper_split_config(struct dpu_encoder_phys * phys_enc,enum dpu_intf interface)498 void dpu_encoder_helper_split_config(
499 struct dpu_encoder_phys *phys_enc,
500 enum dpu_intf interface)
501 {
502 struct dpu_encoder_virt *dpu_enc;
503 struct split_pipe_cfg cfg = { 0 };
504 struct dpu_hw_mdp *hw_mdptop;
505 struct msm_display_info *disp_info;
506
507 if (!phys_enc->hw_mdptop || !phys_enc->parent) {
508 DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
509 return;
510 }
511
512 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
513 hw_mdptop = phys_enc->hw_mdptop;
514 disp_info = &dpu_enc->disp_info;
515
516 if (disp_info->intf_type != INTF_DSI)
517 return;
518
519 /**
520 * disable split modes since encoder will be operating in as the only
521 * encoder, either for the entire use case in the case of, for example,
522 * single DSI, or for this frame in the case of left/right only partial
523 * update.
524 */
525 if (phys_enc->split_role == ENC_ROLE_SOLO) {
526 if (hw_mdptop->ops.setup_split_pipe)
527 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
528 return;
529 }
530
531 cfg.en = true;
532 cfg.mode = phys_enc->intf_mode;
533 cfg.intf = interface;
534
535 if (cfg.en && phys_enc->ops.needs_single_flush &&
536 phys_enc->ops.needs_single_flush(phys_enc))
537 cfg.split_flush_en = true;
538
539 if (phys_enc->split_role == ENC_ROLE_MASTER) {
540 DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
541
542 if (hw_mdptop->ops.setup_split_pipe)
543 hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
544 }
545 }
546
dpu_encoder_use_dsc_merge(struct drm_encoder * drm_enc)547 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
548 {
549 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
550 int i, intf_count = 0, num_dsc = 0;
551
552 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
553 if (dpu_enc->phys_encs[i])
554 intf_count++;
555
556 /* See dpu_encoder_get_topology, we only support 2:2:1 topology */
557 if (dpu_enc->dsc)
558 num_dsc = 2;
559
560 return (num_dsc > 0) && (num_dsc > intf_count);
561 }
562
dpu_encoder_get_dsc_config(struct drm_encoder * drm_enc)563 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc)
564 {
565 struct msm_drm_private *priv = drm_enc->dev->dev_private;
566 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
567 int index = dpu_enc->disp_info.h_tile_instance[0];
568
569 if (dpu_enc->disp_info.intf_type == INTF_DSI)
570 return msm_dsi_get_dsc_config(priv->dsi[index]);
571
572 return NULL;
573 }
574
dpu_encoder_get_topology(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct drm_display_mode * mode,struct drm_crtc_state * crtc_state,struct drm_dsc_config * dsc)575 static struct msm_display_topology dpu_encoder_get_topology(
576 struct dpu_encoder_virt *dpu_enc,
577 struct dpu_kms *dpu_kms,
578 struct drm_display_mode *mode,
579 struct drm_crtc_state *crtc_state,
580 struct drm_dsc_config *dsc)
581 {
582 struct msm_display_topology topology = {0};
583 int i, intf_count = 0;
584
585 for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
586 if (dpu_enc->phys_encs[i])
587 intf_count++;
588
589 /* Datapath topology selection
590 *
591 * Dual display
592 * 2 LM, 2 INTF ( Split display using 2 interfaces)
593 *
594 * Single display
595 * 1 LM, 1 INTF
596 * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
597 *
598 * Add dspps to the reservation requirements if ctm is requested
599 */
600 if (intf_count == 2)
601 topology.num_lm = 2;
602 else if (!dpu_kms->catalog->caps->has_3d_merge)
603 topology.num_lm = 1;
604 else
605 topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
606
607 if (crtc_state->ctm)
608 topology.num_dspp = topology.num_lm;
609
610 topology.num_intf = intf_count;
611
612 if (dsc) {
613 /*
614 * In case of Display Stream Compression (DSC), we would use
615 * 2 DSC encoders, 2 layer mixers and 1 interface
616 * this is power optimal and can drive up to (including) 4k
617 * screens
618 */
619 topology.num_dsc = 2;
620 topology.num_lm = 2;
621 topology.num_intf = 1;
622 }
623
624 return topology;
625 }
626
dpu_encoder_assign_crtc_resources(struct dpu_kms * dpu_kms,struct drm_encoder * drm_enc,struct dpu_global_state * global_state,struct drm_crtc_state * crtc_state)627 static void dpu_encoder_assign_crtc_resources(struct dpu_kms *dpu_kms,
628 struct drm_encoder *drm_enc,
629 struct dpu_global_state *global_state,
630 struct drm_crtc_state *crtc_state)
631 {
632 struct dpu_crtc_state *cstate;
633 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
634 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
635 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC];
636 int num_lm, num_ctl, num_dspp, i;
637
638 cstate = to_dpu_crtc_state(crtc_state);
639
640 memset(cstate->mixers, 0, sizeof(cstate->mixers));
641
642 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
643 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
644 num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
645 drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
646 num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
647 drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
648 ARRAY_SIZE(hw_dspp));
649
650 for (i = 0; i < num_lm; i++) {
651 int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
652
653 cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
654 cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
655 cstate->mixers[i].hw_dspp = i < num_dspp ? to_dpu_hw_dspp(hw_dspp[i]) : NULL;
656 }
657
658 cstate->num_mixers = num_lm;
659 }
660
dpu_encoder_virt_atomic_check(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)661 static int dpu_encoder_virt_atomic_check(
662 struct drm_encoder *drm_enc,
663 struct drm_crtc_state *crtc_state,
664 struct drm_connector_state *conn_state)
665 {
666 struct dpu_encoder_virt *dpu_enc;
667 struct msm_drm_private *priv;
668 struct dpu_kms *dpu_kms;
669 struct drm_display_mode *adj_mode;
670 struct msm_display_topology topology;
671 struct msm_display_info *disp_info;
672 struct dpu_global_state *global_state;
673 struct drm_framebuffer *fb;
674 struct drm_dsc_config *dsc;
675 int ret = 0;
676
677 if (!drm_enc || !crtc_state || !conn_state) {
678 DPU_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
679 drm_enc != NULL, crtc_state != NULL, conn_state != NULL);
680 return -EINVAL;
681 }
682
683 dpu_enc = to_dpu_encoder_virt(drm_enc);
684 DPU_DEBUG_ENC(dpu_enc, "\n");
685
686 priv = drm_enc->dev->dev_private;
687 disp_info = &dpu_enc->disp_info;
688 dpu_kms = to_dpu_kms(priv->kms);
689 adj_mode = &crtc_state->adjusted_mode;
690 global_state = dpu_kms_get_global_state(crtc_state->state);
691 if (IS_ERR(global_state))
692 return PTR_ERR(global_state);
693
694 trace_dpu_enc_atomic_check(DRMID(drm_enc));
695
696 dsc = dpu_encoder_get_dsc_config(drm_enc);
697
698 topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc);
699
700 /*
701 * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it.
702 * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check()
703 * earlier.
704 */
705 if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) {
706 fb = conn_state->writeback_job->fb;
707
708 if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb)))
709 topology.needs_cdm = true;
710 } else if (disp_info->intf_type == INTF_DP) {
711 if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode))
712 topology.needs_cdm = true;
713 }
714
715 if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm)
716 crtc_state->mode_changed = true;
717 else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm)
718 crtc_state->mode_changed = true;
719 /*
720 * Release and Allocate resources on every modeset
721 */
722 if (drm_atomic_crtc_needs_modeset(crtc_state)) {
723 dpu_rm_release(global_state, drm_enc);
724
725 if (crtc_state->enable)
726 ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
727 drm_enc, crtc_state, topology);
728 if (!ret)
729 dpu_encoder_assign_crtc_resources(dpu_kms, drm_enc,
730 global_state, crtc_state);
731 }
732
733 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
734
735 return ret;
736 }
737
_dpu_encoder_update_vsync_source(struct dpu_encoder_virt * dpu_enc,struct msm_display_info * disp_info)738 static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
739 struct msm_display_info *disp_info)
740 {
741 struct dpu_vsync_source_cfg vsync_cfg = { 0 };
742 struct msm_drm_private *priv;
743 struct dpu_kms *dpu_kms;
744 struct dpu_hw_mdp *hw_mdptop;
745 struct drm_encoder *drm_enc;
746 struct dpu_encoder_phys *phys_enc;
747 int i;
748
749 if (!dpu_enc || !disp_info) {
750 DPU_ERROR("invalid param dpu_enc:%d or disp_info:%d\n",
751 dpu_enc != NULL, disp_info != NULL);
752 return;
753 } else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
754 DPU_ERROR("invalid num phys enc %d/%d\n",
755 dpu_enc->num_phys_encs,
756 (int) ARRAY_SIZE(dpu_enc->hw_pp));
757 return;
758 }
759
760 drm_enc = &dpu_enc->base;
761 /* this pointers are checked in virt_enable_helper */
762 priv = drm_enc->dev->dev_private;
763
764 dpu_kms = to_dpu_kms(priv->kms);
765 hw_mdptop = dpu_kms->hw_mdp;
766 if (!hw_mdptop) {
767 DPU_ERROR("invalid mdptop\n");
768 return;
769 }
770
771 if (hw_mdptop->ops.setup_vsync_source) {
772 for (i = 0; i < dpu_enc->num_phys_encs; i++)
773 vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
774
775 vsync_cfg.pp_count = dpu_enc->num_phys_encs;
776 vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode);
777
778 vsync_cfg.vsync_source = disp_info->vsync_source;
779
780 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
781
782 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
783 phys_enc = dpu_enc->phys_encs[i];
784
785 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel)
786 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf,
787 vsync_cfg.vsync_source);
788 }
789 }
790 }
791
_dpu_encoder_irq_enable(struct drm_encoder * drm_enc)792 static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc)
793 {
794 struct dpu_encoder_virt *dpu_enc;
795 int i;
796
797 if (!drm_enc) {
798 DPU_ERROR("invalid encoder\n");
799 return;
800 }
801
802 dpu_enc = to_dpu_encoder_virt(drm_enc);
803
804 DPU_DEBUG_ENC(dpu_enc, "\n");
805 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
806 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
807
808 phys->ops.irq_enable(phys);
809 }
810 }
811
_dpu_encoder_irq_disable(struct drm_encoder * drm_enc)812 static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc)
813 {
814 struct dpu_encoder_virt *dpu_enc;
815 int i;
816
817 if (!drm_enc) {
818 DPU_ERROR("invalid encoder\n");
819 return;
820 }
821
822 dpu_enc = to_dpu_encoder_virt(drm_enc);
823
824 DPU_DEBUG_ENC(dpu_enc, "\n");
825 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
826 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
827
828 phys->ops.irq_disable(phys);
829 }
830 }
831
_dpu_encoder_resource_enable(struct drm_encoder * drm_enc)832 static void _dpu_encoder_resource_enable(struct drm_encoder *drm_enc)
833 {
834 struct msm_drm_private *priv;
835 struct dpu_kms *dpu_kms;
836 struct dpu_encoder_virt *dpu_enc;
837
838 dpu_enc = to_dpu_encoder_virt(drm_enc);
839 priv = drm_enc->dev->dev_private;
840 dpu_kms = to_dpu_kms(priv->kms);
841
842 trace_dpu_enc_rc_enable(DRMID(drm_enc));
843
844 if (!dpu_enc->cur_master) {
845 DPU_ERROR("encoder master not set\n");
846 return;
847 }
848
849 /* enable DPU core clks */
850 pm_runtime_get_sync(&dpu_kms->pdev->dev);
851
852 /* enable all the irq */
853 _dpu_encoder_irq_enable(drm_enc);
854 }
855
_dpu_encoder_resource_disable(struct drm_encoder * drm_enc)856 static void _dpu_encoder_resource_disable(struct drm_encoder *drm_enc)
857 {
858 struct msm_drm_private *priv;
859 struct dpu_kms *dpu_kms;
860 struct dpu_encoder_virt *dpu_enc;
861
862 dpu_enc = to_dpu_encoder_virt(drm_enc);
863 priv = drm_enc->dev->dev_private;
864 dpu_kms = to_dpu_kms(priv->kms);
865
866 trace_dpu_enc_rc_disable(DRMID(drm_enc));
867
868 if (!dpu_enc->cur_master) {
869 DPU_ERROR("encoder master not set\n");
870 return;
871 }
872
873 /* disable all the irq */
874 _dpu_encoder_irq_disable(drm_enc);
875
876 /* disable DPU core clks */
877 pm_runtime_put_sync(&dpu_kms->pdev->dev);
878 }
879
dpu_encoder_resource_control(struct drm_encoder * drm_enc,u32 sw_event)880 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
881 u32 sw_event)
882 {
883 struct dpu_encoder_virt *dpu_enc;
884 struct msm_drm_private *priv;
885 bool is_vid_mode = false;
886
887 if (!drm_enc || !drm_enc->dev || !drm_enc->crtc) {
888 DPU_ERROR("invalid parameters\n");
889 return -EINVAL;
890 }
891 dpu_enc = to_dpu_encoder_virt(drm_enc);
892 priv = drm_enc->dev->dev_private;
893 is_vid_mode = !dpu_enc->disp_info.is_cmd_mode;
894
895 /*
896 * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
897 * events and return early for other events (ie wb display).
898 */
899 if (!dpu_enc->idle_pc_supported &&
900 (sw_event != DPU_ENC_RC_EVENT_KICKOFF &&
901 sw_event != DPU_ENC_RC_EVENT_STOP &&
902 sw_event != DPU_ENC_RC_EVENT_PRE_STOP))
903 return 0;
904
905 trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
906 dpu_enc->rc_state, "begin");
907
908 switch (sw_event) {
909 case DPU_ENC_RC_EVENT_KICKOFF:
910 /* cancel delayed off work, if any */
911 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
912 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
913 sw_event);
914
915 mutex_lock(&dpu_enc->rc_lock);
916
917 /* return if the resource control is already in ON state */
918 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
919 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n",
920 DRMID(drm_enc), sw_event);
921 mutex_unlock(&dpu_enc->rc_lock);
922 return 0;
923 } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF &&
924 dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) {
925 DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n",
926 DRMID(drm_enc), sw_event,
927 dpu_enc->rc_state);
928 mutex_unlock(&dpu_enc->rc_lock);
929 return -EINVAL;
930 }
931
932 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE)
933 _dpu_encoder_irq_enable(drm_enc);
934 else
935 _dpu_encoder_resource_enable(drm_enc);
936
937 dpu_enc->rc_state = DPU_ENC_RC_STATE_ON;
938
939 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
940 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
941 "kickoff");
942
943 mutex_unlock(&dpu_enc->rc_lock);
944 break;
945
946 case DPU_ENC_RC_EVENT_FRAME_DONE:
947 /*
948 * mutex lock is not used as this event happens at interrupt
949 * context. And locking is not required as, the other events
950 * like KICKOFF and STOP does a wait-for-idle before executing
951 * the resource_control
952 */
953 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
954 DRM_DEBUG_KMS("id:%d, sw_event:%d,rc:%d-unexpected\n",
955 DRMID(drm_enc), sw_event,
956 dpu_enc->rc_state);
957 return -EINVAL;
958 }
959
960 /*
961 * schedule off work item only when there are no
962 * frames pending
963 */
964 if (dpu_crtc_frame_pending(drm_enc->crtc) > 1) {
965 DRM_DEBUG_KMS("id:%d skip schedule work\n",
966 DRMID(drm_enc));
967 return 0;
968 }
969
970 queue_delayed_work(priv->wq, &dpu_enc->delayed_off_work,
971 msecs_to_jiffies(dpu_enc->idle_timeout));
972
973 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
974 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
975 "frame done");
976 break;
977
978 case DPU_ENC_RC_EVENT_PRE_STOP:
979 /* cancel delayed off work, if any */
980 if (cancel_delayed_work_sync(&dpu_enc->delayed_off_work))
981 DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work cancelled\n",
982 sw_event);
983
984 mutex_lock(&dpu_enc->rc_lock);
985
986 if (is_vid_mode &&
987 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
988 _dpu_encoder_irq_enable(drm_enc);
989 }
990 /* skip if is already OFF or IDLE, resources are off already */
991 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF ||
992 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) {
993 DRM_DEBUG_KMS("id:%u, sw_event:%d, rc in %d state\n",
994 DRMID(drm_enc), sw_event,
995 dpu_enc->rc_state);
996 mutex_unlock(&dpu_enc->rc_lock);
997 return 0;
998 }
999
1000 dpu_enc->rc_state = DPU_ENC_RC_STATE_PRE_OFF;
1001
1002 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1003 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1004 "pre stop");
1005
1006 mutex_unlock(&dpu_enc->rc_lock);
1007 break;
1008
1009 case DPU_ENC_RC_EVENT_STOP:
1010 mutex_lock(&dpu_enc->rc_lock);
1011
1012 /* return if the resource control is already in OFF state */
1013 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF) {
1014 DRM_DEBUG_KMS("id: %u, sw_event:%d, rc in OFF state\n",
1015 DRMID(drm_enc), sw_event);
1016 mutex_unlock(&dpu_enc->rc_lock);
1017 return 0;
1018 } else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) {
1019 DRM_ERROR("id: %u, sw_event:%d, rc in state %d\n",
1020 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1021 mutex_unlock(&dpu_enc->rc_lock);
1022 return -EINVAL;
1023 }
1024
1025 /**
1026 * expect to arrive here only if in either idle state or pre-off
1027 * and in IDLE state the resources are already disabled
1028 */
1029 if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF)
1030 _dpu_encoder_resource_disable(drm_enc);
1031
1032 dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF;
1033
1034 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1035 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1036 "stop");
1037
1038 mutex_unlock(&dpu_enc->rc_lock);
1039 break;
1040
1041 case DPU_ENC_RC_EVENT_ENTER_IDLE:
1042 mutex_lock(&dpu_enc->rc_lock);
1043
1044 if (dpu_enc->rc_state != DPU_ENC_RC_STATE_ON) {
1045 DRM_ERROR("id: %u, sw_event:%d, rc:%d !ON state\n",
1046 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1047 mutex_unlock(&dpu_enc->rc_lock);
1048 return 0;
1049 }
1050
1051 /*
1052 * if we are in ON but a frame was just kicked off,
1053 * ignore the IDLE event, it's probably a stale timer event
1054 */
1055 if (dpu_enc->frame_busy_mask[0]) {
1056 DRM_ERROR("id:%u, sw_event:%d, rc:%d frame pending\n",
1057 DRMID(drm_enc), sw_event, dpu_enc->rc_state);
1058 mutex_unlock(&dpu_enc->rc_lock);
1059 return 0;
1060 }
1061
1062 if (is_vid_mode)
1063 _dpu_encoder_irq_disable(drm_enc);
1064 else
1065 _dpu_encoder_resource_disable(drm_enc);
1066
1067 dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE;
1068
1069 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1070 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1071 "idle");
1072
1073 mutex_unlock(&dpu_enc->rc_lock);
1074 break;
1075
1076 default:
1077 DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
1078 sw_event);
1079 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1080 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1081 "error");
1082 break;
1083 }
1084
1085 trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
1086 dpu_enc->idle_pc_supported, dpu_enc->rc_state,
1087 "end");
1088 return 0;
1089 }
1090
dpu_encoder_prepare_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1091 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
1092 struct drm_writeback_job *job)
1093 {
1094 struct dpu_encoder_virt *dpu_enc;
1095 int i;
1096
1097 dpu_enc = to_dpu_encoder_virt(drm_enc);
1098
1099 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1100 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1101
1102 if (phys->ops.prepare_wb_job)
1103 phys->ops.prepare_wb_job(phys, job);
1104
1105 }
1106 }
1107
dpu_encoder_cleanup_wb_job(struct drm_encoder * drm_enc,struct drm_writeback_job * job)1108 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
1109 struct drm_writeback_job *job)
1110 {
1111 struct dpu_encoder_virt *dpu_enc;
1112 int i;
1113
1114 dpu_enc = to_dpu_encoder_virt(drm_enc);
1115
1116 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1117 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1118
1119 if (phys->ops.cleanup_wb_job)
1120 phys->ops.cleanup_wb_job(phys, job);
1121
1122 }
1123 }
1124
dpu_encoder_virt_atomic_mode_set(struct drm_encoder * drm_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1125 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
1126 struct drm_crtc_state *crtc_state,
1127 struct drm_connector_state *conn_state)
1128 {
1129 struct dpu_encoder_virt *dpu_enc;
1130 struct msm_drm_private *priv;
1131 struct dpu_kms *dpu_kms;
1132 struct dpu_global_state *global_state;
1133 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
1134 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
1135 struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
1136 int num_ctl, num_pp, num_dsc;
1137 unsigned int dsc_mask = 0;
1138 int i;
1139
1140 if (!drm_enc) {
1141 DPU_ERROR("invalid encoder\n");
1142 return;
1143 }
1144
1145 dpu_enc = to_dpu_encoder_virt(drm_enc);
1146 DPU_DEBUG_ENC(dpu_enc, "\n");
1147
1148 priv = drm_enc->dev->dev_private;
1149 dpu_kms = to_dpu_kms(priv->kms);
1150
1151 global_state = dpu_kms_get_existing_global_state(dpu_kms);
1152 if (IS_ERR_OR_NULL(global_state)) {
1153 DPU_ERROR("Failed to get global state");
1154 return;
1155 }
1156
1157 trace_dpu_enc_mode_set(DRMID(drm_enc));
1158
1159 /* Query resource that have been reserved in atomic check step. */
1160 num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1161 drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp,
1162 ARRAY_SIZE(hw_pp));
1163 num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1164 drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
1165
1166 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1167 dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
1168 : NULL;
1169
1170 num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1171 drm_enc->base.id, DPU_HW_BLK_DSC,
1172 hw_dsc, ARRAY_SIZE(hw_dsc));
1173 for (i = 0; i < num_dsc; i++) {
1174 dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]);
1175 dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
1176 }
1177
1178 dpu_enc->dsc_mask = dsc_mask;
1179
1180 if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) ||
1181 dpu_enc->disp_info.intf_type == INTF_DP) {
1182 struct dpu_hw_blk *hw_cdm = NULL;
1183
1184 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
1185 drm_enc->base.id, DPU_HW_BLK_CDM,
1186 &hw_cdm, 1);
1187 dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL;
1188 }
1189
1190 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1191 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1192
1193 phys->hw_pp = dpu_enc->hw_pp[i];
1194 if (!phys->hw_pp) {
1195 DPU_ERROR_ENC(dpu_enc,
1196 "no pp block assigned at idx: %d\n", i);
1197 return;
1198 }
1199
1200 phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL;
1201 if (!phys->hw_ctl) {
1202 DPU_ERROR_ENC(dpu_enc,
1203 "no ctl block assigned at idx: %d\n", i);
1204 return;
1205 }
1206
1207 phys->cached_mode = crtc_state->adjusted_mode;
1208 if (phys->ops.atomic_mode_set)
1209 phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
1210 }
1211 }
1212
_dpu_encoder_virt_enable_helper(struct drm_encoder * drm_enc)1213 static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
1214 {
1215 struct dpu_encoder_virt *dpu_enc = NULL;
1216 int i;
1217
1218 if (!drm_enc || !drm_enc->dev) {
1219 DPU_ERROR("invalid parameters\n");
1220 return;
1221 }
1222
1223 dpu_enc = to_dpu_encoder_virt(drm_enc);
1224 if (!dpu_enc || !dpu_enc->cur_master) {
1225 DPU_ERROR("invalid dpu encoder/master\n");
1226 return;
1227 }
1228
1229
1230 if (dpu_enc->disp_info.intf_type == INTF_DP &&
1231 dpu_enc->cur_master->hw_mdptop &&
1232 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
1233 dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
1234 dpu_enc->cur_master->hw_mdptop);
1235
1236 if (dpu_enc->disp_info.is_cmd_mode)
1237 _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info);
1238
1239 if (dpu_enc->disp_info.intf_type == INTF_DSI &&
1240 !WARN_ON(dpu_enc->num_phys_encs == 0)) {
1241 unsigned bpc = dpu_enc->connector->display_info.bpc;
1242 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1243 if (!dpu_enc->hw_pp[i])
1244 continue;
1245 _dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
1246 }
1247 }
1248 }
1249
dpu_encoder_virt_runtime_resume(struct drm_encoder * drm_enc)1250 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
1251 {
1252 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1253
1254 mutex_lock(&dpu_enc->enc_lock);
1255
1256 if (!dpu_enc->enabled)
1257 goto out;
1258
1259 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.restore)
1260 dpu_enc->cur_slave->ops.restore(dpu_enc->cur_slave);
1261 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.restore)
1262 dpu_enc->cur_master->ops.restore(dpu_enc->cur_master);
1263
1264 _dpu_encoder_virt_enable_helper(drm_enc);
1265
1266 out:
1267 mutex_unlock(&dpu_enc->enc_lock);
1268 }
1269
dpu_encoder_virt_atomic_enable(struct drm_encoder * drm_enc,struct drm_atomic_state * state)1270 static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc,
1271 struct drm_atomic_state *state)
1272 {
1273 struct dpu_encoder_virt *dpu_enc = NULL;
1274 int ret = 0;
1275 struct drm_display_mode *cur_mode = NULL;
1276
1277 dpu_enc = to_dpu_encoder_virt(drm_enc);
1278 dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc);
1279
1280 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0);
1281
1282 mutex_lock(&dpu_enc->enc_lock);
1283
1284 dpu_enc->commit_done_timedout = false;
1285
1286 dpu_enc->connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
1287
1288 cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
1289
1290 dpu_enc->wide_bus_en = dpu_encoder_is_widebus_enabled(drm_enc);
1291
1292 trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
1293 cur_mode->vdisplay);
1294
1295 /* always enable slave encoder before master */
1296 if (dpu_enc->cur_slave && dpu_enc->cur_slave->ops.enable)
1297 dpu_enc->cur_slave->ops.enable(dpu_enc->cur_slave);
1298
1299 if (dpu_enc->cur_master && dpu_enc->cur_master->ops.enable)
1300 dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
1301
1302 ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1303 if (ret) {
1304 DPU_ERROR_ENC(dpu_enc, "dpu resource control failed: %d\n",
1305 ret);
1306 goto out;
1307 }
1308
1309 _dpu_encoder_virt_enable_helper(drm_enc);
1310
1311 dpu_enc->enabled = true;
1312
1313 out:
1314 mutex_unlock(&dpu_enc->enc_lock);
1315 }
1316
dpu_encoder_virt_atomic_disable(struct drm_encoder * drm_enc,struct drm_atomic_state * state)1317 static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc,
1318 struct drm_atomic_state *state)
1319 {
1320 struct dpu_encoder_virt *dpu_enc = NULL;
1321 struct drm_crtc *crtc;
1322 struct drm_crtc_state *old_state = NULL;
1323 int i = 0;
1324
1325 dpu_enc = to_dpu_encoder_virt(drm_enc);
1326 DPU_DEBUG_ENC(dpu_enc, "\n");
1327
1328 crtc = drm_atomic_get_old_crtc_for_encoder(state, drm_enc);
1329 if (crtc)
1330 old_state = drm_atomic_get_old_crtc_state(state, crtc);
1331
1332 /*
1333 * The encoder is already disabled if self refresh mode was set earlier,
1334 * in the old_state for the corresponding crtc.
1335 */
1336 if (old_state && old_state->self_refresh_active)
1337 return;
1338
1339 mutex_lock(&dpu_enc->enc_lock);
1340 dpu_enc->enabled = false;
1341
1342 trace_dpu_enc_disable(DRMID(drm_enc));
1343
1344 /* wait for idle */
1345 dpu_encoder_wait_for_tx_complete(drm_enc);
1346
1347 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
1348
1349 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1350 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1351
1352 if (phys->ops.disable)
1353 phys->ops.disable(phys);
1354 }
1355
1356
1357 /* after phys waits for frame-done, should be no more frames pending */
1358 if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
1359 DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
1360 del_timer_sync(&dpu_enc->frame_done_timer);
1361 }
1362
1363 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);
1364
1365 dpu_enc->connector = NULL;
1366
1367 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1368
1369 mutex_unlock(&dpu_enc->enc_lock);
1370 }
1371
dpu_encoder_get_intf(const struct dpu_mdss_cfg * catalog,struct dpu_rm * dpu_rm,enum dpu_intf_type type,u32 controller_id)1372 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,
1373 struct dpu_rm *dpu_rm,
1374 enum dpu_intf_type type, u32 controller_id)
1375 {
1376 int i = 0;
1377
1378 if (type == INTF_WB)
1379 return NULL;
1380
1381 for (i = 0; i < catalog->intf_count; i++) {
1382 if (catalog->intf[i].type == type
1383 && catalog->intf[i].controller_id == controller_id) {
1384 return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id);
1385 }
1386 }
1387
1388 return NULL;
1389 }
1390
dpu_encoder_vblank_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1391 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
1392 struct dpu_encoder_phys *phy_enc)
1393 {
1394 struct dpu_encoder_virt *dpu_enc = NULL;
1395 unsigned long lock_flags;
1396
1397 if (!drm_enc || !phy_enc)
1398 return;
1399
1400 DPU_ATRACE_BEGIN("encoder_vblank_callback");
1401 dpu_enc = to_dpu_encoder_virt(drm_enc);
1402
1403 atomic_inc(&phy_enc->vsync_cnt);
1404
1405 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1406 if (dpu_enc->crtc)
1407 dpu_crtc_vblank_callback(dpu_enc->crtc);
1408 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1409
1410 DPU_ATRACE_END("encoder_vblank_callback");
1411 }
1412
dpu_encoder_underrun_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phy_enc)1413 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
1414 struct dpu_encoder_phys *phy_enc)
1415 {
1416 if (!phy_enc)
1417 return;
1418
1419 DPU_ATRACE_BEGIN("encoder_underrun_callback");
1420 atomic_inc(&phy_enc->underrun_cnt);
1421
1422 /* trigger dump only on the first underrun */
1423 if (atomic_read(&phy_enc->underrun_cnt) == 1)
1424 msm_disp_snapshot_state(drm_enc->dev);
1425
1426 trace_dpu_enc_underrun_cb(DRMID(drm_enc),
1427 atomic_read(&phy_enc->underrun_cnt));
1428 DPU_ATRACE_END("encoder_underrun_callback");
1429 }
1430
dpu_encoder_assign_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc)1431 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc)
1432 {
1433 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1434 unsigned long lock_flags;
1435
1436 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1437 /* crtc should always be cleared before re-assigning */
1438 WARN_ON(crtc && dpu_enc->crtc);
1439 dpu_enc->crtc = crtc;
1440 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1441 }
1442
dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder * drm_enc,struct drm_crtc * crtc,bool enable)1443 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
1444 struct drm_crtc *crtc, bool enable)
1445 {
1446 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1447 unsigned long lock_flags;
1448 int i;
1449
1450 trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
1451
1452 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1453 if (dpu_enc->crtc != crtc) {
1454 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1455 return;
1456 }
1457 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1458
1459 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1460 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1461
1462 if (phys->ops.control_vblank_irq)
1463 phys->ops.control_vblank_irq(phys, enable);
1464 }
1465 }
1466
dpu_encoder_frame_done_callback(struct drm_encoder * drm_enc,struct dpu_encoder_phys * ready_phys,u32 event)1467 void dpu_encoder_frame_done_callback(
1468 struct drm_encoder *drm_enc,
1469 struct dpu_encoder_phys *ready_phys, u32 event)
1470 {
1471 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
1472 unsigned int i;
1473
1474 if (event & (DPU_ENCODER_FRAME_EVENT_DONE
1475 | DPU_ENCODER_FRAME_EVENT_ERROR
1476 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
1477
1478 if (!dpu_enc->frame_busy_mask[0]) {
1479 /**
1480 * suppress frame_done without waiter,
1481 * likely autorefresh
1482 */
1483 trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event,
1484 dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),
1485 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1,
1486 ready_phys->hw_wb ? ready_phys->hw_wb->idx : -1);
1487 return;
1488 }
1489
1490 /* One of the physical encoders has become idle */
1491 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1492 if (dpu_enc->phys_encs[i] == ready_phys) {
1493 trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
1494 dpu_enc->frame_busy_mask[0]);
1495 clear_bit(i, dpu_enc->frame_busy_mask);
1496 }
1497 }
1498
1499 if (!dpu_enc->frame_busy_mask[0]) {
1500 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
1501 del_timer(&dpu_enc->frame_done_timer);
1502
1503 dpu_encoder_resource_control(drm_enc,
1504 DPU_ENC_RC_EVENT_FRAME_DONE);
1505
1506 if (dpu_enc->crtc)
1507 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
1508 }
1509 } else {
1510 if (dpu_enc->crtc)
1511 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
1512 }
1513 }
1514
dpu_encoder_off_work(struct work_struct * work)1515 static void dpu_encoder_off_work(struct work_struct *work)
1516 {
1517 struct dpu_encoder_virt *dpu_enc = container_of(work,
1518 struct dpu_encoder_virt, delayed_off_work.work);
1519
1520 dpu_encoder_resource_control(&dpu_enc->base,
1521 DPU_ENC_RC_EVENT_ENTER_IDLE);
1522
1523 dpu_encoder_frame_done_callback(&dpu_enc->base, NULL,
1524 DPU_ENCODER_FRAME_EVENT_IDLE);
1525 }
1526
1527 /**
1528 * _dpu_encoder_trigger_flush - trigger flush for a physical encoder
1529 * @drm_enc: Pointer to drm encoder structure
1530 * @phys: Pointer to physical encoder structure
1531 * @extra_flush_bits: Additional bit mask to include in flush trigger
1532 */
_dpu_encoder_trigger_flush(struct drm_encoder * drm_enc,struct dpu_encoder_phys * phys,uint32_t extra_flush_bits)1533 static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
1534 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits)
1535 {
1536 struct dpu_hw_ctl *ctl;
1537 int pending_kickoff_cnt;
1538 u32 ret = UINT_MAX;
1539
1540 if (!phys->hw_pp) {
1541 DPU_ERROR("invalid pingpong hw\n");
1542 return;
1543 }
1544
1545 ctl = phys->hw_ctl;
1546 if (!ctl->ops.trigger_flush) {
1547 DPU_ERROR("missing trigger cb\n");
1548 return;
1549 }
1550
1551 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
1552
1553 if (extra_flush_bits && ctl->ops.update_pending_flush)
1554 ctl->ops.update_pending_flush(ctl, extra_flush_bits);
1555
1556 ctl->ops.trigger_flush(ctl);
1557
1558 if (ctl->ops.get_pending_flush)
1559 ret = ctl->ops.get_pending_flush(ctl);
1560
1561 trace_dpu_enc_trigger_flush(DRMID(drm_enc),
1562 dpu_encoder_helper_get_intf_type(phys->intf_mode),
1563 phys->hw_intf ? phys->hw_intf->idx : -1,
1564 phys->hw_wb ? phys->hw_wb->idx : -1,
1565 pending_kickoff_cnt, ctl->idx,
1566 extra_flush_bits, ret);
1567 }
1568
1569 /**
1570 * _dpu_encoder_trigger_start - trigger start for a physical encoder
1571 * @phys: Pointer to physical encoder structure
1572 */
_dpu_encoder_trigger_start(struct dpu_encoder_phys * phys)1573 static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
1574 {
1575 if (!phys) {
1576 DPU_ERROR("invalid argument(s)\n");
1577 return;
1578 }
1579
1580 if (!phys->hw_pp) {
1581 DPU_ERROR("invalid pingpong hw\n");
1582 return;
1583 }
1584
1585 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
1586 phys->ops.trigger_start(phys);
1587 }
1588
dpu_encoder_helper_trigger_start(struct dpu_encoder_phys * phys_enc)1589 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc)
1590 {
1591 struct dpu_hw_ctl *ctl;
1592
1593 ctl = phys_enc->hw_ctl;
1594 if (ctl->ops.trigger_start) {
1595 ctl->ops.trigger_start(ctl);
1596 trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
1597 }
1598 }
1599
dpu_encoder_helper_wait_event_timeout(int32_t drm_id,unsigned int irq_idx,struct dpu_encoder_wait_info * info)1600 static int dpu_encoder_helper_wait_event_timeout(
1601 int32_t drm_id,
1602 unsigned int irq_idx,
1603 struct dpu_encoder_wait_info *info)
1604 {
1605 int rc = 0;
1606 s64 expected_time = ktime_to_ms(ktime_get()) + info->timeout_ms;
1607 s64 jiffies = msecs_to_jiffies(info->timeout_ms);
1608 s64 time;
1609
1610 do {
1611 rc = wait_event_timeout(*(info->wq),
1612 atomic_read(info->atomic_cnt) == 0, jiffies);
1613 time = ktime_to_ms(ktime_get());
1614
1615 trace_dpu_enc_wait_event_timeout(drm_id,
1616 DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx),
1617 rc, time,
1618 expected_time,
1619 atomic_read(info->atomic_cnt));
1620 /* If we timed out, counter is valid and time is less, wait again */
1621 } while (atomic_read(info->atomic_cnt) && (rc == 0) &&
1622 (time < expected_time));
1623
1624 return rc;
1625 }
1626
dpu_encoder_helper_hw_reset(struct dpu_encoder_phys * phys_enc)1627 static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)
1628 {
1629 struct dpu_encoder_virt *dpu_enc;
1630 struct dpu_hw_ctl *ctl;
1631 int rc;
1632 struct drm_encoder *drm_enc;
1633
1634 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
1635 ctl = phys_enc->hw_ctl;
1636 drm_enc = phys_enc->parent;
1637
1638 if (!ctl->ops.reset)
1639 return;
1640
1641 DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
1642 ctl->idx);
1643
1644 rc = ctl->ops.reset(ctl);
1645 if (rc) {
1646 DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx);
1647 msm_disp_snapshot_state(drm_enc->dev);
1648 }
1649
1650 phys_enc->enable_state = DPU_ENC_ENABLED;
1651 }
1652
1653 /**
1654 * _dpu_encoder_kickoff_phys - handle physical encoder kickoff
1655 * Iterate through the physical encoders and perform consolidated flush
1656 * and/or control start triggering as needed. This is done in the virtual
1657 * encoder rather than the individual physical ones in order to handle
1658 * use cases that require visibility into multiple physical encoders at
1659 * a time.
1660 * @dpu_enc: Pointer to virtual encoder structure
1661 */
_dpu_encoder_kickoff_phys(struct dpu_encoder_virt * dpu_enc)1662 static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
1663 {
1664 struct dpu_hw_ctl *ctl;
1665 uint32_t i, pending_flush;
1666 unsigned long lock_flags;
1667
1668 pending_flush = 0x0;
1669
1670 /* update pending counts and trigger kickoff ctl flush atomically */
1671 spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
1672
1673 /* don't perform flush/start operations for slave encoders */
1674 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1675 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
1676
1677 if (phys->enable_state == DPU_ENC_DISABLED)
1678 continue;
1679
1680 ctl = phys->hw_ctl;
1681
1682 /*
1683 * This is cleared in frame_done worker, which isn't invoked
1684 * for async commits. So don't set this for async, since it'll
1685 * roll over to the next commit.
1686 */
1687 if (phys->split_role != ENC_ROLE_SLAVE)
1688 set_bit(i, dpu_enc->frame_busy_mask);
1689
1690 if (!phys->ops.needs_single_flush ||
1691 !phys->ops.needs_single_flush(phys))
1692 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0);
1693 else if (ctl->ops.get_pending_flush)
1694 pending_flush |= ctl->ops.get_pending_flush(ctl);
1695 }
1696
1697 /* for split flush, combine pending flush masks and send to master */
1698 if (pending_flush && dpu_enc->cur_master) {
1699 _dpu_encoder_trigger_flush(
1700 &dpu_enc->base,
1701 dpu_enc->cur_master,
1702 pending_flush);
1703 }
1704
1705 _dpu_encoder_trigger_start(dpu_enc->cur_master);
1706
1707 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
1708 }
1709
dpu_encoder_trigger_kickoff_pending(struct drm_encoder * drm_enc)1710 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
1711 {
1712 struct dpu_encoder_virt *dpu_enc;
1713 struct dpu_encoder_phys *phys;
1714 unsigned int i;
1715 struct dpu_hw_ctl *ctl;
1716 struct msm_display_info *disp_info;
1717
1718 if (!drm_enc) {
1719 DPU_ERROR("invalid encoder\n");
1720 return;
1721 }
1722 dpu_enc = to_dpu_encoder_virt(drm_enc);
1723 disp_info = &dpu_enc->disp_info;
1724
1725 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1726 phys = dpu_enc->phys_encs[i];
1727
1728 ctl = phys->hw_ctl;
1729 ctl->ops.clear_pending_flush(ctl);
1730
1731 /* update only for command mode primary ctl */
1732 if ((phys == dpu_enc->cur_master) &&
1733 disp_info->is_cmd_mode
1734 && ctl->ops.trigger_pending)
1735 ctl->ops.trigger_pending(ctl);
1736 }
1737 }
1738
_dpu_encoder_calculate_linetime(struct dpu_encoder_virt * dpu_enc,struct drm_display_mode * mode)1739 static u32 _dpu_encoder_calculate_linetime(struct dpu_encoder_virt *dpu_enc,
1740 struct drm_display_mode *mode)
1741 {
1742 u64 pclk_rate;
1743 u32 pclk_period;
1744 u32 line_time;
1745
1746 /*
1747 * For linetime calculation, only operate on master encoder.
1748 */
1749 if (!dpu_enc->cur_master)
1750 return 0;
1751
1752 if (!dpu_enc->cur_master->ops.get_line_count) {
1753 DPU_ERROR("get_line_count function not defined\n");
1754 return 0;
1755 }
1756
1757 pclk_rate = mode->clock; /* pixel clock in kHz */
1758 if (pclk_rate == 0) {
1759 DPU_ERROR("pclk is 0, cannot calculate line time\n");
1760 return 0;
1761 }
1762
1763 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate);
1764 if (pclk_period == 0) {
1765 DPU_ERROR("pclk period is 0\n");
1766 return 0;
1767 }
1768
1769 /*
1770 * Line time calculation based on Pixel clock and HTOTAL.
1771 * Final unit is in ns.
1772 */
1773 line_time = (pclk_period * mode->htotal) / 1000;
1774 if (line_time == 0) {
1775 DPU_ERROR("line time calculation is 0\n");
1776 return 0;
1777 }
1778
1779 DPU_DEBUG_ENC(dpu_enc,
1780 "clk_rate=%lldkHz, clk_period=%d, linetime=%dns\n",
1781 pclk_rate, pclk_period, line_time);
1782
1783 return line_time;
1784 }
1785
dpu_encoder_vsync_time(struct drm_encoder * drm_enc,ktime_t * wakeup_time)1786 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time)
1787 {
1788 struct drm_display_mode *mode;
1789 struct dpu_encoder_virt *dpu_enc;
1790 u32 cur_line;
1791 u32 line_time;
1792 u32 vtotal, time_to_vsync;
1793 ktime_t cur_time;
1794
1795 dpu_enc = to_dpu_encoder_virt(drm_enc);
1796
1797 if (!drm_enc->crtc || !drm_enc->crtc->state) {
1798 DPU_ERROR("crtc/crtc state object is NULL\n");
1799 return -EINVAL;
1800 }
1801 mode = &drm_enc->crtc->state->adjusted_mode;
1802
1803 line_time = _dpu_encoder_calculate_linetime(dpu_enc, mode);
1804 if (!line_time)
1805 return -EINVAL;
1806
1807 cur_line = dpu_enc->cur_master->ops.get_line_count(dpu_enc->cur_master);
1808
1809 vtotal = mode->vtotal;
1810 if (cur_line >= vtotal)
1811 time_to_vsync = line_time * vtotal;
1812 else
1813 time_to_vsync = line_time * (vtotal - cur_line);
1814
1815 if (time_to_vsync == 0) {
1816 DPU_ERROR("time to vsync should not be zero, vtotal=%d\n",
1817 vtotal);
1818 return -EINVAL;
1819 }
1820
1821 cur_time = ktime_get();
1822 *wakeup_time = ktime_add_ns(cur_time, time_to_vsync);
1823
1824 DPU_DEBUG_ENC(dpu_enc,
1825 "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
1826 cur_line, vtotal, time_to_vsync,
1827 ktime_to_ms(cur_time),
1828 ktime_to_ms(*wakeup_time));
1829 return 0;
1830 }
1831
1832 static u32
dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config * dsc,u32 enc_ip_width)1833 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc,
1834 u32 enc_ip_width)
1835 {
1836 int ssm_delay, total_pixels, soft_slice_per_enc;
1837
1838 soft_slice_per_enc = enc_ip_width / dsc->slice_width;
1839
1840 /*
1841 * minimum number of initial line pixels is a sum of:
1842 * 1. sub-stream multiplexer delay (83 groups for 8bpc,
1843 * 91 for 10 bpc) * 3
1844 * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
1845 * 3. the initial xmit delay
1846 * 4. total pipeline delay through the "lock step" of encoder (47)
1847 * 5. 6 additional pixels as the output of the rate buffer is
1848 * 48 bits wide
1849 */
1850 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92);
1851 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
1852 if (soft_slice_per_enc > 1)
1853 total_pixels += (ssm_delay * 3);
1854 return DIV_ROUND_UP(total_pixels, dsc->slice_width);
1855 }
1856
dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl * ctl,struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp,struct drm_dsc_config * dsc,u32 common_mode,u32 initial_lines)1857 static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_ctl *ctl,
1858 struct dpu_hw_dsc *hw_dsc,
1859 struct dpu_hw_pingpong *hw_pp,
1860 struct drm_dsc_config *dsc,
1861 u32 common_mode,
1862 u32 initial_lines)
1863 {
1864 if (hw_dsc->ops.dsc_config)
1865 hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines);
1866
1867 if (hw_dsc->ops.dsc_config_thresh)
1868 hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
1869
1870 if (hw_pp->ops.setup_dsc)
1871 hw_pp->ops.setup_dsc(hw_pp);
1872
1873 if (hw_dsc->ops.dsc_bind_pingpong_blk)
1874 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, hw_pp->idx);
1875
1876 if (hw_pp->ops.enable_dsc)
1877 hw_pp->ops.enable_dsc(hw_pp);
1878
1879 if (ctl->ops.update_pending_flush_dsc)
1880 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
1881 }
1882
dpu_encoder_prep_dsc(struct dpu_encoder_virt * dpu_enc,struct drm_dsc_config * dsc)1883 static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
1884 struct drm_dsc_config *dsc)
1885 {
1886 /* coding only for 2LM, 2enc, 1 dsc config */
1887 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
1888 struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
1889 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
1890 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
1891 int this_frame_slices;
1892 int intf_ip_w, enc_ip_w;
1893 int dsc_common_mode;
1894 int pic_width;
1895 u32 initial_lines;
1896 int i;
1897
1898 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
1899 hw_pp[i] = dpu_enc->hw_pp[i];
1900 hw_dsc[i] = dpu_enc->hw_dsc[i];
1901
1902 if (!hw_pp[i] || !hw_dsc[i]) {
1903 DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
1904 return;
1905 }
1906 }
1907
1908 dsc_common_mode = 0;
1909 pic_width = dsc->pic_width;
1910
1911 dsc_common_mode = DSC_MODE_SPLIT_PANEL;
1912 if (dpu_encoder_use_dsc_merge(enc_master->parent))
1913 dsc_common_mode |= DSC_MODE_MULTIPLEX;
1914 if (enc_master->intf_mode == INTF_MODE_VIDEO)
1915 dsc_common_mode |= DSC_MODE_VIDEO;
1916
1917 this_frame_slices = pic_width / dsc->slice_width;
1918 intf_ip_w = this_frame_slices * dsc->slice_width;
1919
1920 /*
1921 * dsc merge case: when using 2 encoders for the same stream,
1922 * no. of slices need to be same on both the encoders.
1923 */
1924 enc_ip_w = intf_ip_w / 2;
1925 initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
1926
1927 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
1928 dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i],
1929 dsc, dsc_common_mode, initial_lines);
1930 }
1931
dpu_encoder_prepare_for_kickoff(struct drm_encoder * drm_enc)1932 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
1933 {
1934 struct dpu_encoder_virt *dpu_enc;
1935 struct dpu_encoder_phys *phys;
1936 bool needs_hw_reset = false;
1937 unsigned int i;
1938
1939 dpu_enc = to_dpu_encoder_virt(drm_enc);
1940
1941 trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
1942
1943 /* prepare for next kickoff, may include waiting on previous kickoff */
1944 DPU_ATRACE_BEGIN("enc_prepare_for_kickoff");
1945 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1946 phys = dpu_enc->phys_encs[i];
1947 if (phys->ops.prepare_for_kickoff)
1948 phys->ops.prepare_for_kickoff(phys);
1949 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET)
1950 needs_hw_reset = true;
1951 }
1952 DPU_ATRACE_END("enc_prepare_for_kickoff");
1953
1954 dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
1955
1956 /* if any phys needs reset, reset all phys, in-order */
1957 if (needs_hw_reset) {
1958 trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
1959 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1960 dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
1961 }
1962 }
1963
1964 if (dpu_enc->dsc)
1965 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
1966 }
1967
dpu_encoder_is_valid_for_commit(struct drm_encoder * drm_enc)1968 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc)
1969 {
1970 struct dpu_encoder_virt *dpu_enc;
1971 unsigned int i;
1972 struct dpu_encoder_phys *phys;
1973
1974 dpu_enc = to_dpu_encoder_virt(drm_enc);
1975
1976 if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1977 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
1978 phys = dpu_enc->phys_encs[i];
1979 if (phys->ops.is_valid_for_commit && !phys->ops.is_valid_for_commit(phys)) {
1980 DPU_DEBUG("invalid FB not kicking off\n");
1981 return false;
1982 }
1983 }
1984 }
1985
1986 return true;
1987 }
1988
dpu_encoder_kickoff(struct drm_encoder * drm_enc)1989 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
1990 {
1991 struct dpu_encoder_virt *dpu_enc;
1992 struct dpu_encoder_phys *phys;
1993 unsigned long timeout_ms;
1994 unsigned int i;
1995
1996 DPU_ATRACE_BEGIN("encoder_kickoff");
1997 dpu_enc = to_dpu_encoder_virt(drm_enc);
1998
1999 trace_dpu_enc_kickoff(DRMID(drm_enc));
2000
2001 timeout_ms = DPU_ENCODER_FRAME_DONE_TIMEOUT_FRAMES * 1000 /
2002 drm_mode_vrefresh(&drm_enc->crtc->state->adjusted_mode);
2003
2004 atomic_set(&dpu_enc->frame_done_timeout_ms, timeout_ms);
2005 mod_timer(&dpu_enc->frame_done_timer,
2006 jiffies + msecs_to_jiffies(timeout_ms));
2007
2008 /* All phys encs are ready to go, trigger the kickoff */
2009 _dpu_encoder_kickoff_phys(dpu_enc);
2010
2011 /* allow phys encs to handle any post-kickoff business */
2012 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2013 phys = dpu_enc->phys_encs[i];
2014 if (phys->ops.handle_post_kickoff)
2015 phys->ops.handle_post_kickoff(phys);
2016 }
2017
2018 DPU_ATRACE_END("encoder_kickoff");
2019 }
2020
dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys * phys_enc)2021 static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
2022 {
2023 struct dpu_hw_mixer_cfg mixer;
2024 int i, num_lm;
2025 struct dpu_global_state *global_state;
2026 struct dpu_hw_blk *hw_lm[2];
2027 struct dpu_hw_mixer *hw_mixer[2];
2028 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2029
2030 memset(&mixer, 0, sizeof(mixer));
2031
2032 /* reset all mixers for this encoder */
2033 if (phys_enc->hw_ctl->ops.clear_all_blendstages)
2034 phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
2035
2036 global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms);
2037
2038 num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state,
2039 phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
2040
2041 for (i = 0; i < num_lm; i++) {
2042 hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]);
2043 if (phys_enc->hw_ctl->ops.update_pending_flush_mixer)
2044 phys_enc->hw_ctl->ops.update_pending_flush_mixer(ctl, hw_mixer[i]->idx);
2045
2046 /* clear all blendstages */
2047 if (phys_enc->hw_ctl->ops.setup_blendstage)
2048 phys_enc->hw_ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL);
2049 }
2050 }
2051
dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl * ctl,struct dpu_hw_dsc * hw_dsc,struct dpu_hw_pingpong * hw_pp)2052 static void dpu_encoder_dsc_pipe_clr(struct dpu_hw_ctl *ctl,
2053 struct dpu_hw_dsc *hw_dsc,
2054 struct dpu_hw_pingpong *hw_pp)
2055 {
2056 if (hw_dsc->ops.dsc_disable)
2057 hw_dsc->ops.dsc_disable(hw_dsc);
2058
2059 if (hw_pp->ops.disable_dsc)
2060 hw_pp->ops.disable_dsc(hw_pp);
2061
2062 if (hw_dsc->ops.dsc_bind_pingpong_blk)
2063 hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE);
2064
2065 if (ctl->ops.update_pending_flush_dsc)
2066 ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx);
2067 }
2068
dpu_encoder_unprep_dsc(struct dpu_encoder_virt * dpu_enc)2069 static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc)
2070 {
2071 /* coding only for 2LM, 2enc, 1 dsc config */
2072 struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
2073 struct dpu_hw_ctl *ctl = enc_master->hw_ctl;
2074 struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
2075 struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
2076 int i;
2077
2078 for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
2079 hw_pp[i] = dpu_enc->hw_pp[i];
2080 hw_dsc[i] = dpu_enc->hw_dsc[i];
2081
2082 if (hw_pp[i] && hw_dsc[i])
2083 dpu_encoder_dsc_pipe_clr(ctl, hw_dsc[i], hw_pp[i]);
2084 }
2085 }
2086
dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys * phys_enc)2087 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
2088 {
2089 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
2090 struct dpu_hw_intf_cfg intf_cfg = { 0 };
2091 int i;
2092 struct dpu_encoder_virt *dpu_enc;
2093
2094 dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
2095
2096 phys_enc->hw_ctl->ops.reset(ctl);
2097
2098 dpu_encoder_helper_reset_mixers(phys_enc);
2099
2100 /*
2101 * TODO: move the once-only operation like CTL flush/trigger
2102 * into dpu_encoder_virt_disable() and all operations which need
2103 * to be done per phys encoder into the phys_disable() op.
2104 */
2105 if (phys_enc->hw_wb) {
2106 /* disable the PP block */
2107 if (phys_enc->hw_wb->ops.bind_pingpong_blk)
2108 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, PINGPONG_NONE);
2109
2110 /* mark WB flush as pending */
2111 if (phys_enc->hw_ctl->ops.update_pending_flush_wb)
2112 phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, phys_enc->hw_wb->idx);
2113 } else {
2114 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2115 if (dpu_enc->phys_encs[i] && phys_enc->hw_intf->ops.bind_pingpong_blk)
2116 phys_enc->hw_intf->ops.bind_pingpong_blk(
2117 dpu_enc->phys_encs[i]->hw_intf,
2118 PINGPONG_NONE);
2119
2120 /* mark INTF flush as pending */
2121 if (phys_enc->hw_ctl->ops.update_pending_flush_intf)
2122 phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl,
2123 dpu_enc->phys_encs[i]->hw_intf->idx);
2124 }
2125 }
2126
2127 if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither)
2128 phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL);
2129
2130 /* reset the merge 3D HW block */
2131 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d) {
2132 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
2133 BLEND_3D_NONE);
2134 if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d)
2135 phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl,
2136 phys_enc->hw_pp->merge_3d->idx);
2137 }
2138
2139 if (phys_enc->hw_cdm) {
2140 if (phys_enc->hw_cdm->ops.bind_pingpong_blk && phys_enc->hw_pp)
2141 phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
2142 PINGPONG_NONE);
2143 if (phys_enc->hw_ctl->ops.update_pending_flush_cdm)
2144 phys_enc->hw_ctl->ops.update_pending_flush_cdm(phys_enc->hw_ctl,
2145 phys_enc->hw_cdm->idx);
2146 }
2147
2148 if (dpu_enc->dsc) {
2149 dpu_encoder_unprep_dsc(dpu_enc);
2150 dpu_enc->dsc = NULL;
2151 }
2152
2153 intf_cfg.stream_sel = 0; /* Don't care value for video mode */
2154 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
2155 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
2156
2157 if (phys_enc->hw_intf)
2158 intf_cfg.intf = phys_enc->hw_intf->idx;
2159 if (phys_enc->hw_wb)
2160 intf_cfg.wb = phys_enc->hw_wb->idx;
2161
2162 if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d)
2163 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
2164
2165 if (ctl->ops.reset_intf_cfg)
2166 ctl->ops.reset_intf_cfg(ctl, &intf_cfg);
2167
2168 ctl->ops.trigger_flush(ctl);
2169 ctl->ops.trigger_start(ctl);
2170 ctl->ops.clear_pending_flush(ctl);
2171 }
2172
dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys * phys_enc,const struct msm_format * dpu_fmt,u32 output_type)2173 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
2174 const struct msm_format *dpu_fmt,
2175 u32 output_type)
2176 {
2177 struct dpu_hw_cdm *hw_cdm;
2178 struct dpu_hw_cdm_cfg *cdm_cfg;
2179 struct dpu_hw_pingpong *hw_pp;
2180 int ret;
2181
2182 if (!phys_enc)
2183 return;
2184
2185 cdm_cfg = &phys_enc->cdm_cfg;
2186 hw_pp = phys_enc->hw_pp;
2187 hw_cdm = phys_enc->hw_cdm;
2188
2189 if (!hw_cdm)
2190 return;
2191
2192 if (!MSM_FORMAT_IS_YUV(dpu_fmt)) {
2193 DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent),
2194 &dpu_fmt->pixel_format);
2195 if (hw_cdm->ops.bind_pingpong_blk)
2196 hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
2197
2198 return;
2199 }
2200
2201 memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));
2202
2203 cdm_cfg->output_width = phys_enc->cached_mode.hdisplay;
2204 cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
2205 cdm_cfg->output_fmt = dpu_fmt;
2206 cdm_cfg->output_type = output_type;
2207 cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ?
2208 CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
2209 cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
2210
2211 /* enable 10 bit logic */
2212 switch (cdm_cfg->output_fmt->chroma_sample) {
2213 case CHROMA_FULL:
2214 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
2215 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2216 break;
2217 case CHROMA_H2V1:
2218 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
2219 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2220 break;
2221 case CHROMA_420:
2222 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
2223 cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
2224 break;
2225 case CHROMA_H1V2:
2226 default:
2227 DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
2228 DRMID(phys_enc->parent));
2229 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
2230 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
2231 break;
2232 }
2233
2234 DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n",
2235 DRMID(phys_enc->parent), cdm_cfg->output_width,
2236 cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format,
2237 cdm_cfg->output_type, cdm_cfg->output_bit_depth,
2238 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
2239
2240 if (hw_cdm->ops.enable) {
2241 cdm_cfg->pp_id = hw_pp->idx;
2242 ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
2243 if (ret < 0) {
2244 DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n",
2245 DRMID(phys_enc->parent), ret);
2246 return;
2247 }
2248 }
2249 }
2250
2251 #ifdef CONFIG_DEBUG_FS
_dpu_encoder_status_show(struct seq_file * s,void * data)2252 static int _dpu_encoder_status_show(struct seq_file *s, void *data)
2253 {
2254 struct drm_encoder *drm_enc = s->private;
2255 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
2256 int i;
2257
2258 mutex_lock(&dpu_enc->enc_lock);
2259 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2260 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2261
2262 seq_printf(s, "intf:%d wb:%d vsync:%8d underrun:%8d frame_done_cnt:%d",
2263 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1,
2264 phys->hw_wb ? phys->hw_wb->idx - WB_0 : -1,
2265 atomic_read(&phys->vsync_cnt),
2266 atomic_read(&phys->underrun_cnt),
2267 atomic_read(&dpu_enc->frame_done_timeout_cnt));
2268
2269 seq_printf(s, "mode: %s\n", dpu_encoder_helper_get_intf_type(phys->intf_mode));
2270 }
2271 mutex_unlock(&dpu_enc->enc_lock);
2272
2273 return 0;
2274 }
2275
2276 DEFINE_SHOW_ATTRIBUTE(_dpu_encoder_status);
2277
dpu_encoder_debugfs_init(struct drm_encoder * drm_enc,struct dentry * root)2278 static void dpu_encoder_debugfs_init(struct drm_encoder *drm_enc, struct dentry *root)
2279 {
2280 /* don't error check these */
2281 debugfs_create_file("status", 0600,
2282 root, drm_enc, &_dpu_encoder_status_fops);
2283 }
2284 #else
2285 #define dpu_encoder_debugfs_init NULL
2286 #endif
2287
dpu_encoder_virt_add_phys_encs(struct drm_device * dev,struct msm_display_info * disp_info,struct dpu_encoder_virt * dpu_enc,struct dpu_enc_phys_init_params * params)2288 static int dpu_encoder_virt_add_phys_encs(
2289 struct drm_device *dev,
2290 struct msm_display_info *disp_info,
2291 struct dpu_encoder_virt *dpu_enc,
2292 struct dpu_enc_phys_init_params *params)
2293 {
2294 struct dpu_encoder_phys *enc = NULL;
2295
2296 DPU_DEBUG_ENC(dpu_enc, "\n");
2297
2298 /*
2299 * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
2300 * in this function, check up-front.
2301 */
2302 if (dpu_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
2303 ARRAY_SIZE(dpu_enc->phys_encs)) {
2304 DPU_ERROR_ENC(dpu_enc, "too many physical encoders %d\n",
2305 dpu_enc->num_phys_encs);
2306 return -EINVAL;
2307 }
2308
2309
2310 if (disp_info->intf_type == INTF_WB) {
2311 enc = dpu_encoder_phys_wb_init(dev, params);
2312
2313 if (IS_ERR(enc)) {
2314 DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
2315 PTR_ERR(enc));
2316 return PTR_ERR(enc);
2317 }
2318
2319 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2320 ++dpu_enc->num_phys_encs;
2321 } else if (disp_info->is_cmd_mode) {
2322 enc = dpu_encoder_phys_cmd_init(dev, params);
2323
2324 if (IS_ERR(enc)) {
2325 DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n",
2326 PTR_ERR(enc));
2327 return PTR_ERR(enc);
2328 }
2329
2330 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2331 ++dpu_enc->num_phys_encs;
2332 } else {
2333 enc = dpu_encoder_phys_vid_init(dev, params);
2334
2335 if (IS_ERR(enc)) {
2336 DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n",
2337 PTR_ERR(enc));
2338 return PTR_ERR(enc);
2339 }
2340
2341 dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
2342 ++dpu_enc->num_phys_encs;
2343 }
2344
2345 if (params->split_role == ENC_ROLE_SLAVE)
2346 dpu_enc->cur_slave = enc;
2347 else
2348 dpu_enc->cur_master = enc;
2349
2350 return 0;
2351 }
2352
dpu_encoder_setup_display(struct dpu_encoder_virt * dpu_enc,struct dpu_kms * dpu_kms,struct msm_display_info * disp_info)2353 static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
2354 struct dpu_kms *dpu_kms,
2355 struct msm_display_info *disp_info)
2356 {
2357 int ret = 0;
2358 int i = 0;
2359 struct dpu_enc_phys_init_params phys_params;
2360
2361 if (!dpu_enc) {
2362 DPU_ERROR("invalid arg(s), enc %d\n", dpu_enc != NULL);
2363 return -EINVAL;
2364 }
2365
2366 dpu_enc->cur_master = NULL;
2367
2368 memset(&phys_params, 0, sizeof(phys_params));
2369 phys_params.dpu_kms = dpu_kms;
2370 phys_params.parent = &dpu_enc->base;
2371 phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
2372
2373 WARN_ON(disp_info->num_of_h_tiles < 1);
2374
2375 DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
2376
2377 if (disp_info->intf_type != INTF_WB)
2378 dpu_enc->idle_pc_supported =
2379 dpu_kms->catalog->caps->has_idle_pc;
2380
2381 mutex_lock(&dpu_enc->enc_lock);
2382 for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
2383 /*
2384 * Left-most tile is at index 0, content is controller id
2385 * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
2386 * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
2387 */
2388 u32 controller_id = disp_info->h_tile_instance[i];
2389
2390 if (disp_info->num_of_h_tiles > 1) {
2391 if (i == 0)
2392 phys_params.split_role = ENC_ROLE_MASTER;
2393 else
2394 phys_params.split_role = ENC_ROLE_SLAVE;
2395 } else {
2396 phys_params.split_role = ENC_ROLE_SOLO;
2397 }
2398
2399 DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
2400 i, controller_id, phys_params.split_role);
2401
2402 phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm,
2403 disp_info->intf_type,
2404 controller_id);
2405
2406 if (disp_info->intf_type == INTF_WB && controller_id < WB_MAX)
2407 phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id);
2408
2409 if (!phys_params.hw_intf && !phys_params.hw_wb) {
2410 DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
2411 ret = -EINVAL;
2412 break;
2413 }
2414
2415 if (phys_params.hw_intf && phys_params.hw_wb) {
2416 DPU_ERROR_ENC(dpu_enc,
2417 "invalid phys both intf and wb block at idx: %d\n", i);
2418 ret = -EINVAL;
2419 break;
2420 }
2421
2422 ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info,
2423 dpu_enc, &phys_params);
2424 if (ret) {
2425 DPU_ERROR_ENC(dpu_enc, "failed to add phys encs\n");
2426 break;
2427 }
2428 }
2429
2430 mutex_unlock(&dpu_enc->enc_lock);
2431
2432 return ret;
2433 }
2434
dpu_encoder_frame_done_timeout(struct timer_list * t)2435 static void dpu_encoder_frame_done_timeout(struct timer_list *t)
2436 {
2437 struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t,
2438 frame_done_timer);
2439 struct drm_encoder *drm_enc = &dpu_enc->base;
2440 u32 event;
2441
2442 if (!drm_enc->dev) {
2443 DPU_ERROR("invalid parameters\n");
2444 return;
2445 }
2446
2447 if (!dpu_enc->frame_busy_mask[0] || !dpu_enc->crtc) {
2448 DRM_DEBUG_KMS("id:%u invalid timeout frame_busy_mask=%lu\n",
2449 DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
2450 return;
2451 } else if (!atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
2452 DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
2453 return;
2454 }
2455
2456 DPU_ERROR_ENC_RATELIMITED(dpu_enc, "frame done timeout\n");
2457
2458 if (atomic_inc_return(&dpu_enc->frame_done_timeout_cnt) == 1)
2459 msm_disp_snapshot_state(drm_enc->dev);
2460
2461 event = DPU_ENCODER_FRAME_EVENT_ERROR;
2462 trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
2463 dpu_crtc_frame_event_cb(dpu_enc->crtc, event);
2464 }
2465
2466 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
2467 .atomic_mode_set = dpu_encoder_virt_atomic_mode_set,
2468 .atomic_disable = dpu_encoder_virt_atomic_disable,
2469 .atomic_enable = dpu_encoder_virt_atomic_enable,
2470 .atomic_check = dpu_encoder_virt_atomic_check,
2471 };
2472
2473 static const struct drm_encoder_funcs dpu_encoder_funcs = {
2474 .debugfs_init = dpu_encoder_debugfs_init,
2475 };
2476
dpu_encoder_init(struct drm_device * dev,int drm_enc_mode,struct msm_display_info * disp_info)2477 struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
2478 int drm_enc_mode,
2479 struct msm_display_info *disp_info)
2480 {
2481 struct msm_drm_private *priv = dev->dev_private;
2482 struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
2483 struct dpu_encoder_virt *dpu_enc;
2484 int ret;
2485
2486 dpu_enc = drmm_encoder_alloc(dev, struct dpu_encoder_virt, base,
2487 &dpu_encoder_funcs, drm_enc_mode, NULL);
2488 if (IS_ERR(dpu_enc))
2489 return ERR_CAST(dpu_enc);
2490
2491 drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs);
2492
2493 spin_lock_init(&dpu_enc->enc_spinlock);
2494 dpu_enc->enabled = false;
2495 mutex_init(&dpu_enc->enc_lock);
2496 mutex_init(&dpu_enc->rc_lock);
2497
2498 ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);
2499 if (ret) {
2500 DPU_ERROR("failed to setup encoder\n");
2501 return ERR_PTR(-ENOMEM);
2502 }
2503
2504 atomic_set(&dpu_enc->frame_done_timeout_ms, 0);
2505 atomic_set(&dpu_enc->frame_done_timeout_cnt, 0);
2506 timer_setup(&dpu_enc->frame_done_timer,
2507 dpu_encoder_frame_done_timeout, 0);
2508
2509 INIT_DELAYED_WORK(&dpu_enc->delayed_off_work,
2510 dpu_encoder_off_work);
2511 dpu_enc->idle_timeout = IDLE_TIMEOUT;
2512
2513 memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info));
2514
2515 DPU_DEBUG_ENC(dpu_enc, "created\n");
2516
2517 return &dpu_enc->base;
2518 }
2519
2520 /**
2521 * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state
2522 * @drm_enc: encoder pointer
2523 *
2524 * Wait for hardware to have flushed the current pending changes to hardware at
2525 * a vblank or CTL_START. Physical encoders will map this differently depending
2526 * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START.
2527 *
2528 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
2529 */
dpu_encoder_wait_for_commit_done(struct drm_encoder * drm_enc)2530 int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc)
2531 {
2532 struct dpu_encoder_virt *dpu_enc = NULL;
2533 int i, ret = 0;
2534
2535 if (!drm_enc) {
2536 DPU_ERROR("invalid encoder\n");
2537 return -EINVAL;
2538 }
2539 dpu_enc = to_dpu_encoder_virt(drm_enc);
2540 DPU_DEBUG_ENC(dpu_enc, "\n");
2541
2542 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2543 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2544
2545 if (phys->ops.wait_for_commit_done) {
2546 DPU_ATRACE_BEGIN("wait_for_commit_done");
2547 ret = phys->ops.wait_for_commit_done(phys);
2548 DPU_ATRACE_END("wait_for_commit_done");
2549 if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) {
2550 dpu_enc->commit_done_timedout = true;
2551 msm_disp_snapshot_state(drm_enc->dev);
2552 }
2553 if (ret)
2554 return ret;
2555 }
2556 }
2557
2558 return ret;
2559 }
2560
2561 /**
2562 * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel
2563 * @drm_enc: encoder pointer
2564 *
2565 * Wait for the hardware to transfer all the pixels to the panel. Physical
2566 * encoders will map this differently depending on the type: vid mode -> vsync_irq,
2567 * cmd mode -> pp_done.
2568 *
2569 * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
2570 */
dpu_encoder_wait_for_tx_complete(struct drm_encoder * drm_enc)2571 int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc)
2572 {
2573 struct dpu_encoder_virt *dpu_enc = NULL;
2574 int i, ret = 0;
2575
2576 if (!drm_enc) {
2577 DPU_ERROR("invalid encoder\n");
2578 return -EINVAL;
2579 }
2580 dpu_enc = to_dpu_encoder_virt(drm_enc);
2581 DPU_DEBUG_ENC(dpu_enc, "\n");
2582
2583 for (i = 0; i < dpu_enc->num_phys_encs; i++) {
2584 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
2585
2586 if (phys->ops.wait_for_tx_complete) {
2587 DPU_ATRACE_BEGIN("wait_for_tx_complete");
2588 ret = phys->ops.wait_for_tx_complete(phys);
2589 DPU_ATRACE_END("wait_for_tx_complete");
2590 if (ret)
2591 return ret;
2592 }
2593 }
2594
2595 return ret;
2596 }
2597
dpu_encoder_get_intf_mode(struct drm_encoder * encoder)2598 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
2599 {
2600 struct dpu_encoder_virt *dpu_enc = NULL;
2601
2602 if (!encoder) {
2603 DPU_ERROR("invalid encoder\n");
2604 return INTF_MODE_NONE;
2605 }
2606 dpu_enc = to_dpu_encoder_virt(encoder);
2607
2608 if (dpu_enc->cur_master)
2609 return dpu_enc->cur_master->intf_mode;
2610
2611 if (dpu_enc->num_phys_encs)
2612 return dpu_enc->phys_encs[0]->intf_mode;
2613
2614 return INTF_MODE_NONE;
2615 }
2616
dpu_encoder_helper_get_dsc(struct dpu_encoder_phys * phys_enc)2617 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
2618 {
2619 struct drm_encoder *encoder = phys_enc->parent;
2620 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
2621
2622 return dpu_enc->dsc_mask;
2623 }
2624
dpu_encoder_phys_init(struct dpu_encoder_phys * phys_enc,struct dpu_enc_phys_init_params * p)2625 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys_enc,
2626 struct dpu_enc_phys_init_params *p)
2627 {
2628 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
2629 phys_enc->hw_intf = p->hw_intf;
2630 phys_enc->hw_wb = p->hw_wb;
2631 phys_enc->parent = p->parent;
2632 phys_enc->dpu_kms = p->dpu_kms;
2633 phys_enc->split_role = p->split_role;
2634 phys_enc->enc_spinlock = p->enc_spinlock;
2635 phys_enc->enable_state = DPU_ENC_DISABLED;
2636
2637 atomic_set(&phys_enc->pending_kickoff_cnt, 0);
2638 atomic_set(&phys_enc->pending_ctlstart_cnt, 0);
2639
2640 atomic_set(&phys_enc->vsync_cnt, 0);
2641 atomic_set(&phys_enc->underrun_cnt, 0);
2642
2643 init_waitqueue_head(&phys_enc->pending_kickoff_wq);
2644 }
2645