1 /* 2 * Copyright (C) 2015 Red Hat, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef VIRTIO_DRV_H 27 #define VIRTIO_DRV_H 28 29 #include <linux/dma-direction.h> 30 #include <linux/virtio.h> 31 #include <linux/virtio_ids.h> 32 #include <linux/virtio_config.h> 33 #include <linux/virtio_gpu.h> 34 35 #include <drm/drm_atomic.h> 36 #include <drm/drm_drv.h> 37 #include <drm/drm_encoder.h> 38 #include <drm/drm_fourcc.h> 39 #include <drm/drm_framebuffer.h> 40 #include <drm/drm_gem.h> 41 #include <drm/drm_gem_shmem_helper.h> 42 #include <drm/drm_ioctl.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/virtgpu_drm.h> 45 46 #define DRIVER_NAME "virtio_gpu" 47 #define DRIVER_DESC "virtio GPU" 48 #define DRIVER_DATE "0" 49 50 #define DRIVER_MAJOR 0 51 #define DRIVER_MINOR 1 52 #define DRIVER_PATCHLEVEL 0 53 54 #define STATE_INITIALIZING 0 55 #define STATE_OK 1 56 #define STATE_ERR 2 57 58 #define MAX_CAPSET_ID 63 59 #define MAX_RINGS 64 60 61 /* See virtio_gpu_ctx_create. One additional character for NULL terminator. */ 62 #define DEBUG_NAME_MAX_LEN 65 63 64 struct virtio_gpu_object_params { 65 unsigned long size; 66 bool dumb; 67 /* 3d */ 68 bool virgl; 69 bool blob; 70 71 /* classic resources only */ 72 uint32_t format; 73 uint32_t width; 74 uint32_t height; 75 uint32_t target; 76 uint32_t bind; 77 uint32_t depth; 78 uint32_t array_size; 79 uint32_t last_level; 80 uint32_t nr_samples; 81 uint32_t flags; 82 83 /* blob resources only */ 84 uint32_t ctx_id; 85 uint32_t blob_mem; 86 uint32_t blob_flags; 87 uint64_t blob_id; 88 }; 89 90 struct virtio_gpu_object { 91 struct drm_gem_shmem_object base; 92 uint32_t hw_res_handle; 93 bool dumb; 94 bool created; 95 bool host3d_blob, guest_blob; 96 uint32_t blob_mem, blob_flags; 97 98 int uuid_state; 99 uuid_t uuid; 100 }; 101 #define gem_to_virtio_gpu_obj(gobj) \ 102 container_of((gobj), struct virtio_gpu_object, base.base) 103 104 struct virtio_gpu_object_shmem { 105 struct virtio_gpu_object base; 106 }; 107 108 struct virtio_gpu_object_vram { 109 struct virtio_gpu_object base; 110 uint32_t map_state; 111 uint32_t map_info; 112 struct drm_mm_node vram_node; 113 }; 114 115 #define to_virtio_gpu_shmem(virtio_gpu_object) \ 116 container_of((virtio_gpu_object), struct virtio_gpu_object_shmem, base) 117 118 #define to_virtio_gpu_vram(virtio_gpu_object) \ 119 container_of((virtio_gpu_object), struct virtio_gpu_object_vram, base) 120 121 struct virtio_gpu_object_array { 122 struct ww_acquire_ctx ticket; 123 struct list_head next; 124 u32 nents, total; 125 struct drm_gem_object *objs[] __counted_by(total); 126 }; 127 128 struct virtio_gpu_vbuffer; 129 struct virtio_gpu_device; 130 131 typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev, 132 struct virtio_gpu_vbuffer *vbuf); 133 134 struct virtio_gpu_fence_driver { 135 atomic64_t last_fence_id; 136 uint64_t current_fence_id; 137 uint64_t context; 138 struct list_head fences; 139 spinlock_t lock; 140 }; 141 142 struct virtio_gpu_fence_event { 143 struct drm_pending_event base; 144 struct drm_event event; 145 }; 146 147 struct virtio_gpu_fence { 148 struct dma_fence f; 149 uint32_t ring_idx; 150 uint64_t fence_id; 151 bool emit_fence_info; 152 struct virtio_gpu_fence_event *e; 153 struct virtio_gpu_fence_driver *drv; 154 struct list_head node; 155 }; 156 157 struct virtio_gpu_vbuffer { 158 char *buf; 159 int size; 160 161 void *data_buf; 162 uint32_t data_size; 163 164 char *resp_buf; 165 int resp_size; 166 virtio_gpu_resp_cb resp_cb; 167 void *resp_cb_data; 168 169 struct virtio_gpu_object_array *objs; 170 struct list_head list; 171 172 uint32_t seqno; 173 }; 174 175 struct virtio_gpu_output { 176 int index; 177 struct drm_crtc crtc; 178 struct drm_connector conn; 179 struct drm_encoder enc; 180 struct virtio_gpu_display_one info; 181 struct virtio_gpu_update_cursor cursor; 182 const struct drm_edid *drm_edid; 183 int cur_x; 184 int cur_y; 185 bool needs_modeset; 186 }; 187 #define drm_crtc_to_virtio_gpu_output(x) \ 188 container_of(x, struct virtio_gpu_output, crtc) 189 190 struct virtio_gpu_framebuffer { 191 struct drm_framebuffer base; 192 struct virtio_gpu_fence *fence; 193 }; 194 #define to_virtio_gpu_framebuffer(x) \ 195 container_of(x, struct virtio_gpu_framebuffer, base) 196 197 struct virtio_gpu_plane_state { 198 struct drm_plane_state base; 199 struct virtio_gpu_fence *fence; 200 }; 201 #define to_virtio_gpu_plane_state(x) \ 202 container_of(x, struct virtio_gpu_plane_state, base) 203 204 struct virtio_gpu_queue { 205 struct virtqueue *vq; 206 spinlock_t qlock; 207 wait_queue_head_t ack_queue; 208 struct work_struct dequeue_work; 209 uint32_t seqno; 210 }; 211 212 struct virtio_gpu_drv_capset { 213 uint32_t id; 214 uint32_t max_version; 215 uint32_t max_size; 216 }; 217 218 struct virtio_gpu_drv_cap_cache { 219 struct list_head head; 220 void *caps_cache; 221 uint32_t id; 222 uint32_t version; 223 uint32_t size; 224 atomic_t is_valid; 225 }; 226 227 struct virtio_gpu_device { 228 struct drm_device *ddev; 229 230 struct virtio_device *vdev; 231 232 struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS]; 233 uint32_t num_scanouts; 234 235 struct virtio_gpu_queue ctrlq; 236 struct virtio_gpu_queue cursorq; 237 struct kmem_cache *vbufs; 238 239 atomic_t pending_commands; 240 241 struct ida resource_ida; 242 243 wait_queue_head_t resp_wq; 244 /* current display info */ 245 spinlock_t display_info_lock; 246 bool display_info_pending; 247 248 struct virtio_gpu_fence_driver fence_drv; 249 250 struct ida ctx_id_ida; 251 252 bool has_virgl_3d; 253 bool has_edid; 254 bool has_indirect; 255 bool has_resource_assign_uuid; 256 bool has_resource_blob; 257 bool has_host_visible; 258 bool has_context_init; 259 struct virtio_shm_region host_visible_region; 260 struct drm_mm host_visible_mm; 261 262 struct work_struct config_changed_work; 263 264 struct work_struct obj_free_work; 265 spinlock_t obj_free_lock; 266 struct list_head obj_free_list; 267 268 struct virtio_gpu_drv_capset *capsets; 269 uint32_t num_capsets; 270 uint64_t capset_id_mask; 271 struct list_head cap_cache; 272 273 /* protects uuid state when exporting */ 274 spinlock_t resource_export_lock; 275 /* protects map state and host_visible_mm */ 276 spinlock_t host_visible_lock; 277 }; 278 279 struct virtio_gpu_fpriv { 280 uint32_t ctx_id; 281 uint32_t context_init; 282 bool context_created; 283 uint32_t num_rings; 284 uint64_t base_fence_ctx; 285 uint64_t ring_idx_mask; 286 struct mutex context_lock; 287 char debug_name[DEBUG_NAME_MAX_LEN]; 288 bool explicit_debug_name; 289 }; 290 291 /* virtgpu_ioctl.c */ 292 #define DRM_VIRTIO_NUM_IOCTLS 12 293 extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS]; 294 void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file); 295 296 /* virtgpu_kms.c */ 297 int virtio_gpu_init(struct virtio_device *vdev, struct drm_device *dev); 298 void virtio_gpu_deinit(struct drm_device *dev); 299 void virtio_gpu_release(struct drm_device *dev); 300 int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file); 301 void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file); 302 303 /* virtgpu_gem.c */ 304 int virtio_gpu_gem_object_open(struct drm_gem_object *obj, 305 struct drm_file *file); 306 void virtio_gpu_gem_object_close(struct drm_gem_object *obj, 307 struct drm_file *file); 308 int virtio_gpu_mode_dumb_create(struct drm_file *file_priv, 309 struct drm_device *dev, 310 struct drm_mode_create_dumb *args); 311 int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv, 312 struct drm_device *dev, 313 uint32_t handle, uint64_t *offset_p); 314 315 struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents); 316 struct virtio_gpu_object_array* 317 virtio_gpu_array_from_handles(struct drm_file *drm_file, u32 *handles, u32 nents); 318 void virtio_gpu_array_add_obj(struct virtio_gpu_object_array *objs, 319 struct drm_gem_object *obj); 320 int virtio_gpu_array_lock_resv(struct virtio_gpu_object_array *objs); 321 void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs); 322 void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs, 323 struct dma_fence *fence); 324 void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs); 325 void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev, 326 struct virtio_gpu_object_array *objs); 327 void virtio_gpu_array_put_free_work(struct work_struct *work); 328 329 /* virtgpu_vq.c */ 330 int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev); 331 void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev); 332 void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev, 333 struct virtio_gpu_object *bo, 334 struct virtio_gpu_object_params *params, 335 struct virtio_gpu_object_array *objs, 336 struct virtio_gpu_fence *fence); 337 void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev, 338 struct virtio_gpu_object *bo); 339 void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev, 340 uint64_t offset, 341 uint32_t width, uint32_t height, 342 uint32_t x, uint32_t y, 343 struct virtio_gpu_object_array *objs, 344 struct virtio_gpu_fence *fence); 345 void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev, 346 uint32_t resource_id, 347 uint32_t x, uint32_t y, 348 uint32_t width, uint32_t height, 349 struct virtio_gpu_object_array *objs, 350 struct virtio_gpu_fence *fence); 351 void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev, 352 uint32_t scanout_id, uint32_t resource_id, 353 uint32_t width, uint32_t height, 354 uint32_t x, uint32_t y); 355 void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev, 356 struct virtio_gpu_object *obj, 357 struct virtio_gpu_mem_entry *ents, 358 unsigned int nents); 359 void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev, 360 struct virtio_gpu_output *output); 361 int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev); 362 int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx); 363 int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev, 364 int idx, int version, 365 struct virtio_gpu_drv_cap_cache **cache_p); 366 int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev); 367 void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id, 368 uint32_t context_init, uint32_t nlen, 369 const char *name); 370 void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev, 371 uint32_t id); 372 void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev, 373 uint32_t ctx_id, 374 struct virtio_gpu_object_array *objs); 375 void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev, 376 uint32_t ctx_id, 377 struct virtio_gpu_object_array *objs); 378 void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev, 379 void *data, uint32_t data_size, 380 uint32_t ctx_id, 381 struct virtio_gpu_object_array *objs, 382 struct virtio_gpu_fence *fence); 383 void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev, 384 uint32_t ctx_id, 385 uint64_t offset, uint32_t level, 386 uint32_t stride, 387 uint32_t layer_stride, 388 struct drm_virtgpu_3d_box *box, 389 struct virtio_gpu_object_array *objs, 390 struct virtio_gpu_fence *fence); 391 void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev, 392 uint32_t ctx_id, 393 uint64_t offset, uint32_t level, 394 uint32_t stride, 395 uint32_t layer_stride, 396 struct drm_virtgpu_3d_box *box, 397 struct virtio_gpu_object_array *objs, 398 struct virtio_gpu_fence *fence); 399 void 400 virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev, 401 struct virtio_gpu_object *bo, 402 struct virtio_gpu_object_params *params, 403 struct virtio_gpu_object_array *objs, 404 struct virtio_gpu_fence *fence); 405 void virtio_gpu_ctrl_ack(struct virtqueue *vq); 406 void virtio_gpu_cursor_ack(struct virtqueue *vq); 407 void virtio_gpu_dequeue_ctrl_func(struct work_struct *work); 408 void virtio_gpu_dequeue_cursor_func(struct work_struct *work); 409 void virtio_gpu_notify(struct virtio_gpu_device *vgdev); 410 411 int 412 virtio_gpu_cmd_resource_assign_uuid(struct virtio_gpu_device *vgdev, 413 struct virtio_gpu_object_array *objs); 414 415 int virtio_gpu_cmd_map(struct virtio_gpu_device *vgdev, 416 struct virtio_gpu_object_array *objs, uint64_t offset); 417 418 void virtio_gpu_cmd_unmap(struct virtio_gpu_device *vgdev, 419 struct virtio_gpu_object *bo); 420 421 void 422 virtio_gpu_cmd_resource_create_blob(struct virtio_gpu_device *vgdev, 423 struct virtio_gpu_object *bo, 424 struct virtio_gpu_object_params *params, 425 struct virtio_gpu_mem_entry *ents, 426 uint32_t nents); 427 void 428 virtio_gpu_cmd_set_scanout_blob(struct virtio_gpu_device *vgdev, 429 uint32_t scanout_id, 430 struct virtio_gpu_object *bo, 431 struct drm_framebuffer *fb, 432 uint32_t width, uint32_t height, 433 uint32_t x, uint32_t y); 434 435 /* virtgpu_display.c */ 436 int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev); 437 void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev); 438 439 /* virtgpu_plane.c */ 440 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc); 441 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev, 442 enum drm_plane_type type, 443 int index); 444 445 /* virtgpu_fence.c */ 446 struct virtio_gpu_fence *virtio_gpu_fence_alloc(struct virtio_gpu_device *vgdev, 447 uint64_t base_fence_ctx, 448 uint32_t ring_idx); 449 void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev, 450 struct virtio_gpu_ctrl_hdr *cmd_hdr, 451 struct virtio_gpu_fence *fence); 452 void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev, 453 u64 fence_id); 454 455 /* virtgpu_object.c */ 456 void virtio_gpu_cleanup_object(struct virtio_gpu_object *bo); 457 struct drm_gem_object *virtio_gpu_create_object(struct drm_device *dev, 458 size_t size); 459 int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, 460 struct virtio_gpu_object_params *params, 461 struct virtio_gpu_object **bo_ptr, 462 struct virtio_gpu_fence *fence); 463 464 bool virtio_gpu_is_shmem(struct virtio_gpu_object *bo); 465 466 int virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev, 467 uint32_t *resid); 468 /* virtgpu_prime.c */ 469 int virtio_gpu_resource_assign_uuid(struct virtio_gpu_device *vgdev, 470 struct virtio_gpu_object *bo); 471 struct dma_buf *virtgpu_gem_prime_export(struct drm_gem_object *obj, 472 int flags); 473 struct drm_gem_object *virtgpu_gem_prime_import(struct drm_device *dev, 474 struct dma_buf *buf); 475 struct drm_gem_object *virtgpu_gem_prime_import_sg_table( 476 struct drm_device *dev, struct dma_buf_attachment *attach, 477 struct sg_table *sgt); 478 479 /* virtgpu_debugfs.c */ 480 void virtio_gpu_debugfs_init(struct drm_minor *minor); 481 482 /* virtgpu_vram.c */ 483 bool virtio_gpu_is_vram(struct virtio_gpu_object *bo); 484 int virtio_gpu_vram_create(struct virtio_gpu_device *vgdev, 485 struct virtio_gpu_object_params *params, 486 struct virtio_gpu_object **bo_ptr); 487 struct sg_table *virtio_gpu_vram_map_dma_buf(struct virtio_gpu_object *bo, 488 struct device *dev, 489 enum dma_data_direction dir); 490 void virtio_gpu_vram_unmap_dma_buf(struct device *dev, 491 struct sg_table *sgt, 492 enum dma_data_direction dir); 493 494 /* virtgpu_submit.c */ 495 int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data, 496 struct drm_file *file); 497 498 #endif 499