1 // SPDX-License-Identifier: GPL-2.0
2
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
4
5 #include <linux/interrupt.h>
6 #include <linux/dmar.h>
7 #include <linux/spinlock.h>
8 #include <linux/slab.h>
9 #include <linux/jiffies.h>
10 #include <linux/hpet.h>
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/acpi.h>
14 #include <linux/irqdomain.h>
15 #include <linux/crash_dump.h>
16 #include <asm/io_apic.h>
17 #include <asm/apic.h>
18 #include <asm/smp.h>
19 #include <asm/cpu.h>
20 #include <asm/irq_remapping.h>
21 #include <asm/pci-direct.h>
22 #include <asm/posted_intr.h>
23
24 #include "iommu.h"
25 #include "../irq_remapping.h"
26 #include "../iommu-pages.h"
27 #include "cap_audit.h"
28
29 struct ioapic_scope {
30 struct intel_iommu *iommu;
31 unsigned int id;
32 unsigned int bus; /* PCI bus number */
33 unsigned int devfn; /* PCI devfn number */
34 };
35
36 struct hpet_scope {
37 struct intel_iommu *iommu;
38 u8 id;
39 unsigned int bus;
40 unsigned int devfn;
41 };
42
43 struct irq_2_iommu {
44 struct intel_iommu *iommu;
45 u16 irte_index;
46 u16 sub_handle;
47 u8 irte_mask;
48 bool posted_msi;
49 bool posted_vcpu;
50 };
51
52 struct intel_ir_data {
53 struct irq_2_iommu irq_2_iommu;
54 struct irte irte_entry;
55 union {
56 struct msi_msg msi_entry;
57 };
58 };
59
60 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
61 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
62
63 static int __read_mostly eim_mode;
64 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
65 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
66
67 /*
68 * Lock ordering:
69 * ->dmar_global_lock
70 * ->irq_2_ir_lock
71 * ->qi->q_lock
72 * ->iommu->register_lock
73 * Note:
74 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
75 * in single-threaded environment with interrupt disabled, so no need to tabke
76 * the dmar_global_lock.
77 */
78 DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
79 static const struct irq_domain_ops intel_ir_domain_ops;
80
81 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
82 static int __init parse_ioapics_under_ir(void);
83 static const struct msi_parent_ops dmar_msi_parent_ops;
84
ir_pre_enabled(struct intel_iommu * iommu)85 static bool ir_pre_enabled(struct intel_iommu *iommu)
86 {
87 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
88 }
89
clear_ir_pre_enabled(struct intel_iommu * iommu)90 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
91 {
92 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
93 }
94
init_ir_status(struct intel_iommu * iommu)95 static void init_ir_status(struct intel_iommu *iommu)
96 {
97 u32 gsts;
98
99 gsts = readl(iommu->reg + DMAR_GSTS_REG);
100 if (gsts & DMA_GSTS_IRES)
101 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
102 }
103
alloc_irte(struct intel_iommu * iommu,struct irq_2_iommu * irq_iommu,u16 count)104 static int alloc_irte(struct intel_iommu *iommu,
105 struct irq_2_iommu *irq_iommu, u16 count)
106 {
107 struct ir_table *table = iommu->ir_table;
108 unsigned int mask = 0;
109 unsigned long flags;
110 int index;
111
112 if (!count || !irq_iommu)
113 return -1;
114
115 if (count > 1) {
116 count = __roundup_pow_of_two(count);
117 mask = ilog2(count);
118 }
119
120 if (mask > ecap_max_handle_mask(iommu->ecap)) {
121 pr_err("Requested mask %x exceeds the max invalidation handle"
122 " mask value %Lx\n", mask,
123 ecap_max_handle_mask(iommu->ecap));
124 return -1;
125 }
126
127 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
128 index = bitmap_find_free_region(table->bitmap,
129 INTR_REMAP_TABLE_ENTRIES, mask);
130 if (index < 0) {
131 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
132 } else {
133 irq_iommu->iommu = iommu;
134 irq_iommu->irte_index = index;
135 irq_iommu->sub_handle = 0;
136 irq_iommu->irte_mask = mask;
137 }
138 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
139
140 return index;
141 }
142
qi_flush_iec(struct intel_iommu * iommu,int index,int mask)143 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
144 {
145 struct qi_desc desc;
146
147 desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
148 | QI_IEC_SELECTIVE;
149 desc.qw1 = 0;
150 desc.qw2 = 0;
151 desc.qw3 = 0;
152
153 return qi_submit_sync(iommu, &desc, 1, 0);
154 }
155
modify_irte(struct irq_2_iommu * irq_iommu,struct irte * irte_modified)156 static int modify_irte(struct irq_2_iommu *irq_iommu,
157 struct irte *irte_modified)
158 {
159 struct intel_iommu *iommu;
160 unsigned long flags;
161 struct irte *irte;
162 int rc, index;
163
164 if (!irq_iommu)
165 return -1;
166
167 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
168
169 iommu = irq_iommu->iommu;
170
171 index = irq_iommu->irte_index + irq_iommu->sub_handle;
172 irte = &iommu->ir_table->base[index];
173
174 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
175 /*
176 * We use cmpxchg16 to atomically update the 128-bit IRTE,
177 * and it cannot be updated by the hardware or other processors
178 * behind us, so the return value of cmpxchg16 should be the
179 * same as the old value.
180 */
181 u128 old = irte->irte;
182 WARN_ON(!try_cmpxchg128(&irte->irte, &old, irte_modified->irte));
183 } else {
184 WRITE_ONCE(irte->low, irte_modified->low);
185 WRITE_ONCE(irte->high, irte_modified->high);
186 }
187 __iommu_flush_cache(iommu, irte, sizeof(*irte));
188
189 rc = qi_flush_iec(iommu, index, 0);
190
191 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
192
193 return rc;
194 }
195
map_hpet_to_iommu(u8 hpet_id)196 static struct intel_iommu *map_hpet_to_iommu(u8 hpet_id)
197 {
198 int i;
199
200 for (i = 0; i < MAX_HPET_TBS; i++) {
201 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
202 return ir_hpet[i].iommu;
203 }
204 return NULL;
205 }
206
map_ioapic_to_iommu(int apic)207 static struct intel_iommu *map_ioapic_to_iommu(int apic)
208 {
209 int i;
210
211 for (i = 0; i < MAX_IO_APICS; i++) {
212 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
213 return ir_ioapic[i].iommu;
214 }
215 return NULL;
216 }
217
map_dev_to_ir(struct pci_dev * dev)218 static struct irq_domain *map_dev_to_ir(struct pci_dev *dev)
219 {
220 struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev);
221
222 return drhd ? drhd->iommu->ir_domain : NULL;
223 }
224
clear_entries(struct irq_2_iommu * irq_iommu)225 static int clear_entries(struct irq_2_iommu *irq_iommu)
226 {
227 struct irte *start, *entry, *end;
228 struct intel_iommu *iommu;
229 int index;
230
231 if (irq_iommu->sub_handle)
232 return 0;
233
234 iommu = irq_iommu->iommu;
235 index = irq_iommu->irte_index;
236
237 start = iommu->ir_table->base + index;
238 end = start + (1 << irq_iommu->irte_mask);
239
240 for (entry = start; entry < end; entry++) {
241 WRITE_ONCE(entry->low, 0);
242 WRITE_ONCE(entry->high, 0);
243 }
244 bitmap_release_region(iommu->ir_table->bitmap, index,
245 irq_iommu->irte_mask);
246
247 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
248 }
249
250 /*
251 * source validation type
252 */
253 #define SVT_NO_VERIFY 0x0 /* no verification is required */
254 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
255 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
256
257 /*
258 * source-id qualifier
259 */
260 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
261 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
262 * the third least significant bit
263 */
264 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
265 * the second and third least significant bits
266 */
267 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
268 * the least three significant bits
269 */
270
271 /*
272 * set SVT, SQ and SID fields of irte to verify
273 * source ids of interrupt requests
274 */
set_irte_sid(struct irte * irte,unsigned int svt,unsigned int sq,unsigned int sid)275 static void set_irte_sid(struct irte *irte, unsigned int svt,
276 unsigned int sq, unsigned int sid)
277 {
278 if (disable_sourceid_checking)
279 svt = SVT_NO_VERIFY;
280 irte->svt = svt;
281 irte->sq = sq;
282 irte->sid = sid;
283 }
284
285 /*
286 * Set an IRTE to match only the bus number. Interrupt requests that reference
287 * this IRTE must have a requester-id whose bus number is between or equal
288 * to the start_bus and end_bus arguments.
289 */
set_irte_verify_bus(struct irte * irte,unsigned int start_bus,unsigned int end_bus)290 static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
291 unsigned int end_bus)
292 {
293 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
294 (start_bus << 8) | end_bus);
295 }
296
set_ioapic_sid(struct irte * irte,int apic)297 static int set_ioapic_sid(struct irte *irte, int apic)
298 {
299 int i;
300 u16 sid = 0;
301
302 if (!irte)
303 return -1;
304
305 for (i = 0; i < MAX_IO_APICS; i++) {
306 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
307 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
308 break;
309 }
310 }
311
312 if (sid == 0) {
313 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
314 return -1;
315 }
316
317 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
318
319 return 0;
320 }
321
set_hpet_sid(struct irte * irte,u8 id)322 static int set_hpet_sid(struct irte *irte, u8 id)
323 {
324 int i;
325 u16 sid = 0;
326
327 if (!irte)
328 return -1;
329
330 for (i = 0; i < MAX_HPET_TBS; i++) {
331 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
332 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
333 break;
334 }
335 }
336
337 if (sid == 0) {
338 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
339 return -1;
340 }
341
342 /*
343 * Should really use SQ_ALL_16. Some platforms are broken.
344 * While we figure out the right quirks for these broken platforms, use
345 * SQ_13_IGNORE_3 for now.
346 */
347 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
348
349 return 0;
350 }
351
352 struct set_msi_sid_data {
353 struct pci_dev *pdev;
354 u16 alias;
355 int count;
356 int busmatch_count;
357 };
358
set_msi_sid_cb(struct pci_dev * pdev,u16 alias,void * opaque)359 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
360 {
361 struct set_msi_sid_data *data = opaque;
362
363 if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias))
364 data->busmatch_count++;
365
366 data->pdev = pdev;
367 data->alias = alias;
368 data->count++;
369
370 return 0;
371 }
372
set_msi_sid(struct irte * irte,struct pci_dev * dev)373 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
374 {
375 struct set_msi_sid_data data;
376
377 if (!irte || !dev)
378 return -1;
379
380 data.count = 0;
381 data.busmatch_count = 0;
382 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
383
384 /*
385 * DMA alias provides us with a PCI device and alias. The only case
386 * where the it will return an alias on a different bus than the
387 * device is the case of a PCIe-to-PCI bridge, where the alias is for
388 * the subordinate bus. In this case we can only verify the bus.
389 *
390 * If there are multiple aliases, all with the same bus number,
391 * then all we can do is verify the bus. This is typical in NTB
392 * hardware which use proxy IDs where the device will generate traffic
393 * from multiple devfn numbers on the same bus.
394 *
395 * If the alias device is on a different bus than our source device
396 * then we have a topology based alias, use it.
397 *
398 * Otherwise, the alias is for a device DMA quirk and we cannot
399 * assume that MSI uses the same requester ID. Therefore use the
400 * original device.
401 */
402 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
403 set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
404 dev->bus->number);
405 else if (data.count >= 2 && data.busmatch_count == data.count)
406 set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
407 else if (data.pdev->bus->number != dev->bus->number)
408 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
409 else
410 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
411 pci_dev_id(dev));
412
413 return 0;
414 }
415
iommu_load_old_irte(struct intel_iommu * iommu)416 static int iommu_load_old_irte(struct intel_iommu *iommu)
417 {
418 struct irte *old_ir_table;
419 phys_addr_t irt_phys;
420 unsigned int i;
421 size_t size;
422 u64 irta;
423
424 /* Check whether the old ir-table has the same size as ours */
425 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
426 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
427 != INTR_REMAP_TABLE_REG_SIZE)
428 return -EINVAL;
429
430 irt_phys = irta & VTD_PAGE_MASK;
431 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
432
433 /* Map the old IR table */
434 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
435 if (!old_ir_table)
436 return -ENOMEM;
437
438 /* Copy data over */
439 memcpy(iommu->ir_table->base, old_ir_table, size);
440
441 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
442
443 /*
444 * Now check the table for used entries and mark those as
445 * allocated in the bitmap
446 */
447 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
448 if (iommu->ir_table->base[i].present)
449 bitmap_set(iommu->ir_table->bitmap, i, 1);
450 }
451
452 memunmap(old_ir_table);
453
454 return 0;
455 }
456
457
iommu_set_irq_remapping(struct intel_iommu * iommu,int mode)458 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
459 {
460 unsigned long flags;
461 u64 addr;
462 u32 sts;
463
464 addr = virt_to_phys((void *)iommu->ir_table->base);
465
466 raw_spin_lock_irqsave(&iommu->register_lock, flags);
467
468 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
469 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
470
471 /* Set interrupt-remapping table pointer */
472 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
473
474 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
475 readl, (sts & DMA_GSTS_IRTPS), sts);
476 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
477
478 /*
479 * Global invalidation of interrupt entry cache to make sure the
480 * hardware uses the new irq remapping table.
481 */
482 if (!cap_esirtps(iommu->cap))
483 qi_global_iec(iommu);
484 }
485
iommu_enable_irq_remapping(struct intel_iommu * iommu)486 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
487 {
488 unsigned long flags;
489 u32 sts;
490
491 raw_spin_lock_irqsave(&iommu->register_lock, flags);
492
493 /* Enable interrupt-remapping */
494 iommu->gcmd |= DMA_GCMD_IRE;
495 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
496 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
497 readl, (sts & DMA_GSTS_IRES), sts);
498
499 /* Block compatibility-format MSIs */
500 if (sts & DMA_GSTS_CFIS) {
501 iommu->gcmd &= ~DMA_GCMD_CFI;
502 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
503 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
504 readl, !(sts & DMA_GSTS_CFIS), sts);
505 }
506
507 /*
508 * With CFI clear in the Global Command register, we should be
509 * protected from dangerous (i.e. compatibility) interrupts
510 * regardless of x2apic status. Check just to be sure.
511 */
512 if (sts & DMA_GSTS_CFIS)
513 WARN(1, KERN_WARNING
514 "Compatibility-format IRQs enabled despite intr remapping;\n"
515 "you are vulnerable to IRQ injection.\n");
516
517 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
518 }
519
intel_setup_irq_remapping(struct intel_iommu * iommu)520 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
521 {
522 struct ir_table *ir_table;
523 struct fwnode_handle *fn;
524 unsigned long *bitmap;
525 void *ir_table_base;
526
527 if (iommu->ir_table)
528 return 0;
529
530 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
531 if (!ir_table)
532 return -ENOMEM;
533
534 ir_table_base = iommu_alloc_pages_node(iommu->node, GFP_KERNEL,
535 INTR_REMAP_PAGE_ORDER);
536 if (!ir_table_base) {
537 pr_err("IR%d: failed to allocate pages of order %d\n",
538 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
539 goto out_free_table;
540 }
541
542 bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_KERNEL);
543 if (bitmap == NULL) {
544 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
545 goto out_free_pages;
546 }
547
548 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
549 if (!fn)
550 goto out_free_bitmap;
551
552 iommu->ir_domain =
553 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
554 0, INTR_REMAP_TABLE_ENTRIES,
555 fn, &intel_ir_domain_ops,
556 iommu);
557 if (!iommu->ir_domain) {
558 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
559 goto out_free_fwnode;
560 }
561
562 irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_DMAR);
563 iommu->ir_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT |
564 IRQ_DOMAIN_FLAG_ISOLATED_MSI;
565 iommu->ir_domain->msi_parent_ops = &dmar_msi_parent_ops;
566
567 ir_table->base = ir_table_base;
568 ir_table->bitmap = bitmap;
569 iommu->ir_table = ir_table;
570
571 /*
572 * If the queued invalidation is already initialized,
573 * shouldn't disable it.
574 */
575 if (!iommu->qi) {
576 /*
577 * Clear previous faults.
578 */
579 dmar_fault(-1, iommu);
580 dmar_disable_qi(iommu);
581
582 if (dmar_enable_qi(iommu)) {
583 pr_err("Failed to enable queued invalidation\n");
584 goto out_free_ir_domain;
585 }
586 }
587
588 init_ir_status(iommu);
589
590 if (ir_pre_enabled(iommu)) {
591 if (!is_kdump_kernel()) {
592 pr_info_once("IRQ remapping was enabled on %s but we are not in kdump mode\n",
593 iommu->name);
594 clear_ir_pre_enabled(iommu);
595 iommu_disable_irq_remapping(iommu);
596 } else if (iommu_load_old_irte(iommu))
597 pr_err("Failed to copy IR table for %s from previous kernel\n",
598 iommu->name);
599 else
600 pr_info("Copied IR table for %s from previous kernel\n",
601 iommu->name);
602 }
603
604 iommu_set_irq_remapping(iommu, eim_mode);
605
606 return 0;
607
608 out_free_ir_domain:
609 irq_domain_remove(iommu->ir_domain);
610 iommu->ir_domain = NULL;
611 out_free_fwnode:
612 irq_domain_free_fwnode(fn);
613 out_free_bitmap:
614 bitmap_free(bitmap);
615 out_free_pages:
616 iommu_free_pages(ir_table_base, INTR_REMAP_PAGE_ORDER);
617 out_free_table:
618 kfree(ir_table);
619
620 iommu->ir_table = NULL;
621
622 return -ENOMEM;
623 }
624
intel_teardown_irq_remapping(struct intel_iommu * iommu)625 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
626 {
627 struct fwnode_handle *fn;
628
629 if (iommu && iommu->ir_table) {
630 if (iommu->ir_domain) {
631 fn = iommu->ir_domain->fwnode;
632
633 irq_domain_remove(iommu->ir_domain);
634 irq_domain_free_fwnode(fn);
635 iommu->ir_domain = NULL;
636 }
637 iommu_free_pages(iommu->ir_table->base, INTR_REMAP_PAGE_ORDER);
638 bitmap_free(iommu->ir_table->bitmap);
639 kfree(iommu->ir_table);
640 iommu->ir_table = NULL;
641 }
642 }
643
644 /*
645 * Disable Interrupt Remapping.
646 */
iommu_disable_irq_remapping(struct intel_iommu * iommu)647 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
648 {
649 unsigned long flags;
650 u32 sts;
651
652 if (!ecap_ir_support(iommu->ecap))
653 return;
654
655 /*
656 * global invalidation of interrupt entry cache before disabling
657 * interrupt-remapping.
658 */
659 if (!cap_esirtps(iommu->cap))
660 qi_global_iec(iommu);
661
662 raw_spin_lock_irqsave(&iommu->register_lock, flags);
663
664 sts = readl(iommu->reg + DMAR_GSTS_REG);
665 if (!(sts & DMA_GSTS_IRES))
666 goto end;
667
668 iommu->gcmd &= ~DMA_GCMD_IRE;
669 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
670
671 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
672 readl, !(sts & DMA_GSTS_IRES), sts);
673
674 end:
675 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
676 }
677
dmar_x2apic_optout(void)678 static int __init dmar_x2apic_optout(void)
679 {
680 struct acpi_table_dmar *dmar;
681 dmar = (struct acpi_table_dmar *)dmar_tbl;
682 if (!dmar || no_x2apic_optout)
683 return 0;
684 return dmar->flags & DMAR_X2APIC_OPT_OUT;
685 }
686
intel_cleanup_irq_remapping(void)687 static void __init intel_cleanup_irq_remapping(void)
688 {
689 struct dmar_drhd_unit *drhd;
690 struct intel_iommu *iommu;
691
692 for_each_iommu(iommu, drhd) {
693 if (ecap_ir_support(iommu->ecap)) {
694 iommu_disable_irq_remapping(iommu);
695 intel_teardown_irq_remapping(iommu);
696 }
697 }
698
699 if (x2apic_supported())
700 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
701 }
702
intel_prepare_irq_remapping(void)703 static int __init intel_prepare_irq_remapping(void)
704 {
705 struct dmar_drhd_unit *drhd;
706 struct intel_iommu *iommu;
707 int eim = 0;
708
709 if (irq_remap_broken) {
710 pr_warn("This system BIOS has enabled interrupt remapping\n"
711 "on a chipset that contains an erratum making that\n"
712 "feature unstable. To maintain system stability\n"
713 "interrupt remapping is being disabled. Please\n"
714 "contact your BIOS vendor for an update\n");
715 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
716 return -ENODEV;
717 }
718
719 if (dmar_table_init() < 0)
720 return -ENODEV;
721
722 if (intel_cap_audit(CAP_AUDIT_STATIC_IRQR, NULL))
723 return -ENODEV;
724
725 if (!dmar_ir_support())
726 return -ENODEV;
727
728 if (parse_ioapics_under_ir()) {
729 pr_info("Not enabling interrupt remapping\n");
730 goto error;
731 }
732
733 /* First make sure all IOMMUs support IRQ remapping */
734 for_each_iommu(iommu, drhd)
735 if (!ecap_ir_support(iommu->ecap))
736 goto error;
737
738 /* Detect remapping mode: lapic or x2apic */
739 if (x2apic_supported()) {
740 eim = !dmar_x2apic_optout();
741 if (!eim) {
742 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
743 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
744 }
745 }
746
747 for_each_iommu(iommu, drhd) {
748 if (eim && !ecap_eim_support(iommu->ecap)) {
749 pr_info("%s does not support EIM\n", iommu->name);
750 eim = 0;
751 }
752 }
753
754 eim_mode = eim;
755 if (eim)
756 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
757
758 /* Do the initializations early */
759 for_each_iommu(iommu, drhd) {
760 if (intel_setup_irq_remapping(iommu)) {
761 pr_err("Failed to setup irq remapping for %s\n",
762 iommu->name);
763 goto error;
764 }
765 }
766
767 return 0;
768
769 error:
770 intel_cleanup_irq_remapping();
771 return -ENODEV;
772 }
773
774 /*
775 * Set Posted-Interrupts capability.
776 */
set_irq_posting_cap(void)777 static inline void set_irq_posting_cap(void)
778 {
779 struct dmar_drhd_unit *drhd;
780 struct intel_iommu *iommu;
781
782 if (!disable_irq_post) {
783 /*
784 * If IRTE is in posted format, the 'pda' field goes across the
785 * 64-bit boundary, we need use cmpxchg16b to atomically update
786 * it. We only expose posted-interrupt when X86_FEATURE_CX16
787 * is supported. Actually, hardware platforms supporting PI
788 * should have X86_FEATURE_CX16 support, this has been confirmed
789 * with Intel hardware guys.
790 */
791 if (boot_cpu_has(X86_FEATURE_CX16))
792 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
793
794 for_each_iommu(iommu, drhd)
795 if (!cap_pi_support(iommu->cap)) {
796 intel_irq_remap_ops.capability &=
797 ~(1 << IRQ_POSTING_CAP);
798 break;
799 }
800 }
801 }
802
intel_enable_irq_remapping(void)803 static int __init intel_enable_irq_remapping(void)
804 {
805 struct dmar_drhd_unit *drhd;
806 struct intel_iommu *iommu;
807 bool setup = false;
808
809 /*
810 * Setup Interrupt-remapping for all the DRHD's now.
811 */
812 for_each_iommu(iommu, drhd) {
813 if (!ir_pre_enabled(iommu))
814 iommu_enable_irq_remapping(iommu);
815 setup = true;
816 }
817
818 if (!setup)
819 goto error;
820
821 irq_remapping_enabled = 1;
822
823 set_irq_posting_cap();
824
825 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
826
827 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
828
829 error:
830 intel_cleanup_irq_remapping();
831 return -1;
832 }
833
ir_parse_one_hpet_scope(struct acpi_dmar_device_scope * scope,struct intel_iommu * iommu,struct acpi_dmar_hardware_unit * drhd)834 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
835 struct intel_iommu *iommu,
836 struct acpi_dmar_hardware_unit *drhd)
837 {
838 struct acpi_dmar_pci_path *path;
839 u8 bus;
840 int count, free = -1;
841
842 bus = scope->bus;
843 path = (struct acpi_dmar_pci_path *)(scope + 1);
844 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
845 / sizeof(struct acpi_dmar_pci_path);
846
847 while (--count > 0) {
848 /*
849 * Access PCI directly due to the PCI
850 * subsystem isn't initialized yet.
851 */
852 bus = read_pci_config_byte(bus, path->device, path->function,
853 PCI_SECONDARY_BUS);
854 path++;
855 }
856
857 for (count = 0; count < MAX_HPET_TBS; count++) {
858 if (ir_hpet[count].iommu == iommu &&
859 ir_hpet[count].id == scope->enumeration_id)
860 return 0;
861 else if (ir_hpet[count].iommu == NULL && free == -1)
862 free = count;
863 }
864 if (free == -1) {
865 pr_warn("Exceeded Max HPET blocks\n");
866 return -ENOSPC;
867 }
868
869 ir_hpet[free].iommu = iommu;
870 ir_hpet[free].id = scope->enumeration_id;
871 ir_hpet[free].bus = bus;
872 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
873 pr_info("HPET id %d under DRHD base 0x%Lx\n",
874 scope->enumeration_id, drhd->address);
875
876 return 0;
877 }
878
ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope * scope,struct intel_iommu * iommu,struct acpi_dmar_hardware_unit * drhd)879 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
880 struct intel_iommu *iommu,
881 struct acpi_dmar_hardware_unit *drhd)
882 {
883 struct acpi_dmar_pci_path *path;
884 u8 bus;
885 int count, free = -1;
886
887 bus = scope->bus;
888 path = (struct acpi_dmar_pci_path *)(scope + 1);
889 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
890 / sizeof(struct acpi_dmar_pci_path);
891
892 while (--count > 0) {
893 /*
894 * Access PCI directly due to the PCI
895 * subsystem isn't initialized yet.
896 */
897 bus = read_pci_config_byte(bus, path->device, path->function,
898 PCI_SECONDARY_BUS);
899 path++;
900 }
901
902 for (count = 0; count < MAX_IO_APICS; count++) {
903 if (ir_ioapic[count].iommu == iommu &&
904 ir_ioapic[count].id == scope->enumeration_id)
905 return 0;
906 else if (ir_ioapic[count].iommu == NULL && free == -1)
907 free = count;
908 }
909 if (free == -1) {
910 pr_warn("Exceeded Max IO APICS\n");
911 return -ENOSPC;
912 }
913
914 ir_ioapic[free].bus = bus;
915 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
916 ir_ioapic[free].iommu = iommu;
917 ir_ioapic[free].id = scope->enumeration_id;
918 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
919 scope->enumeration_id, drhd->address, iommu->seq_id);
920
921 return 0;
922 }
923
ir_parse_ioapic_hpet_scope(struct acpi_dmar_header * header,struct intel_iommu * iommu)924 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
925 struct intel_iommu *iommu)
926 {
927 int ret = 0;
928 struct acpi_dmar_hardware_unit *drhd;
929 struct acpi_dmar_device_scope *scope;
930 void *start, *end;
931
932 drhd = (struct acpi_dmar_hardware_unit *)header;
933 start = (void *)(drhd + 1);
934 end = ((void *)drhd) + header->length;
935
936 while (start < end && ret == 0) {
937 scope = start;
938 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
939 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
940 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
941 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
942 start += scope->length;
943 }
944
945 return ret;
946 }
947
ir_remove_ioapic_hpet_scope(struct intel_iommu * iommu)948 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
949 {
950 int i;
951
952 for (i = 0; i < MAX_HPET_TBS; i++)
953 if (ir_hpet[i].iommu == iommu)
954 ir_hpet[i].iommu = NULL;
955
956 for (i = 0; i < MAX_IO_APICS; i++)
957 if (ir_ioapic[i].iommu == iommu)
958 ir_ioapic[i].iommu = NULL;
959 }
960
961 /*
962 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
963 * hardware unit.
964 */
parse_ioapics_under_ir(void)965 static int __init parse_ioapics_under_ir(void)
966 {
967 struct dmar_drhd_unit *drhd;
968 struct intel_iommu *iommu;
969 bool ir_supported = false;
970 int ioapic_idx;
971
972 for_each_iommu(iommu, drhd) {
973 int ret;
974
975 if (!ecap_ir_support(iommu->ecap))
976 continue;
977
978 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
979 if (ret)
980 return ret;
981
982 ir_supported = true;
983 }
984
985 if (!ir_supported)
986 return -ENODEV;
987
988 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
989 int ioapic_id = mpc_ioapic_id(ioapic_idx);
990 if (!map_ioapic_to_iommu(ioapic_id)) {
991 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
992 "interrupt remapping will be disabled\n",
993 ioapic_id);
994 return -1;
995 }
996 }
997
998 return 0;
999 }
1000
ir_dev_scope_init(void)1001 static int __init ir_dev_scope_init(void)
1002 {
1003 int ret;
1004
1005 if (!irq_remapping_enabled)
1006 return 0;
1007
1008 down_write(&dmar_global_lock);
1009 ret = dmar_dev_scope_init();
1010 up_write(&dmar_global_lock);
1011
1012 return ret;
1013 }
1014 rootfs_initcall(ir_dev_scope_init);
1015
disable_irq_remapping(void)1016 static void disable_irq_remapping(void)
1017 {
1018 struct dmar_drhd_unit *drhd;
1019 struct intel_iommu *iommu = NULL;
1020
1021 /*
1022 * Disable Interrupt-remapping for all the DRHD's now.
1023 */
1024 for_each_iommu(iommu, drhd) {
1025 if (!ecap_ir_support(iommu->ecap))
1026 continue;
1027
1028 iommu_disable_irq_remapping(iommu);
1029 }
1030
1031 /*
1032 * Clear Posted-Interrupts capability.
1033 */
1034 if (!disable_irq_post)
1035 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1036 }
1037
reenable_irq_remapping(int eim)1038 static int reenable_irq_remapping(int eim)
1039 {
1040 struct dmar_drhd_unit *drhd;
1041 bool setup = false;
1042 struct intel_iommu *iommu = NULL;
1043
1044 for_each_iommu(iommu, drhd)
1045 if (iommu->qi)
1046 dmar_reenable_qi(iommu);
1047
1048 /*
1049 * Setup Interrupt-remapping for all the DRHD's now.
1050 */
1051 for_each_iommu(iommu, drhd) {
1052 if (!ecap_ir_support(iommu->ecap))
1053 continue;
1054
1055 /* Set up interrupt remapping for iommu.*/
1056 iommu_set_irq_remapping(iommu, eim);
1057 iommu_enable_irq_remapping(iommu);
1058 setup = true;
1059 }
1060
1061 if (!setup)
1062 goto error;
1063
1064 set_irq_posting_cap();
1065
1066 return 0;
1067
1068 error:
1069 /*
1070 * handle error condition gracefully here!
1071 */
1072 return -1;
1073 }
1074
1075 /*
1076 * Store the MSI remapping domain pointer in the device if enabled.
1077 *
1078 * This is called from dmar_pci_bus_add_dev() so it works even when DMA
1079 * remapping is disabled. Only update the pointer if the device is not
1080 * already handled by a non default PCI/MSI interrupt domain. This protects
1081 * e.g. VMD devices.
1082 */
intel_irq_remap_add_device(struct dmar_pci_notify_info * info)1083 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info)
1084 {
1085 if (!irq_remapping_enabled || !pci_dev_has_default_msi_parent_domain(info->dev))
1086 return;
1087
1088 dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev));
1089 }
1090
prepare_irte(struct irte * irte,int vector,unsigned int dest)1091 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1092 {
1093 memset(irte, 0, sizeof(*irte));
1094
1095 irte->present = 1;
1096 irte->dst_mode = apic->dest_mode_logical;
1097 /*
1098 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1099 * actual level or edge trigger will be setup in the IO-APIC
1100 * RTE. This will help simplify level triggered irq migration.
1101 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1102 * irq migration in the presence of interrupt-remapping.
1103 */
1104 irte->trigger_mode = 0;
1105 irte->dlvry_mode = APIC_DELIVERY_MODE_FIXED;
1106 irte->vector = vector;
1107 irte->dest_id = IRTE_DEST(dest);
1108 irte->redir_hint = 1;
1109 }
1110
prepare_irte_posted(struct irte * irte)1111 static void prepare_irte_posted(struct irte *irte)
1112 {
1113 memset(irte, 0, sizeof(*irte));
1114
1115 irte->present = 1;
1116 irte->p_pst = 1;
1117 }
1118
1119 struct irq_remap_ops intel_irq_remap_ops = {
1120 .prepare = intel_prepare_irq_remapping,
1121 .enable = intel_enable_irq_remapping,
1122 .disable = disable_irq_remapping,
1123 .reenable = reenable_irq_remapping,
1124 .enable_faulting = enable_drhd_fault_handling,
1125 };
1126
1127 #ifdef CONFIG_X86_POSTED_MSI
1128
get_pi_desc_addr(struct irq_data * irqd)1129 static phys_addr_t get_pi_desc_addr(struct irq_data *irqd)
1130 {
1131 int cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
1132
1133 if (WARN_ON(cpu >= nr_cpu_ids))
1134 return 0;
1135
1136 return __pa(per_cpu_ptr(&posted_msi_pi_desc, cpu));
1137 }
1138
intel_ir_reconfigure_irte_posted(struct irq_data * irqd)1139 static void intel_ir_reconfigure_irte_posted(struct irq_data *irqd)
1140 {
1141 struct intel_ir_data *ir_data = irqd->chip_data;
1142 struct irte *irte = &ir_data->irte_entry;
1143 struct irte irte_pi;
1144 u64 pid_addr;
1145
1146 pid_addr = get_pi_desc_addr(irqd);
1147
1148 if (!pid_addr) {
1149 pr_warn("Failed to setup IRQ %d for posted mode", irqd->irq);
1150 return;
1151 }
1152
1153 memset(&irte_pi, 0, sizeof(irte_pi));
1154
1155 /* The shared IRTE already be set up as posted during alloc_irte */
1156 dmar_copy_shared_irte(&irte_pi, irte);
1157
1158 irte_pi.pda_l = (pid_addr >> (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1159 irte_pi.pda_h = (pid_addr >> 32) & ~(-1UL << PDA_HIGH_BIT);
1160
1161 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1162 }
1163
1164 #else
intel_ir_reconfigure_irte_posted(struct irq_data * irqd)1165 static inline void intel_ir_reconfigure_irte_posted(struct irq_data *irqd) {}
1166 #endif
1167
__intel_ir_reconfigure_irte(struct irq_data * irqd,bool force_host)1168 static void __intel_ir_reconfigure_irte(struct irq_data *irqd, bool force_host)
1169 {
1170 struct intel_ir_data *ir_data = irqd->chip_data;
1171
1172 /*
1173 * Don't modify IRTEs for IRQs that are being posted to vCPUs if the
1174 * host CPU affinity changes.
1175 */
1176 if (ir_data->irq_2_iommu.posted_vcpu && !force_host)
1177 return;
1178
1179 ir_data->irq_2_iommu.posted_vcpu = false;
1180
1181 if (ir_data->irq_2_iommu.posted_msi)
1182 intel_ir_reconfigure_irte_posted(irqd);
1183 else
1184 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1185 }
1186
intel_ir_reconfigure_irte(struct irq_data * irqd,bool force_host)1187 static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force_host)
1188 {
1189 struct intel_ir_data *ir_data = irqd->chip_data;
1190 struct irte *irte = &ir_data->irte_entry;
1191 struct irq_cfg *cfg = irqd_cfg(irqd);
1192
1193 /*
1194 * Atomically updates the IRTE with the new destination, vector
1195 * and flushes the interrupt entry cache.
1196 */
1197 irte->vector = cfg->vector;
1198 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1199
1200 __intel_ir_reconfigure_irte(irqd, force_host);
1201 }
1202
1203 /*
1204 * Migrate the IO-APIC irq in the presence of intr-remapping.
1205 *
1206 * For both level and edge triggered, irq migration is a simple atomic
1207 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1208 *
1209 * For level triggered, we eliminate the io-apic RTE modification (with the
1210 * updated vector information), by using a virtual vector (io-apic pin number).
1211 * Real vector that is used for interrupting cpu will be coming from
1212 * the interrupt-remapping table entry.
1213 *
1214 * As the migration is a simple atomic update of IRTE, the same mechanism
1215 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1216 */
1217 static int
intel_ir_set_affinity(struct irq_data * data,const struct cpumask * mask,bool force)1218 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1219 bool force)
1220 {
1221 struct irq_data *parent = data->parent_data;
1222 struct irq_cfg *cfg = irqd_cfg(data);
1223 int ret;
1224
1225 ret = parent->chip->irq_set_affinity(parent, mask, force);
1226 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1227 return ret;
1228
1229 intel_ir_reconfigure_irte(data, false);
1230 /*
1231 * After this point, all the interrupts will start arriving
1232 * at the new destination. So, time to cleanup the previous
1233 * vector allocation.
1234 */
1235 vector_schedule_cleanup(cfg);
1236
1237 return IRQ_SET_MASK_OK_DONE;
1238 }
1239
intel_ir_compose_msi_msg(struct irq_data * irq_data,struct msi_msg * msg)1240 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1241 struct msi_msg *msg)
1242 {
1243 struct intel_ir_data *ir_data = irq_data->chip_data;
1244
1245 *msg = ir_data->msi_entry;
1246 }
1247
intel_ir_set_vcpu_affinity(struct irq_data * data,void * info)1248 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1249 {
1250 struct intel_ir_data *ir_data = data->chip_data;
1251 struct vcpu_data *vcpu_pi_info = info;
1252
1253 /* stop posting interrupts, back to the default mode */
1254 if (!vcpu_pi_info) {
1255 __intel_ir_reconfigure_irte(data, true);
1256 } else {
1257 struct irte irte_pi;
1258
1259 /*
1260 * We are not caching the posted interrupt entry. We
1261 * copy the data from the remapped entry and modify
1262 * the fields which are relevant for posted mode. The
1263 * cached remapped entry is used for switching back to
1264 * remapped mode.
1265 */
1266 memset(&irte_pi, 0, sizeof(irte_pi));
1267 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1268
1269 /* Update the posted mode fields */
1270 irte_pi.p_pst = 1;
1271 irte_pi.p_urgent = 0;
1272 irte_pi.p_vector = vcpu_pi_info->vector;
1273 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1274 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1275 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1276 ~(-1UL << PDA_HIGH_BIT);
1277
1278 ir_data->irq_2_iommu.posted_vcpu = true;
1279 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1280 }
1281
1282 return 0;
1283 }
1284
1285 static struct irq_chip intel_ir_chip = {
1286 .name = "INTEL-IR",
1287 .irq_ack = apic_ack_irq,
1288 .irq_set_affinity = intel_ir_set_affinity,
1289 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1290 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1291 };
1292
1293 /*
1294 * With posted MSIs, the MSI vectors are multiplexed into a single notification
1295 * vector, and only the notification vector is sent to the APIC IRR. Device
1296 * MSIs are then dispatched in a demux loop that harvests the MSIs from the
1297 * CPU's Posted Interrupt Request bitmap. I.e. Posted MSIs never get sent to
1298 * the APIC IRR, and thus do not need an EOI. The notification handler instead
1299 * performs a single EOI after processing the PIR.
1300 *
1301 * Note! Pending SMP/CPU affinity changes, which are per MSI, must still be
1302 * honored, only the APIC EOI is omitted.
1303 *
1304 * For the example below, 3 MSIs are coalesced into one CPU notification. Only
1305 * one apic_eoi() is needed, but each MSI needs to process pending changes to
1306 * its CPU affinity.
1307 *
1308 * __sysvec_posted_msi_notification()
1309 * irq_enter();
1310 * handle_edge_irq()
1311 * irq_chip_ack_parent()
1312 * irq_move_irq(); // No EOI
1313 * handle_irq_event()
1314 * driver_handler()
1315 * handle_edge_irq()
1316 * irq_chip_ack_parent()
1317 * irq_move_irq(); // No EOI
1318 * handle_irq_event()
1319 * driver_handler()
1320 * handle_edge_irq()
1321 * irq_chip_ack_parent()
1322 * irq_move_irq(); // No EOI
1323 * handle_irq_event()
1324 * driver_handler()
1325 * apic_eoi()
1326 * irq_exit()
1327 *
1328 */
1329 static struct irq_chip intel_ir_chip_post_msi = {
1330 .name = "INTEL-IR-POST",
1331 .irq_ack = irq_move_irq,
1332 .irq_set_affinity = intel_ir_set_affinity,
1333 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1334 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1335 };
1336
fill_msi_msg(struct msi_msg * msg,u32 index,u32 subhandle)1337 static void fill_msi_msg(struct msi_msg *msg, u32 index, u32 subhandle)
1338 {
1339 memset(msg, 0, sizeof(*msg));
1340
1341 msg->arch_addr_lo.dmar_base_address = X86_MSI_BASE_ADDRESS_LOW;
1342 msg->arch_addr_lo.dmar_subhandle_valid = true;
1343 msg->arch_addr_lo.dmar_format = true;
1344 msg->arch_addr_lo.dmar_index_0_14 = index & 0x7FFF;
1345 msg->arch_addr_lo.dmar_index_15 = !!(index & 0x8000);
1346
1347 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
1348
1349 msg->arch_data.dmar_subhandle = subhandle;
1350 }
1351
intel_irq_remapping_prepare_irte(struct intel_ir_data * data,struct irq_cfg * irq_cfg,struct irq_alloc_info * info,int index,int sub_handle)1352 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1353 struct irq_cfg *irq_cfg,
1354 struct irq_alloc_info *info,
1355 int index, int sub_handle)
1356 {
1357 struct irte *irte = &data->irte_entry;
1358
1359 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1360
1361 switch (info->type) {
1362 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1363 /* Set source-id of interrupt request */
1364 set_ioapic_sid(irte, info->devid);
1365 apic_pr_verbose("IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1366 info->devid, irte->present, irte->fpd, irte->dst_mode,
1367 irte->redir_hint, irte->trigger_mode, irte->dlvry_mode,
1368 irte->avail, irte->vector, irte->dest_id, irte->sid,
1369 irte->sq, irte->svt);
1370 sub_handle = info->ioapic.pin;
1371 break;
1372 case X86_IRQ_ALLOC_TYPE_HPET:
1373 set_hpet_sid(irte, info->devid);
1374 break;
1375 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
1376 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
1377 if (posted_msi_supported()) {
1378 prepare_irte_posted(irte);
1379 data->irq_2_iommu.posted_msi = 1;
1380 }
1381
1382 set_msi_sid(irte,
1383 pci_real_dma_dev(msi_desc_to_pci_dev(info->desc)));
1384 break;
1385 default:
1386 BUG_ON(1);
1387 break;
1388 }
1389 fill_msi_msg(&data->msi_entry, index, sub_handle);
1390 }
1391
intel_free_irq_resources(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)1392 static void intel_free_irq_resources(struct irq_domain *domain,
1393 unsigned int virq, unsigned int nr_irqs)
1394 {
1395 struct irq_data *irq_data;
1396 struct intel_ir_data *data;
1397 struct irq_2_iommu *irq_iommu;
1398 unsigned long flags;
1399 int i;
1400 for (i = 0; i < nr_irqs; i++) {
1401 irq_data = irq_domain_get_irq_data(domain, virq + i);
1402 if (irq_data && irq_data->chip_data) {
1403 data = irq_data->chip_data;
1404 irq_iommu = &data->irq_2_iommu;
1405 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1406 clear_entries(irq_iommu);
1407 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1408 irq_domain_reset_irq_data(irq_data);
1409 kfree(data);
1410 }
1411 }
1412 }
1413
intel_irq_remapping_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)1414 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1415 unsigned int virq, unsigned int nr_irqs,
1416 void *arg)
1417 {
1418 struct intel_iommu *iommu = domain->host_data;
1419 struct irq_alloc_info *info = arg;
1420 struct intel_ir_data *data, *ird;
1421 struct irq_data *irq_data;
1422 struct irq_cfg *irq_cfg;
1423 int i, ret, index;
1424
1425 if (!info || !iommu)
1426 return -EINVAL;
1427 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI)
1428 return -EINVAL;
1429
1430 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1431 if (ret < 0)
1432 return ret;
1433
1434 ret = -ENOMEM;
1435 data = kzalloc(sizeof(*data), GFP_KERNEL);
1436 if (!data)
1437 goto out_free_parent;
1438
1439 index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs);
1440 if (index < 0) {
1441 pr_warn("Failed to allocate IRTE\n");
1442 kfree(data);
1443 goto out_free_parent;
1444 }
1445
1446 for (i = 0; i < nr_irqs; i++) {
1447 irq_data = irq_domain_get_irq_data(domain, virq + i);
1448 irq_cfg = irqd_cfg(irq_data);
1449 if (!irq_data || !irq_cfg) {
1450 if (!i)
1451 kfree(data);
1452 ret = -EINVAL;
1453 goto out_free_data;
1454 }
1455
1456 if (i > 0) {
1457 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1458 if (!ird)
1459 goto out_free_data;
1460 /* Initialize the common data */
1461 ird->irq_2_iommu = data->irq_2_iommu;
1462 ird->irq_2_iommu.sub_handle = i;
1463 } else {
1464 ird = data;
1465 }
1466
1467 irq_data->hwirq = (index << 16) + i;
1468 irq_data->chip_data = ird;
1469 if (posted_msi_supported() &&
1470 ((info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI) ||
1471 (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX)))
1472 irq_data->chip = &intel_ir_chip_post_msi;
1473 else
1474 irq_data->chip = &intel_ir_chip;
1475 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1476 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1477 }
1478 return 0;
1479
1480 out_free_data:
1481 intel_free_irq_resources(domain, virq, i);
1482 out_free_parent:
1483 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1484 return ret;
1485 }
1486
intel_irq_remapping_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)1487 static void intel_irq_remapping_free(struct irq_domain *domain,
1488 unsigned int virq, unsigned int nr_irqs)
1489 {
1490 intel_free_irq_resources(domain, virq, nr_irqs);
1491 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1492 }
1493
intel_irq_remapping_activate(struct irq_domain * domain,struct irq_data * irq_data,bool reserve)1494 static int intel_irq_remapping_activate(struct irq_domain *domain,
1495 struct irq_data *irq_data, bool reserve)
1496 {
1497 intel_ir_reconfigure_irte(irq_data, true);
1498 return 0;
1499 }
1500
intel_irq_remapping_deactivate(struct irq_domain * domain,struct irq_data * irq_data)1501 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1502 struct irq_data *irq_data)
1503 {
1504 struct intel_ir_data *data = irq_data->chip_data;
1505 struct irte entry;
1506
1507 WARN_ON_ONCE(data->irq_2_iommu.posted_vcpu);
1508 data->irq_2_iommu.posted_vcpu = false;
1509
1510 memset(&entry, 0, sizeof(entry));
1511 modify_irte(&data->irq_2_iommu, &entry);
1512 }
1513
intel_irq_remapping_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)1514 static int intel_irq_remapping_select(struct irq_domain *d,
1515 struct irq_fwspec *fwspec,
1516 enum irq_domain_bus_token bus_token)
1517 {
1518 struct intel_iommu *iommu = NULL;
1519
1520 if (x86_fwspec_is_ioapic(fwspec))
1521 iommu = map_ioapic_to_iommu(fwspec->param[0]);
1522 else if (x86_fwspec_is_hpet(fwspec))
1523 iommu = map_hpet_to_iommu(fwspec->param[0]);
1524
1525 return iommu && d == iommu->ir_domain;
1526 }
1527
1528 static const struct irq_domain_ops intel_ir_domain_ops = {
1529 .select = intel_irq_remapping_select,
1530 .alloc = intel_irq_remapping_alloc,
1531 .free = intel_irq_remapping_free,
1532 .activate = intel_irq_remapping_activate,
1533 .deactivate = intel_irq_remapping_deactivate,
1534 };
1535
1536 static const struct msi_parent_ops dmar_msi_parent_ops = {
1537 .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED | MSI_FLAG_MULTI_PCI_MSI,
1538 .prefix = "IR-",
1539 .init_dev_msi_info = msi_parent_init_dev_msi_info,
1540 };
1541
1542 /*
1543 * Support of Interrupt Remapping Unit Hotplug
1544 */
dmar_ir_add(struct dmar_drhd_unit * dmaru,struct intel_iommu * iommu)1545 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1546 {
1547 int ret;
1548 int eim = x2apic_enabled();
1549
1550 ret = intel_cap_audit(CAP_AUDIT_HOTPLUG_IRQR, iommu);
1551 if (ret)
1552 return ret;
1553
1554 if (eim && !ecap_eim_support(iommu->ecap)) {
1555 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1556 iommu->reg_phys, iommu->ecap);
1557 return -ENODEV;
1558 }
1559
1560 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1561 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1562 iommu->reg_phys);
1563 return -ENODEV;
1564 }
1565
1566 /* TODO: check all IOAPICs are covered by IOMMU */
1567
1568 /* Setup Interrupt-remapping now. */
1569 ret = intel_setup_irq_remapping(iommu);
1570 if (ret) {
1571 pr_err("Failed to setup irq remapping for %s\n",
1572 iommu->name);
1573 intel_teardown_irq_remapping(iommu);
1574 ir_remove_ioapic_hpet_scope(iommu);
1575 } else {
1576 iommu_enable_irq_remapping(iommu);
1577 }
1578
1579 return ret;
1580 }
1581
dmar_ir_hotplug(struct dmar_drhd_unit * dmaru,bool insert)1582 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1583 {
1584 int ret = 0;
1585 struct intel_iommu *iommu = dmaru->iommu;
1586
1587 if (!irq_remapping_enabled)
1588 return 0;
1589 if (iommu == NULL)
1590 return -EINVAL;
1591 if (!ecap_ir_support(iommu->ecap))
1592 return 0;
1593 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1594 !cap_pi_support(iommu->cap))
1595 return -EBUSY;
1596
1597 if (insert) {
1598 if (!iommu->ir_table)
1599 ret = dmar_ir_add(dmaru, iommu);
1600 } else {
1601 if (iommu->ir_table) {
1602 if (!bitmap_empty(iommu->ir_table->bitmap,
1603 INTR_REMAP_TABLE_ENTRIES)) {
1604 ret = -EBUSY;
1605 } else {
1606 iommu_disable_irq_remapping(iommu);
1607 intel_teardown_irq_remapping(iommu);
1608 ir_remove_ioapic_hpet_scope(iommu);
1609 }
1610 }
1611 }
1612
1613 return ret;
1614 }
1615