1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4 #include <linux/avf/virtchnl.h>
5 #include <linux/bitfield.h>
6 #include <linux/delay.h>
7 #include <linux/etherdevice.h>
8 #include <linux/pci.h>
9 #include "i40e_adminq_cmd.h"
10 #include "i40e_devids.h"
11 #include "i40e_prototype.h"
12 #include "i40e_register.h"
13
14 /**
15 * i40e_set_mac_type - Sets MAC type
16 * @hw: pointer to the HW structure
17 *
18 * This function sets the mac type of the adapter based on the
19 * vendor ID and device ID stored in the hw structure.
20 **/
i40e_set_mac_type(struct i40e_hw * hw)21 int i40e_set_mac_type(struct i40e_hw *hw)
22 {
23 int status = 0;
24
25 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
26 switch (hw->device_id) {
27 case I40E_DEV_ID_SFP_XL710:
28 case I40E_DEV_ID_QEMU:
29 case I40E_DEV_ID_KX_B:
30 case I40E_DEV_ID_KX_C:
31 case I40E_DEV_ID_QSFP_A:
32 case I40E_DEV_ID_QSFP_B:
33 case I40E_DEV_ID_QSFP_C:
34 case I40E_DEV_ID_1G_BASE_T_BC:
35 case I40E_DEV_ID_5G_BASE_T_BC:
36 case I40E_DEV_ID_10G_BASE_T:
37 case I40E_DEV_ID_10G_BASE_T4:
38 case I40E_DEV_ID_10G_BASE_T_BC:
39 case I40E_DEV_ID_10G_B:
40 case I40E_DEV_ID_10G_SFP:
41 case I40E_DEV_ID_20G_KR2:
42 case I40E_DEV_ID_20G_KR2_A:
43 case I40E_DEV_ID_25G_B:
44 case I40E_DEV_ID_25G_SFP28:
45 case I40E_DEV_ID_X710_N3000:
46 case I40E_DEV_ID_XXV710_N3000:
47 hw->mac.type = I40E_MAC_XL710;
48 break;
49 case I40E_DEV_ID_KX_X722:
50 case I40E_DEV_ID_QSFP_X722:
51 case I40E_DEV_ID_SFP_X722:
52 case I40E_DEV_ID_1G_BASE_T_X722:
53 case I40E_DEV_ID_10G_BASE_T_X722:
54 case I40E_DEV_ID_SFP_I_X722:
55 case I40E_DEV_ID_SFP_X722_A:
56 hw->mac.type = I40E_MAC_X722;
57 break;
58 default:
59 hw->mac.type = I40E_MAC_GENERIC;
60 break;
61 }
62 } else {
63 status = -ENODEV;
64 }
65
66 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
67 hw->mac.type, status);
68 return status;
69 }
70
71 /**
72 * i40e_aq_str - convert AQ err code to a string
73 * @hw: pointer to the HW structure
74 * @aq_err: the AQ error code to convert
75 **/
i40e_aq_str(struct i40e_hw * hw,enum i40e_admin_queue_err aq_err)76 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
77 {
78 switch (aq_err) {
79 case I40E_AQ_RC_OK:
80 return "OK";
81 case I40E_AQ_RC_EPERM:
82 return "I40E_AQ_RC_EPERM";
83 case I40E_AQ_RC_ENOENT:
84 return "I40E_AQ_RC_ENOENT";
85 case I40E_AQ_RC_ESRCH:
86 return "I40E_AQ_RC_ESRCH";
87 case I40E_AQ_RC_EINTR:
88 return "I40E_AQ_RC_EINTR";
89 case I40E_AQ_RC_EIO:
90 return "I40E_AQ_RC_EIO";
91 case I40E_AQ_RC_ENXIO:
92 return "I40E_AQ_RC_ENXIO";
93 case I40E_AQ_RC_E2BIG:
94 return "I40E_AQ_RC_E2BIG";
95 case I40E_AQ_RC_EAGAIN:
96 return "I40E_AQ_RC_EAGAIN";
97 case I40E_AQ_RC_ENOMEM:
98 return "I40E_AQ_RC_ENOMEM";
99 case I40E_AQ_RC_EACCES:
100 return "I40E_AQ_RC_EACCES";
101 case I40E_AQ_RC_EFAULT:
102 return "I40E_AQ_RC_EFAULT";
103 case I40E_AQ_RC_EBUSY:
104 return "I40E_AQ_RC_EBUSY";
105 case I40E_AQ_RC_EEXIST:
106 return "I40E_AQ_RC_EEXIST";
107 case I40E_AQ_RC_EINVAL:
108 return "I40E_AQ_RC_EINVAL";
109 case I40E_AQ_RC_ENOTTY:
110 return "I40E_AQ_RC_ENOTTY";
111 case I40E_AQ_RC_ENOSPC:
112 return "I40E_AQ_RC_ENOSPC";
113 case I40E_AQ_RC_ENOSYS:
114 return "I40E_AQ_RC_ENOSYS";
115 case I40E_AQ_RC_ERANGE:
116 return "I40E_AQ_RC_ERANGE";
117 case I40E_AQ_RC_EFLUSHED:
118 return "I40E_AQ_RC_EFLUSHED";
119 case I40E_AQ_RC_BAD_ADDR:
120 return "I40E_AQ_RC_BAD_ADDR";
121 case I40E_AQ_RC_EMODE:
122 return "I40E_AQ_RC_EMODE";
123 case I40E_AQ_RC_EFBIG:
124 return "I40E_AQ_RC_EFBIG";
125 }
126
127 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
128 return hw->err_str;
129 }
130
131 /**
132 * i40e_debug_aq
133 * @hw: debug mask related to admin queue
134 * @mask: debug mask
135 * @desc: pointer to admin queue descriptor
136 * @buffer: pointer to command buffer
137 * @buf_len: max length of buffer
138 *
139 * Dumps debug log about adminq command with descriptor contents.
140 **/
i40e_debug_aq(struct i40e_hw * hw,enum i40e_debug_mask mask,void * desc,void * buffer,u16 buf_len)141 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
142 void *buffer, u16 buf_len)
143 {
144 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
145 u32 effective_mask = hw->debug_mask & mask;
146 char prefix[27];
147 u16 len;
148 u8 *buf = (u8 *)buffer;
149
150 if (!effective_mask || !desc)
151 return;
152
153 len = le16_to_cpu(aq_desc->datalen);
154
155 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
156 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
157 le16_to_cpu(aq_desc->opcode),
158 le16_to_cpu(aq_desc->flags),
159 le16_to_cpu(aq_desc->datalen),
160 le16_to_cpu(aq_desc->retval));
161 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
162 "\tcookie (h,l) 0x%08X 0x%08X\n",
163 le32_to_cpu(aq_desc->cookie_high),
164 le32_to_cpu(aq_desc->cookie_low));
165 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
166 "\tparam (0,1) 0x%08X 0x%08X\n",
167 le32_to_cpu(aq_desc->params.internal.param0),
168 le32_to_cpu(aq_desc->params.internal.param1));
169 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
170 "\taddr (h,l) 0x%08X 0x%08X\n",
171 le32_to_cpu(aq_desc->params.external.addr_high),
172 le32_to_cpu(aq_desc->params.external.addr_low));
173
174 if (buffer && buf_len != 0 && len != 0 &&
175 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
176 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
177 if (buf_len < len)
178 len = buf_len;
179
180 snprintf(prefix, sizeof(prefix),
181 "i40e %02x:%02x.%x: \t0x",
182 hw->bus.bus_id,
183 hw->bus.device,
184 hw->bus.func);
185
186 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
187 16, 1, buf, len, false);
188 }
189 }
190
191 /**
192 * i40e_check_asq_alive
193 * @hw: pointer to the hw struct
194 *
195 * Returns true if Queue is enabled else false.
196 **/
i40e_check_asq_alive(struct i40e_hw * hw)197 bool i40e_check_asq_alive(struct i40e_hw *hw)
198 {
199 /* Check if the queue is initialized */
200 if (!hw->aq.asq.count)
201 return false;
202
203 return !!(rd32(hw, I40E_PF_ATQLEN) & I40E_PF_ATQLEN_ATQENABLE_MASK);
204 }
205
206 /**
207 * i40e_aq_queue_shutdown
208 * @hw: pointer to the hw struct
209 * @unloading: is the driver unloading itself
210 *
211 * Tell the Firmware that we're shutting down the AdminQ and whether
212 * or not the driver is unloading as well.
213 **/
i40e_aq_queue_shutdown(struct i40e_hw * hw,bool unloading)214 int i40e_aq_queue_shutdown(struct i40e_hw *hw,
215 bool unloading)
216 {
217 struct i40e_aq_desc desc;
218 struct i40e_aqc_queue_shutdown *cmd =
219 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
220 int status;
221
222 i40e_fill_default_direct_cmd_desc(&desc,
223 i40e_aqc_opc_queue_shutdown);
224
225 if (unloading)
226 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
227 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
228
229 return status;
230 }
231
232 /**
233 * i40e_aq_get_set_rss_lut
234 * @hw: pointer to the hardware structure
235 * @vsi_id: vsi fw index
236 * @pf_lut: for PF table set true, for VSI table set false
237 * @lut: pointer to the lut buffer provided by the caller
238 * @lut_size: size of the lut buffer
239 * @set: set true to set the table, false to get the table
240 *
241 * Internal function to get or set RSS look up table
242 **/
i40e_aq_get_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size,bool set)243 static int i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
244 u16 vsi_id, bool pf_lut,
245 u8 *lut, u16 lut_size,
246 bool set)
247 {
248 struct i40e_aq_desc desc;
249 struct i40e_aqc_get_set_rss_lut *cmd_resp =
250 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
251 int status;
252 u16 flags;
253
254 if (set)
255 i40e_fill_default_direct_cmd_desc(&desc,
256 i40e_aqc_opc_set_rss_lut);
257 else
258 i40e_fill_default_direct_cmd_desc(&desc,
259 i40e_aqc_opc_get_rss_lut);
260
261 /* Indirect command */
262 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
263 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
264
265 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_ID_MASK, vsi_id) |
266 FIELD_PREP(I40E_AQC_SET_RSS_LUT_VSI_VALID, 1);
267 cmd_resp->vsi_id = cpu_to_le16(vsi_id);
268
269 if (pf_lut)
270 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK,
271 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF);
272 else
273 flags = FIELD_PREP(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK,
274 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI);
275
276 cmd_resp->flags = cpu_to_le16(flags);
277 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
278
279 return status;
280 }
281
282 /**
283 * i40e_aq_get_rss_lut
284 * @hw: pointer to the hardware structure
285 * @vsi_id: vsi fw index
286 * @pf_lut: for PF table set true, for VSI table set false
287 * @lut: pointer to the lut buffer provided by the caller
288 * @lut_size: size of the lut buffer
289 *
290 * get the RSS lookup table, PF or VSI type
291 **/
i40e_aq_get_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)292 int i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
293 bool pf_lut, u8 *lut, u16 lut_size)
294 {
295 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
296 false);
297 }
298
299 /**
300 * i40e_aq_set_rss_lut
301 * @hw: pointer to the hardware structure
302 * @vsi_id: vsi fw index
303 * @pf_lut: for PF table set true, for VSI table set false
304 * @lut: pointer to the lut buffer provided by the caller
305 * @lut_size: size of the lut buffer
306 *
307 * set the RSS lookup table, PF or VSI type
308 **/
i40e_aq_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)309 int i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
310 bool pf_lut, u8 *lut, u16 lut_size)
311 {
312 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
313 }
314
315 /**
316 * i40e_aq_get_set_rss_key
317 * @hw: pointer to the hw struct
318 * @vsi_id: vsi fw index
319 * @key: pointer to key info struct
320 * @set: set true to set the key, false to get the key
321 *
322 * get the RSS key per VSI
323 **/
i40e_aq_get_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key,bool set)324 static int i40e_aq_get_set_rss_key(struct i40e_hw *hw,
325 u16 vsi_id,
326 struct i40e_aqc_get_set_rss_key_data *key,
327 bool set)
328 {
329 struct i40e_aq_desc desc;
330 struct i40e_aqc_get_set_rss_key *cmd_resp =
331 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
332 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
333 int status;
334
335 if (set)
336 i40e_fill_default_direct_cmd_desc(&desc,
337 i40e_aqc_opc_set_rss_key);
338 else
339 i40e_fill_default_direct_cmd_desc(&desc,
340 i40e_aqc_opc_get_rss_key);
341
342 /* Indirect command */
343 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
344 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
345
346 vsi_id = FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_ID_MASK, vsi_id) |
347 FIELD_PREP(I40E_AQC_SET_RSS_KEY_VSI_VALID, 1);
348 cmd_resp->vsi_id = cpu_to_le16(vsi_id);
349
350 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
351
352 return status;
353 }
354
355 /**
356 * i40e_aq_get_rss_key
357 * @hw: pointer to the hw struct
358 * @vsi_id: vsi fw index
359 * @key: pointer to key info struct
360 *
361 **/
i40e_aq_get_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)362 int i40e_aq_get_rss_key(struct i40e_hw *hw,
363 u16 vsi_id,
364 struct i40e_aqc_get_set_rss_key_data *key)
365 {
366 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
367 }
368
369 /**
370 * i40e_aq_set_rss_key
371 * @hw: pointer to the hw struct
372 * @vsi_id: vsi fw index
373 * @key: pointer to key info struct
374 *
375 * set the RSS key per VSI
376 **/
i40e_aq_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)377 int i40e_aq_set_rss_key(struct i40e_hw *hw,
378 u16 vsi_id,
379 struct i40e_aqc_get_set_rss_key_data *key)
380 {
381 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
382 }
383
384 /**
385 * i40e_init_shared_code - Initialize the shared code
386 * @hw: pointer to hardware structure
387 *
388 * This assigns the MAC type and PHY code and inits the NVM.
389 * Does not touch the hardware. This function must be called prior to any
390 * other function in the shared code. The i40e_hw structure should be
391 * memset to 0 prior to calling this function. The following fields in
392 * hw structure should be filled in prior to calling this function:
393 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
394 * subsystem_vendor_id, and revision_id
395 **/
i40e_init_shared_code(struct i40e_hw * hw)396 int i40e_init_shared_code(struct i40e_hw *hw)
397 {
398 u32 port, ari, func_rid;
399 int status = 0;
400
401 i40e_set_mac_type(hw);
402
403 switch (hw->mac.type) {
404 case I40E_MAC_XL710:
405 case I40E_MAC_X722:
406 break;
407 default:
408 return -ENODEV;
409 }
410
411 hw->phy.get_link_info = true;
412
413 /* Determine port number and PF number*/
414 port = FIELD_GET(I40E_PFGEN_PORTNUM_PORT_NUM_MASK,
415 rd32(hw, I40E_PFGEN_PORTNUM));
416 hw->port = (u8)port;
417 ari = FIELD_GET(I40E_GLPCI_CAPSUP_ARI_EN_MASK,
418 rd32(hw, I40E_GLPCI_CAPSUP));
419 func_rid = rd32(hw, I40E_PF_FUNC_RID);
420 if (ari)
421 hw->pf_id = (u8)(func_rid & 0xff);
422 else
423 hw->pf_id = (u8)(func_rid & 0x7);
424
425 status = i40e_init_nvm(hw);
426 return status;
427 }
428
429 /**
430 * i40e_aq_mac_address_read - Retrieve the MAC addresses
431 * @hw: pointer to the hw struct
432 * @flags: a return indicator of what addresses were added to the addr store
433 * @addrs: the requestor's mac addr store
434 * @cmd_details: pointer to command details structure or NULL
435 **/
436 static int
i40e_aq_mac_address_read(struct i40e_hw * hw,u16 * flags,struct i40e_aqc_mac_address_read_data * addrs,struct i40e_asq_cmd_details * cmd_details)437 i40e_aq_mac_address_read(struct i40e_hw *hw,
438 u16 *flags,
439 struct i40e_aqc_mac_address_read_data *addrs,
440 struct i40e_asq_cmd_details *cmd_details)
441 {
442 struct i40e_aq_desc desc;
443 struct i40e_aqc_mac_address_read *cmd_data =
444 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
445 int status;
446
447 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
448 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
449
450 status = i40e_asq_send_command(hw, &desc, addrs,
451 sizeof(*addrs), cmd_details);
452 *flags = le16_to_cpu(cmd_data->command_flags);
453
454 return status;
455 }
456
457 /**
458 * i40e_aq_mac_address_write - Change the MAC addresses
459 * @hw: pointer to the hw struct
460 * @flags: indicates which MAC to be written
461 * @mac_addr: address to write
462 * @cmd_details: pointer to command details structure or NULL
463 **/
i40e_aq_mac_address_write(struct i40e_hw * hw,u16 flags,u8 * mac_addr,struct i40e_asq_cmd_details * cmd_details)464 int i40e_aq_mac_address_write(struct i40e_hw *hw,
465 u16 flags, u8 *mac_addr,
466 struct i40e_asq_cmd_details *cmd_details)
467 {
468 struct i40e_aq_desc desc;
469 struct i40e_aqc_mac_address_write *cmd_data =
470 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
471 int status;
472
473 i40e_fill_default_direct_cmd_desc(&desc,
474 i40e_aqc_opc_mac_address_write);
475 cmd_data->command_flags = cpu_to_le16(flags);
476 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
477 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
478 ((u32)mac_addr[3] << 16) |
479 ((u32)mac_addr[4] << 8) |
480 mac_addr[5]);
481
482 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
483
484 return status;
485 }
486
487 /**
488 * i40e_get_mac_addr - get MAC address
489 * @hw: pointer to the HW structure
490 * @mac_addr: pointer to MAC address
491 *
492 * Reads the adapter's MAC address from register
493 **/
i40e_get_mac_addr(struct i40e_hw * hw,u8 * mac_addr)494 int i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
495 {
496 struct i40e_aqc_mac_address_read_data addrs;
497 u16 flags = 0;
498 int status;
499
500 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
501
502 if (flags & I40E_AQC_LAN_ADDR_VALID)
503 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
504
505 return status;
506 }
507
508 /**
509 * i40e_get_port_mac_addr - get Port MAC address
510 * @hw: pointer to the HW structure
511 * @mac_addr: pointer to Port MAC address
512 *
513 * Reads the adapter's Port MAC address
514 **/
i40e_get_port_mac_addr(struct i40e_hw * hw,u8 * mac_addr)515 int i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
516 {
517 struct i40e_aqc_mac_address_read_data addrs;
518 u16 flags = 0;
519 int status;
520
521 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
522 if (status)
523 return status;
524
525 if (flags & I40E_AQC_PORT_ADDR_VALID)
526 ether_addr_copy(mac_addr, addrs.port_mac);
527 else
528 status = -EINVAL;
529
530 return status;
531 }
532
533 /**
534 * i40e_pre_tx_queue_cfg - pre tx queue configure
535 * @hw: pointer to the HW structure
536 * @queue: target PF queue index
537 * @enable: state change request
538 *
539 * Handles hw requirement to indicate intention to enable
540 * or disable target queue.
541 **/
i40e_pre_tx_queue_cfg(struct i40e_hw * hw,u32 queue,bool enable)542 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
543 {
544 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
545 u32 reg_block = 0;
546 u32 reg_val;
547
548 if (abs_queue_idx >= 128) {
549 reg_block = abs_queue_idx / 128;
550 abs_queue_idx %= 128;
551 }
552
553 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
554 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
555 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
556
557 if (enable)
558 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
559 else
560 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
561
562 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
563 }
564
565 /**
566 * i40e_get_pba_string - Reads part number string from EEPROM
567 * @hw: pointer to hardware structure
568 *
569 * Reads the part number string from the EEPROM and stores it
570 * into newly allocated buffer and saves resulting pointer
571 * to i40e_hw->pba_id field.
572 **/
i40e_get_pba_string(struct i40e_hw * hw)573 void i40e_get_pba_string(struct i40e_hw *hw)
574 {
575 #define I40E_NVM_PBA_FLAGS_BLK_PRESENT 0xFAFA
576 u16 pba_word = 0;
577 u16 pba_size = 0;
578 u16 pba_ptr = 0;
579 int status;
580 char *ptr;
581 u16 i;
582
583 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
584 if (status) {
585 hw_dbg(hw, "Failed to read PBA flags.\n");
586 return;
587 }
588 if (pba_word != I40E_NVM_PBA_FLAGS_BLK_PRESENT) {
589 hw_dbg(hw, "PBA block is not present.\n");
590 return;
591 }
592
593 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
594 if (status) {
595 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
596 return;
597 }
598
599 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
600 if (status) {
601 hw_dbg(hw, "Failed to read PBA Block size.\n");
602 return;
603 }
604
605 /* Subtract one to get PBA word count (PBA Size word is included in
606 * total size) and advance pointer to first PBA word.
607 */
608 pba_size--;
609 pba_ptr++;
610 if (!pba_size) {
611 hw_dbg(hw, "PBA ID is empty.\n");
612 return;
613 }
614
615 ptr = devm_kzalloc(i40e_hw_to_dev(hw), pba_size * 2 + 1, GFP_KERNEL);
616 if (!ptr)
617 return;
618 hw->pba_id = ptr;
619
620 for (i = 0; i < pba_size; i++) {
621 status = i40e_read_nvm_word(hw, pba_ptr + i, &pba_word);
622 if (status) {
623 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
624 devm_kfree(i40e_hw_to_dev(hw), hw->pba_id);
625 hw->pba_id = NULL;
626 return;
627 }
628
629 *ptr++ = (pba_word >> 8) & 0xFF;
630 *ptr++ = pba_word & 0xFF;
631 }
632 }
633
634 /**
635 * i40e_get_media_type - Gets media type
636 * @hw: pointer to the hardware structure
637 **/
i40e_get_media_type(struct i40e_hw * hw)638 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
639 {
640 enum i40e_media_type media;
641
642 switch (hw->phy.link_info.phy_type) {
643 case I40E_PHY_TYPE_10GBASE_SR:
644 case I40E_PHY_TYPE_10GBASE_LR:
645 case I40E_PHY_TYPE_1000BASE_SX:
646 case I40E_PHY_TYPE_1000BASE_LX:
647 case I40E_PHY_TYPE_40GBASE_SR4:
648 case I40E_PHY_TYPE_40GBASE_LR4:
649 case I40E_PHY_TYPE_25GBASE_LR:
650 case I40E_PHY_TYPE_25GBASE_SR:
651 media = I40E_MEDIA_TYPE_FIBER;
652 break;
653 case I40E_PHY_TYPE_100BASE_TX:
654 case I40E_PHY_TYPE_1000BASE_T:
655 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
656 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
657 case I40E_PHY_TYPE_10GBASE_T:
658 media = I40E_MEDIA_TYPE_BASET;
659 break;
660 case I40E_PHY_TYPE_10GBASE_CR1_CU:
661 case I40E_PHY_TYPE_40GBASE_CR4_CU:
662 case I40E_PHY_TYPE_10GBASE_CR1:
663 case I40E_PHY_TYPE_40GBASE_CR4:
664 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
665 case I40E_PHY_TYPE_40GBASE_AOC:
666 case I40E_PHY_TYPE_10GBASE_AOC:
667 case I40E_PHY_TYPE_25GBASE_CR:
668 case I40E_PHY_TYPE_25GBASE_AOC:
669 case I40E_PHY_TYPE_25GBASE_ACC:
670 media = I40E_MEDIA_TYPE_DA;
671 break;
672 case I40E_PHY_TYPE_1000BASE_KX:
673 case I40E_PHY_TYPE_10GBASE_KX4:
674 case I40E_PHY_TYPE_10GBASE_KR:
675 case I40E_PHY_TYPE_40GBASE_KR4:
676 case I40E_PHY_TYPE_20GBASE_KR2:
677 case I40E_PHY_TYPE_25GBASE_KR:
678 media = I40E_MEDIA_TYPE_BACKPLANE;
679 break;
680 case I40E_PHY_TYPE_SGMII:
681 case I40E_PHY_TYPE_XAUI:
682 case I40E_PHY_TYPE_XFI:
683 case I40E_PHY_TYPE_XLAUI:
684 case I40E_PHY_TYPE_XLPPI:
685 default:
686 media = I40E_MEDIA_TYPE_UNKNOWN;
687 break;
688 }
689
690 return media;
691 }
692
693 /**
694 * i40e_poll_globr - Poll for Global Reset completion
695 * @hw: pointer to the hardware structure
696 * @retry_limit: how many times to retry before failure
697 **/
i40e_poll_globr(struct i40e_hw * hw,u32 retry_limit)698 static int i40e_poll_globr(struct i40e_hw *hw,
699 u32 retry_limit)
700 {
701 u32 cnt, reg = 0;
702
703 for (cnt = 0; cnt < retry_limit; cnt++) {
704 reg = rd32(hw, I40E_GLGEN_RSTAT);
705 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
706 return 0;
707 msleep(100);
708 }
709
710 hw_dbg(hw, "Global reset failed.\n");
711 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
712
713 return -EIO;
714 }
715
716 #define I40E_PF_RESET_WAIT_COUNT_A0 200
717 #define I40E_PF_RESET_WAIT_COUNT 200
718 /**
719 * i40e_pf_reset - Reset the PF
720 * @hw: pointer to the hardware structure
721 *
722 * Assuming someone else has triggered a global reset,
723 * assure the global reset is complete and then reset the PF
724 **/
i40e_pf_reset(struct i40e_hw * hw)725 int i40e_pf_reset(struct i40e_hw *hw)
726 {
727 u32 cnt = 0;
728 u32 cnt1 = 0;
729 u32 reg = 0;
730 u32 grst_del;
731
732 /* Poll for Global Reset steady state in case of recent GRST.
733 * The grst delay value is in 100ms units, and we'll wait a
734 * couple counts longer to be sure we don't just miss the end.
735 */
736 grst_del = FIELD_GET(I40E_GLGEN_RSTCTL_GRSTDEL_MASK,
737 rd32(hw, I40E_GLGEN_RSTCTL));
738
739 /* It can take upto 15 secs for GRST steady state.
740 * Bump it to 16 secs max to be safe.
741 */
742 grst_del = grst_del * 20;
743
744 for (cnt = 0; cnt < grst_del; cnt++) {
745 reg = rd32(hw, I40E_GLGEN_RSTAT);
746 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
747 break;
748 msleep(100);
749 }
750 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
751 hw_dbg(hw, "Global reset polling failed to complete.\n");
752 return -EIO;
753 }
754
755 /* Now Wait for the FW to be ready */
756 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
757 reg = rd32(hw, I40E_GLNVM_ULD);
758 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
759 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
760 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
761 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
762 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
763 break;
764 }
765 usleep_range(10000, 20000);
766 }
767 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
768 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
769 hw_dbg(hw, "wait for FW Reset complete timedout\n");
770 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
771 return -EIO;
772 }
773
774 /* If there was a Global Reset in progress when we got here,
775 * we don't need to do the PF Reset
776 */
777 if (!cnt) {
778 u32 reg2 = 0;
779 if (hw->revision_id == 0)
780 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
781 else
782 cnt = I40E_PF_RESET_WAIT_COUNT;
783 reg = rd32(hw, I40E_PFGEN_CTRL);
784 wr32(hw, I40E_PFGEN_CTRL,
785 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
786 for (; cnt; cnt--) {
787 reg = rd32(hw, I40E_PFGEN_CTRL);
788 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
789 break;
790 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
791 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
792 break;
793 usleep_range(1000, 2000);
794 }
795 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
796 if (i40e_poll_globr(hw, grst_del))
797 return -EIO;
798 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
799 hw_dbg(hw, "PF reset polling failed to complete.\n");
800 return -EIO;
801 }
802 }
803
804 i40e_clear_pxe_mode(hw);
805
806 return 0;
807 }
808
809 /**
810 * i40e_clear_hw - clear out any left over hw state
811 * @hw: pointer to the hw struct
812 *
813 * Clear queues and interrupts, typically called at init time,
814 * but after the capabilities have been found so we know how many
815 * queues and msix vectors have been allocated.
816 **/
i40e_clear_hw(struct i40e_hw * hw)817 void i40e_clear_hw(struct i40e_hw *hw)
818 {
819 u32 num_queues, base_queue;
820 s32 num_pf_int;
821 s32 num_vf_int;
822 u32 num_vfs;
823 s32 i;
824 u32 j;
825 u32 val;
826 u32 eol = 0x7ff;
827
828 /* get number of interrupts, queues, and VFs */
829 val = rd32(hw, I40E_GLPCI_CNF2);
830 num_pf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_PF_N_MASK, val);
831 num_vf_int = FIELD_GET(I40E_GLPCI_CNF2_MSI_X_VF_N_MASK, val);
832
833 val = rd32(hw, I40E_PFLAN_QALLOC);
834 base_queue = FIELD_GET(I40E_PFLAN_QALLOC_FIRSTQ_MASK, val);
835 j = FIELD_GET(I40E_PFLAN_QALLOC_LASTQ_MASK, val);
836 if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue)
837 num_queues = (j - base_queue) + 1;
838 else
839 num_queues = 0;
840
841 val = rd32(hw, I40E_PF_VT_PFALLOC);
842 i = FIELD_GET(I40E_PF_VT_PFALLOC_FIRSTVF_MASK, val);
843 j = FIELD_GET(I40E_PF_VT_PFALLOC_LASTVF_MASK, val);
844 if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i)
845 num_vfs = (j - i) + 1;
846 else
847 num_vfs = 0;
848
849 /* stop all the interrupts */
850 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
851 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
852 for (i = 0; i < num_pf_int - 2; i++)
853 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
854
855 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
856 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
857 wr32(hw, I40E_PFINT_LNKLST0, val);
858 for (i = 0; i < num_pf_int - 2; i++)
859 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
860 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
861 for (i = 0; i < num_vfs; i++)
862 wr32(hw, I40E_VPINT_LNKLST0(i), val);
863 for (i = 0; i < num_vf_int - 2; i++)
864 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
865
866 /* warn the HW of the coming Tx disables */
867 for (i = 0; i < num_queues; i++) {
868 u32 abs_queue_idx = base_queue + i;
869 u32 reg_block = 0;
870
871 if (abs_queue_idx >= 128) {
872 reg_block = abs_queue_idx / 128;
873 abs_queue_idx %= 128;
874 }
875
876 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
877 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
878 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
879 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
880
881 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
882 }
883 udelay(400);
884
885 /* stop all the queues */
886 for (i = 0; i < num_queues; i++) {
887 wr32(hw, I40E_QINT_TQCTL(i), 0);
888 wr32(hw, I40E_QTX_ENA(i), 0);
889 wr32(hw, I40E_QINT_RQCTL(i), 0);
890 wr32(hw, I40E_QRX_ENA(i), 0);
891 }
892
893 /* short wait for all queue disables to settle */
894 udelay(50);
895 }
896
897 /**
898 * i40e_clear_pxe_mode - clear pxe operations mode
899 * @hw: pointer to the hw struct
900 *
901 * Make sure all PXE mode settings are cleared, including things
902 * like descriptor fetch/write-back mode.
903 **/
i40e_clear_pxe_mode(struct i40e_hw * hw)904 void i40e_clear_pxe_mode(struct i40e_hw *hw)
905 {
906 u32 reg;
907
908 if (i40e_check_asq_alive(hw))
909 i40e_aq_clear_pxe_mode(hw, NULL);
910
911 /* Clear single descriptor fetch/write-back mode */
912 reg = rd32(hw, I40E_GLLAN_RCTL_0);
913
914 if (hw->revision_id == 0) {
915 /* As a work around clear PXE_MODE instead of setting it */
916 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
917 } else {
918 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
919 }
920 }
921
922 /**
923 * i40e_led_is_mine - helper to find matching led
924 * @hw: pointer to the hw struct
925 * @idx: index into GPIO registers
926 *
927 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
928 */
i40e_led_is_mine(struct i40e_hw * hw,int idx)929 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
930 {
931 u32 gpio_val = 0;
932 u32 port;
933
934 if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
935 !hw->func_caps.led[idx])
936 return 0;
937 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
938 port = FIELD_GET(I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK, gpio_val);
939
940 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
941 * if it is not our port then ignore
942 */
943 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
944 (port != hw->port))
945 return 0;
946
947 return gpio_val;
948 }
949
950 #define I40E_FW_LED BIT(4)
951 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
952 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
953
954 #define I40E_LED0 22
955
956 #define I40E_PIN_FUNC_SDP 0x0
957 #define I40E_PIN_FUNC_LED 0x1
958
959 /**
960 * i40e_led_get - return current on/off mode
961 * @hw: pointer to the hw struct
962 *
963 * The value returned is the 'mode' field as defined in the
964 * GPIO register definitions: 0x0 = off, 0xf = on, and other
965 * values are variations of possible behaviors relating to
966 * blink, link, and wire.
967 **/
i40e_led_get(struct i40e_hw * hw)968 u32 i40e_led_get(struct i40e_hw *hw)
969 {
970 u32 mode = 0;
971 int i;
972
973 /* as per the documentation GPIO 22-29 are the LED
974 * GPIO pins named LED0..LED7
975 */
976 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
977 u32 gpio_val = i40e_led_is_mine(hw, i);
978
979 if (!gpio_val)
980 continue;
981
982 mode = FIELD_GET(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK, gpio_val);
983 break;
984 }
985
986 return mode;
987 }
988
989 /**
990 * i40e_led_set - set new on/off mode
991 * @hw: pointer to the hw struct
992 * @mode: 0=off, 0xf=on (else see manual for mode details)
993 * @blink: true if the LED should blink when on, false if steady
994 *
995 * if this function is used to turn on the blink it should
996 * be used to disable the blink when restoring the original state.
997 **/
i40e_led_set(struct i40e_hw * hw,u32 mode,bool blink)998 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
999 {
1000 int i;
1001
1002 if (mode & ~I40E_LED_MODE_VALID) {
1003 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1004 return;
1005 }
1006
1007 /* as per the documentation GPIO 22-29 are the LED
1008 * GPIO pins named LED0..LED7
1009 */
1010 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1011 u32 gpio_val = i40e_led_is_mine(hw, i);
1012
1013 if (!gpio_val)
1014 continue;
1015
1016 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1017 u32 pin_func = 0;
1018
1019 if (mode & I40E_FW_LED)
1020 pin_func = I40E_PIN_FUNC_SDP;
1021 else
1022 pin_func = I40E_PIN_FUNC_LED;
1023
1024 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1025 gpio_val |=
1026 FIELD_PREP(I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK,
1027 pin_func);
1028 }
1029 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1030 /* this & is a bit of paranoia, but serves as a range check */
1031 gpio_val |= FIELD_PREP(I40E_GLGEN_GPIO_CTL_LED_MODE_MASK,
1032 mode);
1033
1034 if (blink)
1035 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1036 else
1037 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1038
1039 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1040 break;
1041 }
1042 }
1043
1044 /* Admin command wrappers */
1045
1046 /**
1047 * i40e_aq_get_phy_capabilities
1048 * @hw: pointer to the hw struct
1049 * @abilities: structure for PHY capabilities to be filled
1050 * @qualified_modules: report Qualified Modules
1051 * @report_init: report init capabilities (active are default)
1052 * @cmd_details: pointer to command details structure or NULL
1053 *
1054 * Returns the various PHY abilities supported on the Port.
1055 **/
1056 int
i40e_aq_get_phy_capabilities(struct i40e_hw * hw,bool qualified_modules,bool report_init,struct i40e_aq_get_phy_abilities_resp * abilities,struct i40e_asq_cmd_details * cmd_details)1057 i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1058 bool qualified_modules, bool report_init,
1059 struct i40e_aq_get_phy_abilities_resp *abilities,
1060 struct i40e_asq_cmd_details *cmd_details)
1061 {
1062 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1063 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1064 struct i40e_aq_desc desc;
1065 int status;
1066
1067 if (!abilities)
1068 return -EINVAL;
1069
1070 do {
1071 i40e_fill_default_direct_cmd_desc(&desc,
1072 i40e_aqc_opc_get_phy_abilities);
1073
1074 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1075 if (abilities_size > I40E_AQ_LARGE_BUF)
1076 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1077
1078 if (qualified_modules)
1079 desc.params.external.param0 |=
1080 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1081
1082 if (report_init)
1083 desc.params.external.param0 |=
1084 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1085
1086 status = i40e_asq_send_command(hw, &desc, abilities,
1087 abilities_size, cmd_details);
1088
1089 switch (hw->aq.asq_last_status) {
1090 case I40E_AQ_RC_EIO:
1091 status = -EIO;
1092 break;
1093 case I40E_AQ_RC_EAGAIN:
1094 usleep_range(1000, 2000);
1095 total_delay++;
1096 status = -EIO;
1097 break;
1098 /* also covers I40E_AQ_RC_OK */
1099 default:
1100 break;
1101 }
1102
1103 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1104 (total_delay < max_delay));
1105
1106 if (status)
1107 return status;
1108
1109 if (report_init) {
1110 if (hw->mac.type == I40E_MAC_XL710 &&
1111 i40e_is_aq_api_ver_ge(hw, I40E_FW_API_VERSION_MAJOR,
1112 I40E_MINOR_VER_GET_LINK_INFO_XL710)) {
1113 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1114 } else {
1115 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1116 hw->phy.phy_types |=
1117 ((u64)abilities->phy_type_ext << 32);
1118 }
1119 }
1120
1121 return status;
1122 }
1123
1124 /**
1125 * i40e_aq_set_phy_config
1126 * @hw: pointer to the hw struct
1127 * @config: structure with PHY configuration to be set
1128 * @cmd_details: pointer to command details structure or NULL
1129 *
1130 * Set the various PHY configuration parameters
1131 * supported on the Port.One or more of the Set PHY config parameters may be
1132 * ignored in an MFP mode as the PF may not have the privilege to set some
1133 * of the PHY Config parameters. This status will be indicated by the
1134 * command response.
1135 **/
i40e_aq_set_phy_config(struct i40e_hw * hw,struct i40e_aq_set_phy_config * config,struct i40e_asq_cmd_details * cmd_details)1136 int i40e_aq_set_phy_config(struct i40e_hw *hw,
1137 struct i40e_aq_set_phy_config *config,
1138 struct i40e_asq_cmd_details *cmd_details)
1139 {
1140 struct i40e_aq_desc desc;
1141 struct i40e_aq_set_phy_config *cmd =
1142 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1143 int status;
1144
1145 if (!config)
1146 return -EINVAL;
1147
1148 i40e_fill_default_direct_cmd_desc(&desc,
1149 i40e_aqc_opc_set_phy_config);
1150
1151 *cmd = *config;
1152
1153 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1154
1155 return status;
1156 }
1157
1158 static noinline_for_stack int
i40e_set_fc_status(struct i40e_hw * hw,struct i40e_aq_get_phy_abilities_resp * abilities,bool atomic_restart)1159 i40e_set_fc_status(struct i40e_hw *hw,
1160 struct i40e_aq_get_phy_abilities_resp *abilities,
1161 bool atomic_restart)
1162 {
1163 struct i40e_aq_set_phy_config config;
1164 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1165 u8 pause_mask = 0x0;
1166
1167 switch (fc_mode) {
1168 case I40E_FC_FULL:
1169 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1170 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1171 break;
1172 case I40E_FC_RX_PAUSE:
1173 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1174 break;
1175 case I40E_FC_TX_PAUSE:
1176 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1177 break;
1178 default:
1179 break;
1180 }
1181
1182 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1183 /* clear the old pause settings */
1184 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1185 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1186 /* set the new abilities */
1187 config.abilities |= pause_mask;
1188 /* If the abilities have changed, then set the new config */
1189 if (config.abilities == abilities->abilities)
1190 return 0;
1191
1192 /* Auto restart link so settings take effect */
1193 if (atomic_restart)
1194 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1195 /* Copy over all the old settings */
1196 config.phy_type = abilities->phy_type;
1197 config.phy_type_ext = abilities->phy_type_ext;
1198 config.link_speed = abilities->link_speed;
1199 config.eee_capability = abilities->eee_capability;
1200 config.eeer = abilities->eeer_val;
1201 config.low_power_ctrl = abilities->d3_lpan;
1202 config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1203 I40E_AQ_PHY_FEC_CONFIG_MASK;
1204
1205 return i40e_aq_set_phy_config(hw, &config, NULL);
1206 }
1207
1208 /**
1209 * i40e_set_fc
1210 * @hw: pointer to the hw struct
1211 * @aq_failures: buffer to return AdminQ failure information
1212 * @atomic_restart: whether to enable atomic link restart
1213 *
1214 * Set the requested flow control mode using set_phy_config.
1215 **/
i40e_set_fc(struct i40e_hw * hw,u8 * aq_failures,bool atomic_restart)1216 int i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1217 bool atomic_restart)
1218 {
1219 struct i40e_aq_get_phy_abilities_resp abilities;
1220 int status;
1221
1222 *aq_failures = 0x0;
1223
1224 /* Get the current phy config */
1225 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1226 NULL);
1227 if (status) {
1228 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1229 return status;
1230 }
1231
1232 status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1233 if (status)
1234 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1235
1236 /* Update the link info */
1237 status = i40e_update_link_info(hw);
1238 if (status) {
1239 /* Wait a little bit (on 40G cards it sometimes takes a really
1240 * long time for link to come back from the atomic reset)
1241 * and try once more
1242 */
1243 msleep(1000);
1244 status = i40e_update_link_info(hw);
1245 }
1246 if (status)
1247 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1248
1249 return status;
1250 }
1251
1252 /**
1253 * i40e_aq_clear_pxe_mode
1254 * @hw: pointer to the hw struct
1255 * @cmd_details: pointer to command details structure or NULL
1256 *
1257 * Tell the firmware that the driver is taking over from PXE
1258 **/
i40e_aq_clear_pxe_mode(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)1259 int i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1260 struct i40e_asq_cmd_details *cmd_details)
1261 {
1262 struct i40e_aq_desc desc;
1263 struct i40e_aqc_clear_pxe *cmd =
1264 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1265 int status;
1266
1267 i40e_fill_default_direct_cmd_desc(&desc,
1268 i40e_aqc_opc_clear_pxe_mode);
1269
1270 cmd->rx_cnt = 0x2;
1271
1272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1273
1274 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1275
1276 return status;
1277 }
1278
1279 /**
1280 * i40e_aq_set_link_restart_an
1281 * @hw: pointer to the hw struct
1282 * @enable_link: if true: enable link, if false: disable link
1283 * @cmd_details: pointer to command details structure or NULL
1284 *
1285 * Sets up the link and restarts the Auto-Negotiation over the link.
1286 **/
i40e_aq_set_link_restart_an(struct i40e_hw * hw,bool enable_link,struct i40e_asq_cmd_details * cmd_details)1287 int i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1288 bool enable_link,
1289 struct i40e_asq_cmd_details *cmd_details)
1290 {
1291 struct i40e_aq_desc desc;
1292 struct i40e_aqc_set_link_restart_an *cmd =
1293 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1294 int status;
1295
1296 i40e_fill_default_direct_cmd_desc(&desc,
1297 i40e_aqc_opc_set_link_restart_an);
1298
1299 cmd->command = I40E_AQ_PHY_RESTART_AN;
1300 if (enable_link)
1301 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1302 else
1303 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1304
1305 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1306
1307 return status;
1308 }
1309
1310 /**
1311 * i40e_aq_get_link_info
1312 * @hw: pointer to the hw struct
1313 * @enable_lse: enable/disable LinkStatusEvent reporting
1314 * @link: pointer to link status structure - optional
1315 * @cmd_details: pointer to command details structure or NULL
1316 *
1317 * Returns the link status of the adapter.
1318 **/
i40e_aq_get_link_info(struct i40e_hw * hw,bool enable_lse,struct i40e_link_status * link,struct i40e_asq_cmd_details * cmd_details)1319 int i40e_aq_get_link_info(struct i40e_hw *hw,
1320 bool enable_lse, struct i40e_link_status *link,
1321 struct i40e_asq_cmd_details *cmd_details)
1322 {
1323 struct i40e_aq_desc desc;
1324 struct i40e_aqc_get_link_status *resp =
1325 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1326 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1327 bool tx_pause, rx_pause;
1328 u16 command_flags;
1329 int status;
1330
1331 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1332
1333 if (enable_lse)
1334 command_flags = I40E_AQ_LSE_ENABLE;
1335 else
1336 command_flags = I40E_AQ_LSE_DISABLE;
1337 resp->command_flags = cpu_to_le16(command_flags);
1338
1339 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1340
1341 if (status)
1342 goto aq_get_link_info_exit;
1343
1344 /* save off old link status information */
1345 hw->phy.link_info_old = *hw_link_info;
1346
1347 /* update link status */
1348 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1349 hw->phy.media_type = i40e_get_media_type(hw);
1350 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1351 hw_link_info->link_info = resp->link_info;
1352 hw_link_info->an_info = resp->an_info;
1353 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1354 I40E_AQ_CONFIG_FEC_RS_ENA);
1355 hw_link_info->ext_info = resp->ext_info;
1356 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1357 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1358 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1359
1360 /* update fc info */
1361 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1362 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1363 if (tx_pause & rx_pause)
1364 hw->fc.current_mode = I40E_FC_FULL;
1365 else if (tx_pause)
1366 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1367 else if (rx_pause)
1368 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1369 else
1370 hw->fc.current_mode = I40E_FC_NONE;
1371
1372 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1373 hw_link_info->crc_enable = true;
1374 else
1375 hw_link_info->crc_enable = false;
1376
1377 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1378 hw_link_info->lse_enable = true;
1379 else
1380 hw_link_info->lse_enable = false;
1381
1382 if (hw->mac.type == I40E_MAC_XL710 && i40e_is_fw_ver_lt(hw, 4, 40) &&
1383 hw_link_info->phy_type == 0xE)
1384 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1385
1386 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps) &&
1387 hw->mac.type != I40E_MAC_X722) {
1388 __le32 tmp;
1389
1390 memcpy(&tmp, resp->link_type, sizeof(tmp));
1391 hw->phy.phy_types = le32_to_cpu(tmp);
1392 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1393 }
1394
1395 /* save link status information */
1396 if (link)
1397 *link = *hw_link_info;
1398
1399 /* flag cleared so helper functions don't call AQ again */
1400 hw->phy.get_link_info = false;
1401
1402 aq_get_link_info_exit:
1403 return status;
1404 }
1405
1406 /**
1407 * i40e_aq_set_phy_int_mask
1408 * @hw: pointer to the hw struct
1409 * @mask: interrupt mask to be set
1410 * @cmd_details: pointer to command details structure or NULL
1411 *
1412 * Set link interrupt mask.
1413 **/
i40e_aq_set_phy_int_mask(struct i40e_hw * hw,u16 mask,struct i40e_asq_cmd_details * cmd_details)1414 int i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1415 u16 mask,
1416 struct i40e_asq_cmd_details *cmd_details)
1417 {
1418 struct i40e_aq_desc desc;
1419 struct i40e_aqc_set_phy_int_mask *cmd =
1420 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1421 int status;
1422
1423 i40e_fill_default_direct_cmd_desc(&desc,
1424 i40e_aqc_opc_set_phy_int_mask);
1425
1426 cmd->event_mask = cpu_to_le16(mask);
1427
1428 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1429
1430 return status;
1431 }
1432
1433 /**
1434 * i40e_aq_set_mac_loopback
1435 * @hw: pointer to the HW struct
1436 * @ena_lpbk: Enable or Disable loopback
1437 * @cmd_details: pointer to command details structure or NULL
1438 *
1439 * Enable/disable loopback on a given port
1440 */
i40e_aq_set_mac_loopback(struct i40e_hw * hw,bool ena_lpbk,struct i40e_asq_cmd_details * cmd_details)1441 int i40e_aq_set_mac_loopback(struct i40e_hw *hw, bool ena_lpbk,
1442 struct i40e_asq_cmd_details *cmd_details)
1443 {
1444 struct i40e_aq_desc desc;
1445 struct i40e_aqc_set_lb_mode *cmd =
1446 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
1447
1448 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_lb_modes);
1449 if (ena_lpbk) {
1450 if (hw->nvm.version <= I40E_LEGACY_LOOPBACK_NVM_VER)
1451 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL_LEGACY);
1452 else
1453 cmd->lb_mode = cpu_to_le16(I40E_AQ_LB_MAC_LOCAL);
1454 }
1455
1456 return i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1457 }
1458
1459 /**
1460 * i40e_aq_set_phy_debug
1461 * @hw: pointer to the hw struct
1462 * @cmd_flags: debug command flags
1463 * @cmd_details: pointer to command details structure or NULL
1464 *
1465 * Reset the external PHY.
1466 **/
i40e_aq_set_phy_debug(struct i40e_hw * hw,u8 cmd_flags,struct i40e_asq_cmd_details * cmd_details)1467 int i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1468 struct i40e_asq_cmd_details *cmd_details)
1469 {
1470 struct i40e_aq_desc desc;
1471 struct i40e_aqc_set_phy_debug *cmd =
1472 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1473 int status;
1474
1475 i40e_fill_default_direct_cmd_desc(&desc,
1476 i40e_aqc_opc_set_phy_debug);
1477
1478 cmd->command_flags = cmd_flags;
1479
1480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1481
1482 return status;
1483 }
1484
1485 /**
1486 * i40e_aq_add_vsi
1487 * @hw: pointer to the hw struct
1488 * @vsi_ctx: pointer to a vsi context struct
1489 * @cmd_details: pointer to command details structure or NULL
1490 *
1491 * Add a VSI context to the hardware.
1492 **/
i40e_aq_add_vsi(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)1493 int i40e_aq_add_vsi(struct i40e_hw *hw,
1494 struct i40e_vsi_context *vsi_ctx,
1495 struct i40e_asq_cmd_details *cmd_details)
1496 {
1497 struct i40e_aq_desc desc;
1498 struct i40e_aqc_add_get_update_vsi *cmd =
1499 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1500 struct i40e_aqc_add_get_update_vsi_completion *resp =
1501 (struct i40e_aqc_add_get_update_vsi_completion *)
1502 &desc.params.raw;
1503 int status;
1504
1505 i40e_fill_default_direct_cmd_desc(&desc,
1506 i40e_aqc_opc_add_vsi);
1507
1508 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1509 cmd->connection_type = vsi_ctx->connection_type;
1510 cmd->vf_id = vsi_ctx->vf_num;
1511 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1512
1513 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1514
1515 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info,
1516 sizeof(vsi_ctx->info),
1517 cmd_details, true);
1518
1519 if (status)
1520 goto aq_add_vsi_exit;
1521
1522 vsi_ctx->seid = le16_to_cpu(resp->seid);
1523 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1524 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1525 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1526
1527 aq_add_vsi_exit:
1528 return status;
1529 }
1530
1531 /**
1532 * i40e_aq_set_default_vsi
1533 * @hw: pointer to the hw struct
1534 * @seid: vsi number
1535 * @cmd_details: pointer to command details structure or NULL
1536 **/
i40e_aq_set_default_vsi(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)1537 int i40e_aq_set_default_vsi(struct i40e_hw *hw,
1538 u16 seid,
1539 struct i40e_asq_cmd_details *cmd_details)
1540 {
1541 struct i40e_aq_desc desc;
1542 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1543 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1544 &desc.params.raw;
1545 int status;
1546
1547 i40e_fill_default_direct_cmd_desc(&desc,
1548 i40e_aqc_opc_set_vsi_promiscuous_modes);
1549
1550 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1551 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1552 cmd->seid = cpu_to_le16(seid);
1553
1554 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1555
1556 return status;
1557 }
1558
1559 /**
1560 * i40e_aq_clear_default_vsi
1561 * @hw: pointer to the hw struct
1562 * @seid: vsi number
1563 * @cmd_details: pointer to command details structure or NULL
1564 **/
i40e_aq_clear_default_vsi(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)1565 int i40e_aq_clear_default_vsi(struct i40e_hw *hw,
1566 u16 seid,
1567 struct i40e_asq_cmd_details *cmd_details)
1568 {
1569 struct i40e_aq_desc desc;
1570 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1571 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1572 &desc.params.raw;
1573 int status;
1574
1575 i40e_fill_default_direct_cmd_desc(&desc,
1576 i40e_aqc_opc_set_vsi_promiscuous_modes);
1577
1578 cmd->promiscuous_flags = cpu_to_le16(0);
1579 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1580 cmd->seid = cpu_to_le16(seid);
1581
1582 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1583
1584 return status;
1585 }
1586
1587 /**
1588 * i40e_aq_set_vsi_unicast_promiscuous
1589 * @hw: pointer to the hw struct
1590 * @seid: vsi number
1591 * @set: set unicast promiscuous enable/disable
1592 * @cmd_details: pointer to command details structure or NULL
1593 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
1594 **/
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details,bool rx_only_promisc)1595 int i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1596 u16 seid, bool set,
1597 struct i40e_asq_cmd_details *cmd_details,
1598 bool rx_only_promisc)
1599 {
1600 struct i40e_aq_desc desc;
1601 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1602 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1603 u16 flags = 0;
1604 int status;
1605
1606 i40e_fill_default_direct_cmd_desc(&desc,
1607 i40e_aqc_opc_set_vsi_promiscuous_modes);
1608
1609 if (set) {
1610 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1611 if (rx_only_promisc && i40e_is_aq_api_ver_ge(hw, 1, 5))
1612 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
1613 }
1614
1615 cmd->promiscuous_flags = cpu_to_le16(flags);
1616
1617 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1618 if (i40e_is_aq_api_ver_ge(hw, 1, 5))
1619 cmd->valid_flags |=
1620 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
1621
1622 cmd->seid = cpu_to_le16(seid);
1623 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1624
1625 return status;
1626 }
1627
1628 /**
1629 * i40e_aq_set_vsi_multicast_promiscuous
1630 * @hw: pointer to the hw struct
1631 * @seid: vsi number
1632 * @set: set multicast promiscuous enable/disable
1633 * @cmd_details: pointer to command details structure or NULL
1634 **/
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details)1635 int i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1636 u16 seid, bool set,
1637 struct i40e_asq_cmd_details *cmd_details)
1638 {
1639 struct i40e_aq_desc desc;
1640 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1641 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1642 u16 flags = 0;
1643 int status;
1644
1645 i40e_fill_default_direct_cmd_desc(&desc,
1646 i40e_aqc_opc_set_vsi_promiscuous_modes);
1647
1648 if (set)
1649 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1650
1651 cmd->promiscuous_flags = cpu_to_le16(flags);
1652
1653 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1654
1655 cmd->seid = cpu_to_le16(seid);
1656 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1657
1658 return status;
1659 }
1660
1661 /**
1662 * i40e_aq_set_vsi_mc_promisc_on_vlan
1663 * @hw: pointer to the hw struct
1664 * @seid: vsi number
1665 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1666 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
1667 * @cmd_details: pointer to command details structure or NULL
1668 **/
i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)1669 int i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
1670 u16 seid, bool enable,
1671 u16 vid,
1672 struct i40e_asq_cmd_details *cmd_details)
1673 {
1674 struct i40e_aq_desc desc;
1675 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1676 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1677 u16 flags = 0;
1678 int status;
1679
1680 i40e_fill_default_direct_cmd_desc(&desc,
1681 i40e_aqc_opc_set_vsi_promiscuous_modes);
1682
1683 if (enable)
1684 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1685
1686 cmd->promiscuous_flags = cpu_to_le16(flags);
1687 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1688 cmd->seid = cpu_to_le16(seid);
1689 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
1690
1691 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
1692 cmd_details, true);
1693
1694 return status;
1695 }
1696
1697 /**
1698 * i40e_aq_set_vsi_uc_promisc_on_vlan
1699 * @hw: pointer to the hw struct
1700 * @seid: vsi number
1701 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1702 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
1703 * @cmd_details: pointer to command details structure or NULL
1704 **/
i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)1705 int i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
1706 u16 seid, bool enable,
1707 u16 vid,
1708 struct i40e_asq_cmd_details *cmd_details)
1709 {
1710 struct i40e_aq_desc desc;
1711 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1712 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1713 u16 flags = 0;
1714 int status;
1715
1716 i40e_fill_default_direct_cmd_desc(&desc,
1717 i40e_aqc_opc_set_vsi_promiscuous_modes);
1718
1719 if (enable) {
1720 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1721 if (i40e_is_aq_api_ver_ge(hw, 1, 5))
1722 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
1723 }
1724
1725 cmd->promiscuous_flags = cpu_to_le16(flags);
1726 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1727 if (i40e_is_aq_api_ver_ge(hw, 1, 5))
1728 cmd->valid_flags |=
1729 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
1730 cmd->seid = cpu_to_le16(seid);
1731 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
1732
1733 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
1734 cmd_details, true);
1735
1736 return status;
1737 }
1738
1739 /**
1740 * i40e_aq_set_vsi_bc_promisc_on_vlan
1741 * @hw: pointer to the hw struct
1742 * @seid: vsi number
1743 * @enable: set broadcast promiscuous enable/disable for a given VLAN
1744 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
1745 * @cmd_details: pointer to command details structure or NULL
1746 **/
i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)1747 int i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
1748 u16 seid, bool enable, u16 vid,
1749 struct i40e_asq_cmd_details *cmd_details)
1750 {
1751 struct i40e_aq_desc desc;
1752 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1753 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1754 u16 flags = 0;
1755 int status;
1756
1757 i40e_fill_default_direct_cmd_desc(&desc,
1758 i40e_aqc_opc_set_vsi_promiscuous_modes);
1759
1760 if (enable)
1761 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
1762
1763 cmd->promiscuous_flags = cpu_to_le16(flags);
1764 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1765 cmd->seid = cpu_to_le16(seid);
1766 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
1767
1768 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1769
1770 return status;
1771 }
1772
1773 /**
1774 * i40e_aq_set_vsi_broadcast
1775 * @hw: pointer to the hw struct
1776 * @seid: vsi number
1777 * @set_filter: true to set filter, false to clear filter
1778 * @cmd_details: pointer to command details structure or NULL
1779 *
1780 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1781 **/
i40e_aq_set_vsi_broadcast(struct i40e_hw * hw,u16 seid,bool set_filter,struct i40e_asq_cmd_details * cmd_details)1782 int i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1783 u16 seid, bool set_filter,
1784 struct i40e_asq_cmd_details *cmd_details)
1785 {
1786 struct i40e_aq_desc desc;
1787 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1788 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1789 int status;
1790
1791 i40e_fill_default_direct_cmd_desc(&desc,
1792 i40e_aqc_opc_set_vsi_promiscuous_modes);
1793
1794 if (set_filter)
1795 cmd->promiscuous_flags
1796 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1797 else
1798 cmd->promiscuous_flags
1799 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1800
1801 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1802 cmd->seid = cpu_to_le16(seid);
1803 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1804
1805 return status;
1806 }
1807
1808 /**
1809 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
1810 * @hw: pointer to the hw struct
1811 * @seid: vsi number
1812 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
1813 * @cmd_details: pointer to command details structure or NULL
1814 **/
i40e_aq_set_vsi_vlan_promisc(struct i40e_hw * hw,u16 seid,bool enable,struct i40e_asq_cmd_details * cmd_details)1815 int i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
1816 u16 seid, bool enable,
1817 struct i40e_asq_cmd_details *cmd_details)
1818 {
1819 struct i40e_aq_desc desc;
1820 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1821 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1822 u16 flags = 0;
1823 int status;
1824
1825 i40e_fill_default_direct_cmd_desc(&desc,
1826 i40e_aqc_opc_set_vsi_promiscuous_modes);
1827 if (enable)
1828 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
1829
1830 cmd->promiscuous_flags = cpu_to_le16(flags);
1831 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
1832 cmd->seid = cpu_to_le16(seid);
1833
1834 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1835
1836 return status;
1837 }
1838
1839 /**
1840 * i40e_aq_get_vsi_params - get VSI configuration info
1841 * @hw: pointer to the hw struct
1842 * @vsi_ctx: pointer to a vsi context struct
1843 * @cmd_details: pointer to command details structure or NULL
1844 **/
i40e_aq_get_vsi_params(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)1845 int i40e_aq_get_vsi_params(struct i40e_hw *hw,
1846 struct i40e_vsi_context *vsi_ctx,
1847 struct i40e_asq_cmd_details *cmd_details)
1848 {
1849 struct i40e_aq_desc desc;
1850 struct i40e_aqc_add_get_update_vsi *cmd =
1851 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1852 struct i40e_aqc_add_get_update_vsi_completion *resp =
1853 (struct i40e_aqc_add_get_update_vsi_completion *)
1854 &desc.params.raw;
1855 int status;
1856
1857 i40e_fill_default_direct_cmd_desc(&desc,
1858 i40e_aqc_opc_get_vsi_parameters);
1859
1860 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1861
1862 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1863
1864 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1865 sizeof(vsi_ctx->info), NULL);
1866
1867 if (status)
1868 goto aq_get_vsi_params_exit;
1869
1870 vsi_ctx->seid = le16_to_cpu(resp->seid);
1871 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1872 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1873 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1874
1875 aq_get_vsi_params_exit:
1876 return status;
1877 }
1878
1879 /**
1880 * i40e_aq_update_vsi_params
1881 * @hw: pointer to the hw struct
1882 * @vsi_ctx: pointer to a vsi context struct
1883 * @cmd_details: pointer to command details structure or NULL
1884 *
1885 * Update a VSI context.
1886 **/
i40e_aq_update_vsi_params(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)1887 int i40e_aq_update_vsi_params(struct i40e_hw *hw,
1888 struct i40e_vsi_context *vsi_ctx,
1889 struct i40e_asq_cmd_details *cmd_details)
1890 {
1891 struct i40e_aq_desc desc;
1892 struct i40e_aqc_add_get_update_vsi *cmd =
1893 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1894 struct i40e_aqc_add_get_update_vsi_completion *resp =
1895 (struct i40e_aqc_add_get_update_vsi_completion *)
1896 &desc.params.raw;
1897 int status;
1898
1899 i40e_fill_default_direct_cmd_desc(&desc,
1900 i40e_aqc_opc_update_vsi_parameters);
1901 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
1902
1903 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1904
1905 status = i40e_asq_send_command_atomic(hw, &desc, &vsi_ctx->info,
1906 sizeof(vsi_ctx->info),
1907 cmd_details, true);
1908
1909 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1910 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1911
1912 return status;
1913 }
1914
1915 /**
1916 * i40e_aq_get_switch_config
1917 * @hw: pointer to the hardware structure
1918 * @buf: pointer to the result buffer
1919 * @buf_size: length of input buffer
1920 * @start_seid: seid to start for the report, 0 == beginning
1921 * @cmd_details: pointer to command details structure or NULL
1922 *
1923 * Fill the buf with switch configuration returned from AdminQ command
1924 **/
i40e_aq_get_switch_config(struct i40e_hw * hw,struct i40e_aqc_get_switch_config_resp * buf,u16 buf_size,u16 * start_seid,struct i40e_asq_cmd_details * cmd_details)1925 int i40e_aq_get_switch_config(struct i40e_hw *hw,
1926 struct i40e_aqc_get_switch_config_resp *buf,
1927 u16 buf_size, u16 *start_seid,
1928 struct i40e_asq_cmd_details *cmd_details)
1929 {
1930 struct i40e_aq_desc desc;
1931 struct i40e_aqc_switch_seid *scfg =
1932 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1933 int status;
1934
1935 i40e_fill_default_direct_cmd_desc(&desc,
1936 i40e_aqc_opc_get_switch_config);
1937 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1938 if (buf_size > I40E_AQ_LARGE_BUF)
1939 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1940 scfg->seid = cpu_to_le16(*start_seid);
1941
1942 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1943 *start_seid = le16_to_cpu(scfg->seid);
1944
1945 return status;
1946 }
1947
1948 /**
1949 * i40e_aq_set_switch_config
1950 * @hw: pointer to the hardware structure
1951 * @flags: bit flag values to set
1952 * @mode: cloud filter mode
1953 * @valid_flags: which bit flags to set
1954 * @mode: cloud filter mode
1955 * @cmd_details: pointer to command details structure or NULL
1956 *
1957 * Set switch configuration bits
1958 **/
i40e_aq_set_switch_config(struct i40e_hw * hw,u16 flags,u16 valid_flags,u8 mode,struct i40e_asq_cmd_details * cmd_details)1959 int i40e_aq_set_switch_config(struct i40e_hw *hw,
1960 u16 flags,
1961 u16 valid_flags, u8 mode,
1962 struct i40e_asq_cmd_details *cmd_details)
1963 {
1964 struct i40e_aq_desc desc;
1965 struct i40e_aqc_set_switch_config *scfg =
1966 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
1967 int status;
1968
1969 i40e_fill_default_direct_cmd_desc(&desc,
1970 i40e_aqc_opc_set_switch_config);
1971 scfg->flags = cpu_to_le16(flags);
1972 scfg->valid_flags = cpu_to_le16(valid_flags);
1973 scfg->mode = mode;
1974 if (test_bit(I40E_HW_CAP_802_1AD, hw->caps)) {
1975 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
1976 scfg->first_tag = cpu_to_le16(hw->first_tag);
1977 scfg->second_tag = cpu_to_le16(hw->second_tag);
1978 }
1979 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1980
1981 return status;
1982 }
1983
1984 /**
1985 * i40e_aq_get_firmware_version
1986 * @hw: pointer to the hw struct
1987 * @fw_major_version: firmware major version
1988 * @fw_minor_version: firmware minor version
1989 * @fw_build: firmware build number
1990 * @api_major_version: major queue version
1991 * @api_minor_version: minor queue version
1992 * @cmd_details: pointer to command details structure or NULL
1993 *
1994 * Get the firmware version from the admin queue commands
1995 **/
i40e_aq_get_firmware_version(struct i40e_hw * hw,u16 * fw_major_version,u16 * fw_minor_version,u32 * fw_build,u16 * api_major_version,u16 * api_minor_version,struct i40e_asq_cmd_details * cmd_details)1996 int i40e_aq_get_firmware_version(struct i40e_hw *hw,
1997 u16 *fw_major_version, u16 *fw_minor_version,
1998 u32 *fw_build,
1999 u16 *api_major_version, u16 *api_minor_version,
2000 struct i40e_asq_cmd_details *cmd_details)
2001 {
2002 struct i40e_aq_desc desc;
2003 struct i40e_aqc_get_version *resp =
2004 (struct i40e_aqc_get_version *)&desc.params.raw;
2005 int status;
2006
2007 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2008
2009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2010
2011 if (!status) {
2012 if (fw_major_version)
2013 *fw_major_version = le16_to_cpu(resp->fw_major);
2014 if (fw_minor_version)
2015 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2016 if (fw_build)
2017 *fw_build = le32_to_cpu(resp->fw_build);
2018 if (api_major_version)
2019 *api_major_version = le16_to_cpu(resp->api_major);
2020 if (api_minor_version)
2021 *api_minor_version = le16_to_cpu(resp->api_minor);
2022 }
2023
2024 return status;
2025 }
2026
2027 /**
2028 * i40e_aq_send_driver_version
2029 * @hw: pointer to the hw struct
2030 * @dv: driver's major, minor version
2031 * @cmd_details: pointer to command details structure or NULL
2032 *
2033 * Send the driver version to the firmware
2034 **/
i40e_aq_send_driver_version(struct i40e_hw * hw,struct i40e_driver_version * dv,struct i40e_asq_cmd_details * cmd_details)2035 int i40e_aq_send_driver_version(struct i40e_hw *hw,
2036 struct i40e_driver_version *dv,
2037 struct i40e_asq_cmd_details *cmd_details)
2038 {
2039 struct i40e_aq_desc desc;
2040 struct i40e_aqc_driver_version *cmd =
2041 (struct i40e_aqc_driver_version *)&desc.params.raw;
2042 int status;
2043 u16 len;
2044
2045 if (dv == NULL)
2046 return -EINVAL;
2047
2048 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2049
2050 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2051 cmd->driver_major_ver = dv->major_version;
2052 cmd->driver_minor_ver = dv->minor_version;
2053 cmd->driver_build_ver = dv->build_version;
2054 cmd->driver_subbuild_ver = dv->subbuild_version;
2055
2056 len = 0;
2057 while (len < sizeof(dv->driver_string) &&
2058 (dv->driver_string[len] < 0x80) &&
2059 dv->driver_string[len])
2060 len++;
2061 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2062 len, cmd_details);
2063
2064 return status;
2065 }
2066
2067 /**
2068 * i40e_get_link_status - get status of the HW network link
2069 * @hw: pointer to the hw struct
2070 * @link_up: pointer to bool (true/false = linkup/linkdown)
2071 *
2072 * Variable link_up true if link is up, false if link is down.
2073 * The variable link_up is invalid if returned value of status != 0
2074 *
2075 * Side effect: LinkStatusEvent reporting becomes enabled
2076 **/
i40e_get_link_status(struct i40e_hw * hw,bool * link_up)2077 int i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2078 {
2079 int status = 0;
2080
2081 if (hw->phy.get_link_info) {
2082 status = i40e_update_link_info(hw);
2083
2084 if (status)
2085 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2086 status);
2087 }
2088
2089 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2090
2091 return status;
2092 }
2093
2094 /**
2095 * i40e_update_link_info - update status of the HW network link
2096 * @hw: pointer to the hw struct
2097 **/
i40e_update_link_info(struct i40e_hw * hw)2098 noinline_for_stack int i40e_update_link_info(struct i40e_hw *hw)
2099 {
2100 struct i40e_aq_get_phy_abilities_resp abilities;
2101 int status = 0;
2102
2103 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2104 if (status)
2105 return status;
2106
2107 /* extra checking needed to ensure link info to user is timely */
2108 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2109 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2110 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2111 status = i40e_aq_get_phy_capabilities(hw, false, false,
2112 &abilities, NULL);
2113 if (status)
2114 return status;
2115
2116 if (abilities.fec_cfg_curr_mod_ext_info &
2117 I40E_AQ_ENABLE_FEC_AUTO)
2118 hw->phy.link_info.req_fec_info =
2119 (I40E_AQ_REQUEST_FEC_KR |
2120 I40E_AQ_REQUEST_FEC_RS);
2121 else
2122 hw->phy.link_info.req_fec_info =
2123 abilities.fec_cfg_curr_mod_ext_info &
2124 (I40E_AQ_REQUEST_FEC_KR |
2125 I40E_AQ_REQUEST_FEC_RS);
2126
2127 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2128 sizeof(hw->phy.link_info.module_type));
2129 }
2130
2131 return status;
2132 }
2133
2134 /**
2135 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2136 * @hw: pointer to the hw struct
2137 * @uplink_seid: the MAC or other gizmo SEID
2138 * @downlink_seid: the VSI SEID
2139 * @enabled_tc: bitmap of TCs to be enabled
2140 * @default_port: true for default port VSI, false for control port
2141 * @veb_seid: pointer to where to put the resulting VEB SEID
2142 * @enable_stats: true to turn on VEB stats
2143 * @cmd_details: pointer to command details structure or NULL
2144 *
2145 * This asks the FW to add a VEB between the uplink and downlink
2146 * elements. If the uplink SEID is 0, this will be a floating VEB.
2147 **/
i40e_aq_add_veb(struct i40e_hw * hw,u16 uplink_seid,u16 downlink_seid,u8 enabled_tc,bool default_port,u16 * veb_seid,bool enable_stats,struct i40e_asq_cmd_details * cmd_details)2148 int i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2149 u16 downlink_seid, u8 enabled_tc,
2150 bool default_port, u16 *veb_seid,
2151 bool enable_stats,
2152 struct i40e_asq_cmd_details *cmd_details)
2153 {
2154 struct i40e_aq_desc desc;
2155 struct i40e_aqc_add_veb *cmd =
2156 (struct i40e_aqc_add_veb *)&desc.params.raw;
2157 struct i40e_aqc_add_veb_completion *resp =
2158 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2159 u16 veb_flags = 0;
2160 int status;
2161
2162 /* SEIDs need to either both be set or both be 0 for floating VEB */
2163 if (!!uplink_seid != !!downlink_seid)
2164 return -EINVAL;
2165
2166 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2167
2168 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2169 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2170 cmd->enable_tcs = enabled_tc;
2171 if (!uplink_seid)
2172 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2173 if (default_port)
2174 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2175 else
2176 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2177
2178 /* reverse logic here: set the bitflag to disable the stats */
2179 if (!enable_stats)
2180 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2181
2182 cmd->veb_flags = cpu_to_le16(veb_flags);
2183
2184 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2185
2186 if (!status && veb_seid)
2187 *veb_seid = le16_to_cpu(resp->veb_seid);
2188
2189 return status;
2190 }
2191
2192 /**
2193 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2194 * @hw: pointer to the hw struct
2195 * @veb_seid: the SEID of the VEB to query
2196 * @switch_id: the uplink switch id
2197 * @floating: set to true if the VEB is floating
2198 * @statistic_index: index of the stats counter block for this VEB
2199 * @vebs_used: number of VEB's used by function
2200 * @vebs_free: total VEB's not reserved by any function
2201 * @cmd_details: pointer to command details structure or NULL
2202 *
2203 * This retrieves the parameters for a particular VEB, specified by
2204 * uplink_seid, and returns them to the caller.
2205 **/
i40e_aq_get_veb_parameters(struct i40e_hw * hw,u16 veb_seid,u16 * switch_id,bool * floating,u16 * statistic_index,u16 * vebs_used,u16 * vebs_free,struct i40e_asq_cmd_details * cmd_details)2206 int i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2207 u16 veb_seid, u16 *switch_id,
2208 bool *floating, u16 *statistic_index,
2209 u16 *vebs_used, u16 *vebs_free,
2210 struct i40e_asq_cmd_details *cmd_details)
2211 {
2212 struct i40e_aq_desc desc;
2213 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2214 (struct i40e_aqc_get_veb_parameters_completion *)
2215 &desc.params.raw;
2216 int status;
2217
2218 if (veb_seid == 0)
2219 return -EINVAL;
2220
2221 i40e_fill_default_direct_cmd_desc(&desc,
2222 i40e_aqc_opc_get_veb_parameters);
2223 cmd_resp->seid = cpu_to_le16(veb_seid);
2224
2225 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2226 if (status)
2227 goto get_veb_exit;
2228
2229 if (switch_id)
2230 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2231 if (statistic_index)
2232 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2233 if (vebs_used)
2234 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2235 if (vebs_free)
2236 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2237 if (floating) {
2238 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2239
2240 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2241 *floating = true;
2242 else
2243 *floating = false;
2244 }
2245
2246 get_veb_exit:
2247 return status;
2248 }
2249
2250 /**
2251 * i40e_prepare_add_macvlan
2252 * @mv_list: list of macvlans to be added
2253 * @desc: pointer to AQ descriptor structure
2254 * @count: length of the list
2255 * @seid: VSI for the mac address
2256 *
2257 * Internal helper function that prepares the add macvlan request
2258 * and returns the buffer size.
2259 **/
2260 static u16
i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data * mv_list,struct i40e_aq_desc * desc,u16 count,u16 seid)2261 i40e_prepare_add_macvlan(struct i40e_aqc_add_macvlan_element_data *mv_list,
2262 struct i40e_aq_desc *desc, u16 count, u16 seid)
2263 {
2264 struct i40e_aqc_macvlan *cmd =
2265 (struct i40e_aqc_macvlan *)&desc->params.raw;
2266 u16 buf_size;
2267 int i;
2268
2269 buf_size = count * sizeof(*mv_list);
2270
2271 /* prep the rest of the request */
2272 i40e_fill_default_direct_cmd_desc(desc, i40e_aqc_opc_add_macvlan);
2273 cmd->num_addresses = cpu_to_le16(count);
2274 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2275 cmd->seid[1] = 0;
2276 cmd->seid[2] = 0;
2277
2278 for (i = 0; i < count; i++)
2279 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2280 mv_list[i].flags |=
2281 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2282
2283 desc->flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2284 if (buf_size > I40E_AQ_LARGE_BUF)
2285 desc->flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2286
2287 return buf_size;
2288 }
2289
2290 /**
2291 * i40e_aq_add_macvlan
2292 * @hw: pointer to the hw struct
2293 * @seid: VSI for the mac address
2294 * @mv_list: list of macvlans to be added
2295 * @count: length of the list
2296 * @cmd_details: pointer to command details structure or NULL
2297 *
2298 * Add MAC/VLAN addresses to the HW filtering
2299 **/
2300 int
i40e_aq_add_macvlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details)2301 i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2302 struct i40e_aqc_add_macvlan_element_data *mv_list,
2303 u16 count, struct i40e_asq_cmd_details *cmd_details)
2304 {
2305 struct i40e_aq_desc desc;
2306 u16 buf_size;
2307
2308 if (count == 0 || !mv_list || !hw)
2309 return -EINVAL;
2310
2311 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid);
2312
2313 return i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size,
2314 cmd_details, true);
2315 }
2316
2317 /**
2318 * i40e_aq_add_macvlan_v2
2319 * @hw: pointer to the hw struct
2320 * @seid: VSI for the mac address
2321 * @mv_list: list of macvlans to be added
2322 * @count: length of the list
2323 * @cmd_details: pointer to command details structure or NULL
2324 * @aq_status: pointer to Admin Queue status return value
2325 *
2326 * Add MAC/VLAN addresses to the HW filtering.
2327 * The _v2 version returns the last Admin Queue status in aq_status
2328 * to avoid race conditions in access to hw->aq.asq_last_status.
2329 * It also calls _v2 versions of asq_send_command functions to
2330 * get the aq_status on the stack.
2331 **/
2332 int
i40e_aq_add_macvlan_v2(struct i40e_hw * hw,u16 seid,struct i40e_aqc_add_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details,enum i40e_admin_queue_err * aq_status)2333 i40e_aq_add_macvlan_v2(struct i40e_hw *hw, u16 seid,
2334 struct i40e_aqc_add_macvlan_element_data *mv_list,
2335 u16 count, struct i40e_asq_cmd_details *cmd_details,
2336 enum i40e_admin_queue_err *aq_status)
2337 {
2338 struct i40e_aq_desc desc;
2339 u16 buf_size;
2340
2341 if (count == 0 || !mv_list || !hw)
2342 return -EINVAL;
2343
2344 buf_size = i40e_prepare_add_macvlan(mv_list, &desc, count, seid);
2345
2346 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size,
2347 cmd_details, true, aq_status);
2348 }
2349
2350 /**
2351 * i40e_aq_remove_macvlan
2352 * @hw: pointer to the hw struct
2353 * @seid: VSI for the mac address
2354 * @mv_list: list of macvlans to be removed
2355 * @count: length of the list
2356 * @cmd_details: pointer to command details structure or NULL
2357 *
2358 * Remove MAC/VLAN addresses from the HW filtering
2359 **/
2360 int
i40e_aq_remove_macvlan(struct i40e_hw * hw,u16 seid,struct i40e_aqc_remove_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details)2361 i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2362 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2363 u16 count, struct i40e_asq_cmd_details *cmd_details)
2364 {
2365 struct i40e_aq_desc desc;
2366 struct i40e_aqc_macvlan *cmd =
2367 (struct i40e_aqc_macvlan *)&desc.params.raw;
2368 u16 buf_size;
2369 int status;
2370
2371 if (count == 0 || !mv_list || !hw)
2372 return -EINVAL;
2373
2374 buf_size = count * sizeof(*mv_list);
2375
2376 /* prep the rest of the request */
2377 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2378 cmd->num_addresses = cpu_to_le16(count);
2379 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2380 cmd->seid[1] = 0;
2381 cmd->seid[2] = 0;
2382
2383 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2384 if (buf_size > I40E_AQ_LARGE_BUF)
2385 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2386
2387 status = i40e_asq_send_command_atomic(hw, &desc, mv_list, buf_size,
2388 cmd_details, true);
2389
2390 return status;
2391 }
2392
2393 /**
2394 * i40e_aq_remove_macvlan_v2
2395 * @hw: pointer to the hw struct
2396 * @seid: VSI for the mac address
2397 * @mv_list: list of macvlans to be removed
2398 * @count: length of the list
2399 * @cmd_details: pointer to command details structure or NULL
2400 * @aq_status: pointer to Admin Queue status return value
2401 *
2402 * Remove MAC/VLAN addresses from the HW filtering.
2403 * The _v2 version returns the last Admin Queue status in aq_status
2404 * to avoid race conditions in access to hw->aq.asq_last_status.
2405 * It also calls _v2 versions of asq_send_command functions to
2406 * get the aq_status on the stack.
2407 **/
2408 int
i40e_aq_remove_macvlan_v2(struct i40e_hw * hw,u16 seid,struct i40e_aqc_remove_macvlan_element_data * mv_list,u16 count,struct i40e_asq_cmd_details * cmd_details,enum i40e_admin_queue_err * aq_status)2409 i40e_aq_remove_macvlan_v2(struct i40e_hw *hw, u16 seid,
2410 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2411 u16 count, struct i40e_asq_cmd_details *cmd_details,
2412 enum i40e_admin_queue_err *aq_status)
2413 {
2414 struct i40e_aqc_macvlan *cmd;
2415 struct i40e_aq_desc desc;
2416 u16 buf_size;
2417
2418 if (count == 0 || !mv_list || !hw)
2419 return -EINVAL;
2420
2421 buf_size = count * sizeof(*mv_list);
2422
2423 /* prep the rest of the request */
2424 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2425 cmd = (struct i40e_aqc_macvlan *)&desc.params.raw;
2426 cmd->num_addresses = cpu_to_le16(count);
2427 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2428 cmd->seid[1] = 0;
2429 cmd->seid[2] = 0;
2430
2431 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2432 if (buf_size > I40E_AQ_LARGE_BUF)
2433 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2434
2435 return i40e_asq_send_command_atomic_v2(hw, &desc, mv_list, buf_size,
2436 cmd_details, true, aq_status);
2437 }
2438
2439 /**
2440 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2441 * @hw: pointer to the hw struct
2442 * @opcode: AQ opcode for add or delete mirror rule
2443 * @sw_seid: Switch SEID (to which rule refers)
2444 * @rule_type: Rule Type (ingress/egress/VLAN)
2445 * @id: Destination VSI SEID or Rule ID
2446 * @count: length of the list
2447 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2448 * @cmd_details: pointer to command details structure or NULL
2449 * @rule_id: Rule ID returned from FW
2450 * @rules_used: Number of rules used in internal switch
2451 * @rules_free: Number of rules free in internal switch
2452 *
2453 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2454 * VEBs/VEPA elements only
2455 **/
i40e_mirrorrule_op(struct i40e_hw * hw,u16 opcode,u16 sw_seid,u16 rule_type,u16 id,u16 count,__le16 * mr_list,struct i40e_asq_cmd_details * cmd_details,u16 * rule_id,u16 * rules_used,u16 * rules_free)2456 static int i40e_mirrorrule_op(struct i40e_hw *hw,
2457 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2458 u16 count, __le16 *mr_list,
2459 struct i40e_asq_cmd_details *cmd_details,
2460 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2461 {
2462 struct i40e_aq_desc desc;
2463 struct i40e_aqc_add_delete_mirror_rule *cmd =
2464 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2465 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2466 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2467 u16 buf_size;
2468 int status;
2469
2470 buf_size = count * sizeof(*mr_list);
2471
2472 /* prep the rest of the request */
2473 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2474 cmd->seid = cpu_to_le16(sw_seid);
2475 cmd->rule_type = cpu_to_le16(rule_type &
2476 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2477 cmd->num_entries = cpu_to_le16(count);
2478 /* Dest VSI for add, rule_id for delete */
2479 cmd->destination = cpu_to_le16(id);
2480 if (mr_list) {
2481 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2482 I40E_AQ_FLAG_RD));
2483 if (buf_size > I40E_AQ_LARGE_BUF)
2484 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2485 }
2486
2487 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2488 cmd_details);
2489 if (!status ||
2490 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2491 if (rule_id)
2492 *rule_id = le16_to_cpu(resp->rule_id);
2493 if (rules_used)
2494 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2495 if (rules_free)
2496 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2497 }
2498 return status;
2499 }
2500
2501 /**
2502 * i40e_aq_add_mirrorrule - add a mirror rule
2503 * @hw: pointer to the hw struct
2504 * @sw_seid: Switch SEID (to which rule refers)
2505 * @rule_type: Rule Type (ingress/egress/VLAN)
2506 * @dest_vsi: SEID of VSI to which packets will be mirrored
2507 * @count: length of the list
2508 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2509 * @cmd_details: pointer to command details structure or NULL
2510 * @rule_id: Rule ID returned from FW
2511 * @rules_used: Number of rules used in internal switch
2512 * @rules_free: Number of rules free in internal switch
2513 *
2514 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2515 **/
i40e_aq_add_mirrorrule(struct i40e_hw * hw,u16 sw_seid,u16 rule_type,u16 dest_vsi,u16 count,__le16 * mr_list,struct i40e_asq_cmd_details * cmd_details,u16 * rule_id,u16 * rules_used,u16 * rules_free)2516 int i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2517 u16 rule_type, u16 dest_vsi, u16 count,
2518 __le16 *mr_list,
2519 struct i40e_asq_cmd_details *cmd_details,
2520 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2521 {
2522 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2523 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2524 if (count == 0 || !mr_list)
2525 return -EINVAL;
2526 }
2527
2528 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2529 rule_type, dest_vsi, count, mr_list,
2530 cmd_details, rule_id, rules_used, rules_free);
2531 }
2532
2533 /**
2534 * i40e_aq_delete_mirrorrule - delete a mirror rule
2535 * @hw: pointer to the hw struct
2536 * @sw_seid: Switch SEID (to which rule refers)
2537 * @rule_type: Rule Type (ingress/egress/VLAN)
2538 * @count: length of the list
2539 * @rule_id: Rule ID that is returned in the receive desc as part of
2540 * add_mirrorrule.
2541 * @mr_list: list of mirrored VLAN IDs to be removed
2542 * @cmd_details: pointer to command details structure or NULL
2543 * @rules_used: Number of rules used in internal switch
2544 * @rules_free: Number of rules free in internal switch
2545 *
2546 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2547 **/
i40e_aq_delete_mirrorrule(struct i40e_hw * hw,u16 sw_seid,u16 rule_type,u16 rule_id,u16 count,__le16 * mr_list,struct i40e_asq_cmd_details * cmd_details,u16 * rules_used,u16 * rules_free)2548 int i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2549 u16 rule_type, u16 rule_id, u16 count,
2550 __le16 *mr_list,
2551 struct i40e_asq_cmd_details *cmd_details,
2552 u16 *rules_used, u16 *rules_free)
2553 {
2554 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2555 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2556 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2557 * mirroring. For other rule_type, count and rule_type should
2558 * not matter.
2559 */
2560 if (count == 0 || !mr_list)
2561 return -EINVAL;
2562 }
2563
2564 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2565 rule_type, rule_id, count, mr_list,
2566 cmd_details, NULL, rules_used, rules_free);
2567 }
2568
2569 /**
2570 * i40e_aq_send_msg_to_vf
2571 * @hw: pointer to the hardware structure
2572 * @vfid: VF id to send msg
2573 * @v_opcode: opcodes for VF-PF communication
2574 * @v_retval: return error code
2575 * @msg: pointer to the msg buffer
2576 * @msglen: msg length
2577 * @cmd_details: pointer to command details
2578 *
2579 * send msg to vf
2580 **/
i40e_aq_send_msg_to_vf(struct i40e_hw * hw,u16 vfid,u32 v_opcode,u32 v_retval,u8 * msg,u16 msglen,struct i40e_asq_cmd_details * cmd_details)2581 int i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2582 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2583 struct i40e_asq_cmd_details *cmd_details)
2584 {
2585 struct i40e_aq_desc desc;
2586 struct i40e_aqc_pf_vf_message *cmd =
2587 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2588 int status;
2589
2590 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2591 cmd->id = cpu_to_le32(vfid);
2592 desc.cookie_high = cpu_to_le32(v_opcode);
2593 desc.cookie_low = cpu_to_le32(v_retval);
2594 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2595 if (msglen) {
2596 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2597 I40E_AQ_FLAG_RD));
2598 if (msglen > I40E_AQ_LARGE_BUF)
2599 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2600 desc.datalen = cpu_to_le16(msglen);
2601 }
2602 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2603
2604 return status;
2605 }
2606
2607 /**
2608 * i40e_aq_debug_read_register
2609 * @hw: pointer to the hw struct
2610 * @reg_addr: register address
2611 * @reg_val: register value
2612 * @cmd_details: pointer to command details structure or NULL
2613 *
2614 * Read the register using the admin queue commands
2615 **/
i40e_aq_debug_read_register(struct i40e_hw * hw,u32 reg_addr,u64 * reg_val,struct i40e_asq_cmd_details * cmd_details)2616 int i40e_aq_debug_read_register(struct i40e_hw *hw,
2617 u32 reg_addr, u64 *reg_val,
2618 struct i40e_asq_cmd_details *cmd_details)
2619 {
2620 struct i40e_aq_desc desc;
2621 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2622 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2623 int status;
2624
2625 if (reg_val == NULL)
2626 return -EINVAL;
2627
2628 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2629
2630 cmd_resp->address = cpu_to_le32(reg_addr);
2631
2632 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2633
2634 if (!status) {
2635 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2636 (u64)le32_to_cpu(cmd_resp->value_low);
2637 }
2638
2639 return status;
2640 }
2641
2642 /**
2643 * i40e_aq_debug_write_register
2644 * @hw: pointer to the hw struct
2645 * @reg_addr: register address
2646 * @reg_val: register value
2647 * @cmd_details: pointer to command details structure or NULL
2648 *
2649 * Write to a register using the admin queue commands
2650 **/
i40e_aq_debug_write_register(struct i40e_hw * hw,u32 reg_addr,u64 reg_val,struct i40e_asq_cmd_details * cmd_details)2651 int i40e_aq_debug_write_register(struct i40e_hw *hw,
2652 u32 reg_addr, u64 reg_val,
2653 struct i40e_asq_cmd_details *cmd_details)
2654 {
2655 struct i40e_aq_desc desc;
2656 struct i40e_aqc_debug_reg_read_write *cmd =
2657 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2658 int status;
2659
2660 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2661
2662 cmd->address = cpu_to_le32(reg_addr);
2663 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2664 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2665
2666 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2667
2668 return status;
2669 }
2670
2671 /**
2672 * i40e_aq_request_resource
2673 * @hw: pointer to the hw struct
2674 * @resource: resource id
2675 * @access: access type
2676 * @sdp_number: resource number
2677 * @timeout: the maximum time in ms that the driver may hold the resource
2678 * @cmd_details: pointer to command details structure or NULL
2679 *
2680 * requests common resource using the admin queue commands
2681 **/
i40e_aq_request_resource(struct i40e_hw * hw,enum i40e_aq_resources_ids resource,enum i40e_aq_resource_access_type access,u8 sdp_number,u64 * timeout,struct i40e_asq_cmd_details * cmd_details)2682 int i40e_aq_request_resource(struct i40e_hw *hw,
2683 enum i40e_aq_resources_ids resource,
2684 enum i40e_aq_resource_access_type access,
2685 u8 sdp_number, u64 *timeout,
2686 struct i40e_asq_cmd_details *cmd_details)
2687 {
2688 struct i40e_aq_desc desc;
2689 struct i40e_aqc_request_resource *cmd_resp =
2690 (struct i40e_aqc_request_resource *)&desc.params.raw;
2691 int status;
2692
2693 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2694
2695 cmd_resp->resource_id = cpu_to_le16(resource);
2696 cmd_resp->access_type = cpu_to_le16(access);
2697 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2698
2699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2700 /* The completion specifies the maximum time in ms that the driver
2701 * may hold the resource in the Timeout field.
2702 * If the resource is held by someone else, the command completes with
2703 * busy return value and the timeout field indicates the maximum time
2704 * the current owner of the resource has to free it.
2705 */
2706 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2707 *timeout = le32_to_cpu(cmd_resp->timeout);
2708
2709 return status;
2710 }
2711
2712 /**
2713 * i40e_aq_release_resource
2714 * @hw: pointer to the hw struct
2715 * @resource: resource id
2716 * @sdp_number: resource number
2717 * @cmd_details: pointer to command details structure or NULL
2718 *
2719 * release common resource using the admin queue commands
2720 **/
i40e_aq_release_resource(struct i40e_hw * hw,enum i40e_aq_resources_ids resource,u8 sdp_number,struct i40e_asq_cmd_details * cmd_details)2721 int i40e_aq_release_resource(struct i40e_hw *hw,
2722 enum i40e_aq_resources_ids resource,
2723 u8 sdp_number,
2724 struct i40e_asq_cmd_details *cmd_details)
2725 {
2726 struct i40e_aq_desc desc;
2727 struct i40e_aqc_request_resource *cmd =
2728 (struct i40e_aqc_request_resource *)&desc.params.raw;
2729 int status;
2730
2731 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2732
2733 cmd->resource_id = cpu_to_le16(resource);
2734 cmd->resource_number = cpu_to_le32(sdp_number);
2735
2736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2737
2738 return status;
2739 }
2740
2741 /**
2742 * i40e_aq_read_nvm
2743 * @hw: pointer to the hw struct
2744 * @module_pointer: module pointer location in words from the NVM beginning
2745 * @offset: byte offset from the module beginning
2746 * @length: length of the section to be read (in bytes from the offset)
2747 * @data: command buffer (size [bytes] = length)
2748 * @last_command: tells if this is the last command in a series
2749 * @cmd_details: pointer to command details structure or NULL
2750 *
2751 * Read the NVM using the admin queue commands
2752 **/
i40e_aq_read_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,void * data,bool last_command,struct i40e_asq_cmd_details * cmd_details)2753 int i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2754 u32 offset, u16 length, void *data,
2755 bool last_command,
2756 struct i40e_asq_cmd_details *cmd_details)
2757 {
2758 struct i40e_aq_desc desc;
2759 struct i40e_aqc_nvm_update *cmd =
2760 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2761 int status;
2762
2763 /* In offset the highest byte must be zeroed. */
2764 if (offset & 0xFF000000) {
2765 status = -EINVAL;
2766 goto i40e_aq_read_nvm_exit;
2767 }
2768
2769 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2770
2771 /* If this is the last command in a series, set the proper flag. */
2772 if (last_command)
2773 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2774 cmd->module_pointer = module_pointer;
2775 cmd->offset = cpu_to_le32(offset);
2776 cmd->length = cpu_to_le16(length);
2777
2778 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2779 if (length > I40E_AQ_LARGE_BUF)
2780 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2781
2782 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2783
2784 i40e_aq_read_nvm_exit:
2785 return status;
2786 }
2787
2788 /**
2789 * i40e_aq_erase_nvm
2790 * @hw: pointer to the hw struct
2791 * @module_pointer: module pointer location in words from the NVM beginning
2792 * @offset: offset in the module (expressed in 4 KB from module's beginning)
2793 * @length: length of the section to be erased (expressed in 4 KB)
2794 * @last_command: tells if this is the last command in a series
2795 * @cmd_details: pointer to command details structure or NULL
2796 *
2797 * Erase the NVM sector using the admin queue commands
2798 **/
i40e_aq_erase_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,bool last_command,struct i40e_asq_cmd_details * cmd_details)2799 int i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2800 u32 offset, u16 length, bool last_command,
2801 struct i40e_asq_cmd_details *cmd_details)
2802 {
2803 struct i40e_aq_desc desc;
2804 struct i40e_aqc_nvm_update *cmd =
2805 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2806 int status;
2807
2808 /* In offset the highest byte must be zeroed. */
2809 if (offset & 0xFF000000) {
2810 status = -EINVAL;
2811 goto i40e_aq_erase_nvm_exit;
2812 }
2813
2814 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2815
2816 /* If this is the last command in a series, set the proper flag. */
2817 if (last_command)
2818 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2819 cmd->module_pointer = module_pointer;
2820 cmd->offset = cpu_to_le32(offset);
2821 cmd->length = cpu_to_le16(length);
2822
2823 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2824
2825 i40e_aq_erase_nvm_exit:
2826 return status;
2827 }
2828
2829 /**
2830 * i40e_parse_discover_capabilities
2831 * @hw: pointer to the hw struct
2832 * @buff: pointer to a buffer containing device/function capability records
2833 * @cap_count: number of capability records in the list
2834 * @list_type_opc: type of capabilities list to parse
2835 *
2836 * Parse the device/function capabilities list.
2837 **/
i40e_parse_discover_capabilities(struct i40e_hw * hw,void * buff,u32 cap_count,enum i40e_admin_queue_opc list_type_opc)2838 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2839 u32 cap_count,
2840 enum i40e_admin_queue_opc list_type_opc)
2841 {
2842 struct i40e_aqc_list_capabilities_element_resp *cap;
2843 u32 valid_functions, num_functions;
2844 u32 number, logical_id, phys_id;
2845 struct i40e_hw_capabilities *p;
2846 u16 id, ocp_cfg_word0;
2847 u8 major_rev;
2848 int status;
2849 u32 i = 0;
2850
2851 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2852
2853 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2854 p = &hw->dev_caps;
2855 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2856 p = &hw->func_caps;
2857 else
2858 return;
2859
2860 for (i = 0; i < cap_count; i++, cap++) {
2861 id = le16_to_cpu(cap->id);
2862 number = le32_to_cpu(cap->number);
2863 logical_id = le32_to_cpu(cap->logical_id);
2864 phys_id = le32_to_cpu(cap->phys_id);
2865 major_rev = cap->major_rev;
2866
2867 switch (id) {
2868 case I40E_AQ_CAP_ID_SWITCH_MODE:
2869 p->switch_mode = number;
2870 break;
2871 case I40E_AQ_CAP_ID_MNG_MODE:
2872 p->management_mode = number;
2873 if (major_rev > 1) {
2874 p->mng_protocols_over_mctp = logical_id;
2875 i40e_debug(hw, I40E_DEBUG_INIT,
2876 "HW Capability: Protocols over MCTP = %d\n",
2877 p->mng_protocols_over_mctp);
2878 } else {
2879 p->mng_protocols_over_mctp = 0;
2880 }
2881 break;
2882 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
2883 p->npar_enable = number;
2884 break;
2885 case I40E_AQ_CAP_ID_OS2BMC_CAP:
2886 p->os2bmc = number;
2887 break;
2888 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
2889 p->valid_functions = number;
2890 break;
2891 case I40E_AQ_CAP_ID_SRIOV:
2892 if (number == 1)
2893 p->sr_iov_1_1 = true;
2894 break;
2895 case I40E_AQ_CAP_ID_VF:
2896 p->num_vfs = number;
2897 p->vf_base_id = logical_id;
2898 break;
2899 case I40E_AQ_CAP_ID_VMDQ:
2900 if (number == 1)
2901 p->vmdq = true;
2902 break;
2903 case I40E_AQ_CAP_ID_8021QBG:
2904 if (number == 1)
2905 p->evb_802_1_qbg = true;
2906 break;
2907 case I40E_AQ_CAP_ID_8021QBR:
2908 if (number == 1)
2909 p->evb_802_1_qbh = true;
2910 break;
2911 case I40E_AQ_CAP_ID_VSI:
2912 p->num_vsis = number;
2913 break;
2914 case I40E_AQ_CAP_ID_DCB:
2915 if (number == 1) {
2916 p->dcb = true;
2917 p->enabled_tcmap = logical_id;
2918 p->maxtc = phys_id;
2919 }
2920 break;
2921 case I40E_AQ_CAP_ID_FCOE:
2922 if (number == 1)
2923 p->fcoe = true;
2924 break;
2925 case I40E_AQ_CAP_ID_ISCSI:
2926 if (number == 1)
2927 p->iscsi = true;
2928 break;
2929 case I40E_AQ_CAP_ID_RSS:
2930 p->rss = true;
2931 p->rss_table_size = number;
2932 p->rss_table_entry_width = logical_id;
2933 break;
2934 case I40E_AQ_CAP_ID_RXQ:
2935 p->num_rx_qp = number;
2936 p->base_queue = phys_id;
2937 break;
2938 case I40E_AQ_CAP_ID_TXQ:
2939 p->num_tx_qp = number;
2940 p->base_queue = phys_id;
2941 break;
2942 case I40E_AQ_CAP_ID_MSIX:
2943 p->num_msix_vectors = number;
2944 i40e_debug(hw, I40E_DEBUG_INIT,
2945 "HW Capability: MSIX vector count = %d\n",
2946 p->num_msix_vectors);
2947 break;
2948 case I40E_AQ_CAP_ID_VF_MSIX:
2949 p->num_msix_vectors_vf = number;
2950 break;
2951 case I40E_AQ_CAP_ID_FLEX10:
2952 if (major_rev == 1) {
2953 if (number == 1) {
2954 p->flex10_enable = true;
2955 p->flex10_capable = true;
2956 }
2957 } else {
2958 /* Capability revision >= 2 */
2959 if (number & 1)
2960 p->flex10_enable = true;
2961 if (number & 2)
2962 p->flex10_capable = true;
2963 }
2964 p->flex10_mode = logical_id;
2965 p->flex10_status = phys_id;
2966 break;
2967 case I40E_AQ_CAP_ID_CEM:
2968 if (number == 1)
2969 p->mgmt_cem = true;
2970 break;
2971 case I40E_AQ_CAP_ID_IWARP:
2972 if (number == 1)
2973 p->iwarp = true;
2974 break;
2975 case I40E_AQ_CAP_ID_LED:
2976 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2977 p->led[phys_id] = true;
2978 break;
2979 case I40E_AQ_CAP_ID_SDP:
2980 if (phys_id < I40E_HW_CAP_MAX_GPIO)
2981 p->sdp[phys_id] = true;
2982 break;
2983 case I40E_AQ_CAP_ID_MDIO:
2984 if (number == 1) {
2985 p->mdio_port_num = phys_id;
2986 p->mdio_port_mode = logical_id;
2987 }
2988 break;
2989 case I40E_AQ_CAP_ID_1588:
2990 if (number == 1)
2991 p->ieee_1588 = true;
2992 break;
2993 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
2994 p->fd = true;
2995 p->fd_filters_guaranteed = number;
2996 p->fd_filters_best_effort = logical_id;
2997 break;
2998 case I40E_AQ_CAP_ID_WSR_PROT:
2999 p->wr_csr_prot = (u64)number;
3000 p->wr_csr_prot |= (u64)logical_id << 32;
3001 break;
3002 case I40E_AQ_CAP_ID_NVM_MGMT:
3003 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3004 p->sec_rev_disabled = true;
3005 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3006 p->update_disabled = true;
3007 break;
3008 default:
3009 break;
3010 }
3011 }
3012
3013 if (p->fcoe)
3014 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3015
3016 /* Software override ensuring FCoE is disabled if npar or mfp
3017 * mode because it is not supported in these modes.
3018 */
3019 if (p->npar_enable || p->flex10_enable)
3020 p->fcoe = false;
3021
3022 /* count the enabled ports (aka the "not disabled" ports) */
3023 hw->num_ports = 0;
3024 for (i = 0; i < 4; i++) {
3025 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3026 u64 port_cfg = 0;
3027
3028 /* use AQ read to get the physical register offset instead
3029 * of the port relative offset
3030 */
3031 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3032 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3033 hw->num_ports++;
3034 }
3035
3036 /* OCP cards case: if a mezz is removed the Ethernet port is at
3037 * disabled state in PRTGEN_CNF register. Additional NVM read is
3038 * needed in order to check if we are dealing with OCP card.
3039 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3040 * physical ports results in wrong partition id calculation and thus
3041 * not supporting WoL.
3042 */
3043 if (hw->mac.type == I40E_MAC_X722) {
3044 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3045 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3046 2 * I40E_SR_OCP_CFG_WORD0,
3047 sizeof(ocp_cfg_word0),
3048 &ocp_cfg_word0, true, NULL);
3049 if (!status &&
3050 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3051 hw->num_ports = 4;
3052 i40e_release_nvm(hw);
3053 }
3054 }
3055
3056 valid_functions = p->valid_functions;
3057 num_functions = 0;
3058 while (valid_functions) {
3059 if (valid_functions & 1)
3060 num_functions++;
3061 valid_functions >>= 1;
3062 }
3063
3064 /* partition id is 1-based, and functions are evenly spread
3065 * across the ports as partitions
3066 */
3067 if (hw->num_ports != 0) {
3068 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3069 hw->num_partitions = num_functions / hw->num_ports;
3070 }
3071
3072 /* additional HW specific goodies that might
3073 * someday be HW version specific
3074 */
3075 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3076 }
3077
3078 /**
3079 * i40e_aq_discover_capabilities
3080 * @hw: pointer to the hw struct
3081 * @buff: a virtual buffer to hold the capabilities
3082 * @buff_size: Size of the virtual buffer
3083 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3084 * @list_type_opc: capabilities type to discover - pass in the command opcode
3085 * @cmd_details: pointer to command details structure or NULL
3086 *
3087 * Get the device capabilities descriptions from the firmware
3088 **/
i40e_aq_discover_capabilities(struct i40e_hw * hw,void * buff,u16 buff_size,u16 * data_size,enum i40e_admin_queue_opc list_type_opc,struct i40e_asq_cmd_details * cmd_details)3089 int i40e_aq_discover_capabilities(struct i40e_hw *hw,
3090 void *buff, u16 buff_size, u16 *data_size,
3091 enum i40e_admin_queue_opc list_type_opc,
3092 struct i40e_asq_cmd_details *cmd_details)
3093 {
3094 struct i40e_aqc_list_capabilites *cmd;
3095 struct i40e_aq_desc desc;
3096 int status = 0;
3097
3098 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3099
3100 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3101 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3102 status = -EINVAL;
3103 goto exit;
3104 }
3105
3106 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3107
3108 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3109 if (buff_size > I40E_AQ_LARGE_BUF)
3110 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3111
3112 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3113 *data_size = le16_to_cpu(desc.datalen);
3114
3115 if (status)
3116 goto exit;
3117
3118 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3119 list_type_opc);
3120
3121 exit:
3122 return status;
3123 }
3124
3125 /**
3126 * i40e_aq_update_nvm
3127 * @hw: pointer to the hw struct
3128 * @module_pointer: module pointer location in words from the NVM beginning
3129 * @offset: byte offset from the module beginning
3130 * @length: length of the section to be written (in bytes from the offset)
3131 * @data: command buffer (size [bytes] = length)
3132 * @last_command: tells if this is the last command in a series
3133 * @preservation_flags: Preservation mode flags
3134 * @cmd_details: pointer to command details structure or NULL
3135 *
3136 * Update the NVM using the admin queue commands
3137 **/
i40e_aq_update_nvm(struct i40e_hw * hw,u8 module_pointer,u32 offset,u16 length,void * data,bool last_command,u8 preservation_flags,struct i40e_asq_cmd_details * cmd_details)3138 int i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3139 u32 offset, u16 length, void *data,
3140 bool last_command, u8 preservation_flags,
3141 struct i40e_asq_cmd_details *cmd_details)
3142 {
3143 struct i40e_aq_desc desc;
3144 struct i40e_aqc_nvm_update *cmd =
3145 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3146 int status;
3147
3148 /* In offset the highest byte must be zeroed. */
3149 if (offset & 0xFF000000) {
3150 status = -EINVAL;
3151 goto i40e_aq_update_nvm_exit;
3152 }
3153
3154 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3155
3156 /* If this is the last command in a series, set the proper flag. */
3157 if (last_command)
3158 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3159 if (hw->mac.type == I40E_MAC_X722) {
3160 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3161 cmd->command_flags |=
3162 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3163 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3164 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3165 cmd->command_flags |=
3166 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3167 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3168 }
3169 cmd->module_pointer = module_pointer;
3170 cmd->offset = cpu_to_le32(offset);
3171 cmd->length = cpu_to_le16(length);
3172
3173 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3174 if (length > I40E_AQ_LARGE_BUF)
3175 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3176
3177 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3178
3179 i40e_aq_update_nvm_exit:
3180 return status;
3181 }
3182
3183 /**
3184 * i40e_aq_rearrange_nvm
3185 * @hw: pointer to the hw struct
3186 * @rearrange_nvm: defines direction of rearrangement
3187 * @cmd_details: pointer to command details structure or NULL
3188 *
3189 * Rearrange NVM structure, available only for transition FW
3190 **/
i40e_aq_rearrange_nvm(struct i40e_hw * hw,u8 rearrange_nvm,struct i40e_asq_cmd_details * cmd_details)3191 int i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3192 u8 rearrange_nvm,
3193 struct i40e_asq_cmd_details *cmd_details)
3194 {
3195 struct i40e_aqc_nvm_update *cmd;
3196 struct i40e_aq_desc desc;
3197 int status;
3198
3199 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3200
3201 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3202
3203 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3204 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3205
3206 if (!rearrange_nvm) {
3207 status = -EINVAL;
3208 goto i40e_aq_rearrange_nvm_exit;
3209 }
3210
3211 cmd->command_flags |= rearrange_nvm;
3212 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3213
3214 i40e_aq_rearrange_nvm_exit:
3215 return status;
3216 }
3217
3218 /**
3219 * i40e_aq_get_lldp_mib
3220 * @hw: pointer to the hw struct
3221 * @bridge_type: type of bridge requested
3222 * @mib_type: Local, Remote or both Local and Remote MIBs
3223 * @buff: pointer to a user supplied buffer to store the MIB block
3224 * @buff_size: size of the buffer (in bytes)
3225 * @local_len : length of the returned Local LLDP MIB
3226 * @remote_len: length of the returned Remote LLDP MIB
3227 * @cmd_details: pointer to command details structure or NULL
3228 *
3229 * Requests the complete LLDP MIB (entire packet).
3230 **/
i40e_aq_get_lldp_mib(struct i40e_hw * hw,u8 bridge_type,u8 mib_type,void * buff,u16 buff_size,u16 * local_len,u16 * remote_len,struct i40e_asq_cmd_details * cmd_details)3231 int i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3232 u8 mib_type, void *buff, u16 buff_size,
3233 u16 *local_len, u16 *remote_len,
3234 struct i40e_asq_cmd_details *cmd_details)
3235 {
3236 struct i40e_aq_desc desc;
3237 struct i40e_aqc_lldp_get_mib *cmd =
3238 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3239 struct i40e_aqc_lldp_get_mib *resp =
3240 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3241 int status;
3242
3243 if (buff_size == 0 || !buff)
3244 return -EINVAL;
3245
3246 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3247 /* Indirect Command */
3248 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3249
3250 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3251 cmd->type |= FIELD_PREP(I40E_AQ_LLDP_BRIDGE_TYPE_MASK, bridge_type);
3252
3253 desc.datalen = cpu_to_le16(buff_size);
3254
3255 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3256 if (buff_size > I40E_AQ_LARGE_BUF)
3257 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3258
3259 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3260 if (!status) {
3261 if (local_len != NULL)
3262 *local_len = le16_to_cpu(resp->local_len);
3263 if (remote_len != NULL)
3264 *remote_len = le16_to_cpu(resp->remote_len);
3265 }
3266
3267 return status;
3268 }
3269
3270 /**
3271 * i40e_aq_set_lldp_mib - Set the LLDP MIB
3272 * @hw: pointer to the hw struct
3273 * @mib_type: Local, Remote or both Local and Remote MIBs
3274 * @buff: pointer to a user supplied buffer to store the MIB block
3275 * @buff_size: size of the buffer (in bytes)
3276 * @cmd_details: pointer to command details structure or NULL
3277 *
3278 * Set the LLDP MIB.
3279 **/
3280 int
i40e_aq_set_lldp_mib(struct i40e_hw * hw,u8 mib_type,void * buff,u16 buff_size,struct i40e_asq_cmd_details * cmd_details)3281 i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3282 u8 mib_type, void *buff, u16 buff_size,
3283 struct i40e_asq_cmd_details *cmd_details)
3284 {
3285 struct i40e_aqc_lldp_set_local_mib *cmd;
3286 struct i40e_aq_desc desc;
3287 int status;
3288
3289 cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3290 if (buff_size == 0 || !buff)
3291 return -EINVAL;
3292
3293 i40e_fill_default_direct_cmd_desc(&desc,
3294 i40e_aqc_opc_lldp_set_local_mib);
3295 /* Indirect Command */
3296 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3297 if (buff_size > I40E_AQ_LARGE_BUF)
3298 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3299 desc.datalen = cpu_to_le16(buff_size);
3300
3301 cmd->type = mib_type;
3302 cmd->length = cpu_to_le16(buff_size);
3303 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff));
3304 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff));
3305
3306 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3307 return status;
3308 }
3309
3310 /**
3311 * i40e_aq_cfg_lldp_mib_change_event
3312 * @hw: pointer to the hw struct
3313 * @enable_update: Enable or Disable event posting
3314 * @cmd_details: pointer to command details structure or NULL
3315 *
3316 * Enable or Disable posting of an event on ARQ when LLDP MIB
3317 * associated with the interface changes
3318 **/
i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw * hw,bool enable_update,struct i40e_asq_cmd_details * cmd_details)3319 int i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3320 bool enable_update,
3321 struct i40e_asq_cmd_details *cmd_details)
3322 {
3323 struct i40e_aq_desc desc;
3324 struct i40e_aqc_lldp_update_mib *cmd =
3325 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3326 int status;
3327
3328 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3329
3330 if (!enable_update)
3331 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3332
3333 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3334
3335 return status;
3336 }
3337
3338 /**
3339 * i40e_aq_restore_lldp
3340 * @hw: pointer to the hw struct
3341 * @setting: pointer to factory setting variable or NULL
3342 * @restore: True if factory settings should be restored
3343 * @cmd_details: pointer to command details structure or NULL
3344 *
3345 * Restore LLDP Agent factory settings if @restore set to True. In other case
3346 * only returns factory setting in AQ response.
3347 **/
3348 int
i40e_aq_restore_lldp(struct i40e_hw * hw,u8 * setting,bool restore,struct i40e_asq_cmd_details * cmd_details)3349 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
3350 struct i40e_asq_cmd_details *cmd_details)
3351 {
3352 struct i40e_aq_desc desc;
3353 struct i40e_aqc_lldp_restore *cmd =
3354 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
3355 int status;
3356
3357 if (!test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps)) {
3358 i40e_debug(hw, I40E_DEBUG_ALL,
3359 "Restore LLDP not supported by current FW version.\n");
3360 return -ENODEV;
3361 }
3362
3363 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
3364
3365 if (restore)
3366 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
3367
3368 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3369
3370 if (setting)
3371 *setting = cmd->command & 1;
3372
3373 return status;
3374 }
3375
3376 /**
3377 * i40e_aq_stop_lldp
3378 * @hw: pointer to the hw struct
3379 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3380 * @persist: True if stop of LLDP should be persistent across power cycles
3381 * @cmd_details: pointer to command details structure or NULL
3382 *
3383 * Stop or Shutdown the embedded LLDP Agent
3384 **/
i40e_aq_stop_lldp(struct i40e_hw * hw,bool shutdown_agent,bool persist,struct i40e_asq_cmd_details * cmd_details)3385 int i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3386 bool persist,
3387 struct i40e_asq_cmd_details *cmd_details)
3388 {
3389 struct i40e_aq_desc desc;
3390 struct i40e_aqc_lldp_stop *cmd =
3391 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3392 int status;
3393
3394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3395
3396 if (shutdown_agent)
3397 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3398
3399 if (persist) {
3400 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps))
3401 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
3402 else
3403 i40e_debug(hw, I40E_DEBUG_ALL,
3404 "Persistent Stop LLDP not supported by current FW version.\n");
3405 }
3406
3407 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3408
3409 return status;
3410 }
3411
3412 /**
3413 * i40e_aq_start_lldp
3414 * @hw: pointer to the hw struct
3415 * @persist: True if start of LLDP should be persistent across power cycles
3416 * @cmd_details: pointer to command details structure or NULL
3417 *
3418 * Start the embedded LLDP Agent on all ports.
3419 **/
i40e_aq_start_lldp(struct i40e_hw * hw,bool persist,struct i40e_asq_cmd_details * cmd_details)3420 int i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
3421 struct i40e_asq_cmd_details *cmd_details)
3422 {
3423 struct i40e_aq_desc desc;
3424 struct i40e_aqc_lldp_start *cmd =
3425 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3426 int status;
3427
3428 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3429
3430 cmd->command = I40E_AQ_LLDP_AGENT_START;
3431
3432 if (persist) {
3433 if (test_bit(I40E_HW_CAP_FW_LLDP_PERSISTENT, hw->caps))
3434 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
3435 else
3436 i40e_debug(hw, I40E_DEBUG_ALL,
3437 "Persistent Start LLDP not supported by current FW version.\n");
3438 }
3439
3440 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3441
3442 return status;
3443 }
3444
3445 /**
3446 * i40e_aq_set_dcb_parameters
3447 * @hw: pointer to the hw struct
3448 * @cmd_details: pointer to command details structure or NULL
3449 * @dcb_enable: True if DCB configuration needs to be applied
3450 *
3451 **/
3452 int
i40e_aq_set_dcb_parameters(struct i40e_hw * hw,bool dcb_enable,struct i40e_asq_cmd_details * cmd_details)3453 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3454 struct i40e_asq_cmd_details *cmd_details)
3455 {
3456 struct i40e_aq_desc desc;
3457 struct i40e_aqc_set_dcb_parameters *cmd =
3458 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3459 int status;
3460
3461 if (!test_bit(I40E_HW_CAP_FW_LLDP_STOPPABLE, hw->caps))
3462 return -ENODEV;
3463
3464 i40e_fill_default_direct_cmd_desc(&desc,
3465 i40e_aqc_opc_set_dcb_parameters);
3466
3467 if (dcb_enable) {
3468 cmd->valid_flags = I40E_DCB_VALID;
3469 cmd->command = I40E_AQ_DCB_SET_AGENT;
3470 }
3471 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3472
3473 return status;
3474 }
3475
3476 /**
3477 * i40e_aq_get_cee_dcb_config
3478 * @hw: pointer to the hw struct
3479 * @buff: response buffer that stores CEE operational configuration
3480 * @buff_size: size of the buffer passed
3481 * @cmd_details: pointer to command details structure or NULL
3482 *
3483 * Get CEE DCBX mode operational configuration from firmware
3484 **/
i40e_aq_get_cee_dcb_config(struct i40e_hw * hw,void * buff,u16 buff_size,struct i40e_asq_cmd_details * cmd_details)3485 int i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3486 void *buff, u16 buff_size,
3487 struct i40e_asq_cmd_details *cmd_details)
3488 {
3489 struct i40e_aq_desc desc;
3490 int status;
3491
3492 if (buff_size == 0 || !buff)
3493 return -EINVAL;
3494
3495 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3496
3497 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3498 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3499 cmd_details);
3500
3501 return status;
3502 }
3503
3504 /**
3505 * i40e_aq_add_udp_tunnel
3506 * @hw: pointer to the hw struct
3507 * @udp_port: the UDP port to add in Host byte order
3508 * @protocol_index: protocol index type
3509 * @filter_index: pointer to filter index
3510 * @cmd_details: pointer to command details structure or NULL
3511 *
3512 * Note: Firmware expects the udp_port value to be in Little Endian format,
3513 * and this function will call cpu_to_le16 to convert from Host byte order to
3514 * Little Endian order.
3515 **/
i40e_aq_add_udp_tunnel(struct i40e_hw * hw,u16 udp_port,u8 protocol_index,u8 * filter_index,struct i40e_asq_cmd_details * cmd_details)3516 int i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3517 u16 udp_port, u8 protocol_index,
3518 u8 *filter_index,
3519 struct i40e_asq_cmd_details *cmd_details)
3520 {
3521 struct i40e_aq_desc desc;
3522 struct i40e_aqc_add_udp_tunnel *cmd =
3523 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3524 struct i40e_aqc_del_udp_tunnel_completion *resp =
3525 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3526 int status;
3527
3528 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3529
3530 cmd->udp_port = cpu_to_le16(udp_port);
3531 cmd->protocol_type = protocol_index;
3532
3533 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3534
3535 if (!status && filter_index)
3536 *filter_index = resp->index;
3537
3538 return status;
3539 }
3540
3541 /**
3542 * i40e_aq_del_udp_tunnel
3543 * @hw: pointer to the hw struct
3544 * @index: filter index
3545 * @cmd_details: pointer to command details structure or NULL
3546 **/
i40e_aq_del_udp_tunnel(struct i40e_hw * hw,u8 index,struct i40e_asq_cmd_details * cmd_details)3547 int i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3548 struct i40e_asq_cmd_details *cmd_details)
3549 {
3550 struct i40e_aq_desc desc;
3551 struct i40e_aqc_remove_udp_tunnel *cmd =
3552 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3553 int status;
3554
3555 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3556
3557 cmd->index = index;
3558
3559 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3560
3561 return status;
3562 }
3563
3564 /**
3565 * i40e_aq_delete_element - Delete switch element
3566 * @hw: pointer to the hw struct
3567 * @seid: the SEID to delete from the switch
3568 * @cmd_details: pointer to command details structure or NULL
3569 *
3570 * This deletes a switch element from the switch.
3571 **/
i40e_aq_delete_element(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)3572 int i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3573 struct i40e_asq_cmd_details *cmd_details)
3574 {
3575 struct i40e_aq_desc desc;
3576 struct i40e_aqc_switch_seid *cmd =
3577 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3578 int status;
3579
3580 if (seid == 0)
3581 return -EINVAL;
3582
3583 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3584
3585 cmd->seid = cpu_to_le16(seid);
3586
3587 status = i40e_asq_send_command_atomic(hw, &desc, NULL, 0,
3588 cmd_details, true);
3589
3590 return status;
3591 }
3592
3593 /**
3594 * i40e_aq_dcb_updated - DCB Updated Command
3595 * @hw: pointer to the hw struct
3596 * @cmd_details: pointer to command details structure or NULL
3597 *
3598 * EMP will return when the shared RPB settings have been
3599 * recomputed and modified. The retval field in the descriptor
3600 * will be set to 0 when RPB is modified.
3601 **/
i40e_aq_dcb_updated(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)3602 int i40e_aq_dcb_updated(struct i40e_hw *hw,
3603 struct i40e_asq_cmd_details *cmd_details)
3604 {
3605 struct i40e_aq_desc desc;
3606 int status;
3607
3608 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3609
3610 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3611
3612 return status;
3613 }
3614
3615 /**
3616 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3617 * @hw: pointer to the hw struct
3618 * @seid: seid for the physical port/switching component/vsi
3619 * @buff: Indirect buffer to hold data parameters and response
3620 * @buff_size: Indirect buffer size
3621 * @opcode: Tx scheduler AQ command opcode
3622 * @cmd_details: pointer to command details structure or NULL
3623 *
3624 * Generic command handler for Tx scheduler AQ commands
3625 **/
i40e_aq_tx_sched_cmd(struct i40e_hw * hw,u16 seid,void * buff,u16 buff_size,enum i40e_admin_queue_opc opcode,struct i40e_asq_cmd_details * cmd_details)3626 static int i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3627 void *buff, u16 buff_size,
3628 enum i40e_admin_queue_opc opcode,
3629 struct i40e_asq_cmd_details *cmd_details)
3630 {
3631 struct i40e_aq_desc desc;
3632 struct i40e_aqc_tx_sched_ind *cmd =
3633 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3634 int status;
3635 bool cmd_param_flag = false;
3636
3637 switch (opcode) {
3638 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3639 case i40e_aqc_opc_configure_vsi_tc_bw:
3640 case i40e_aqc_opc_enable_switching_comp_ets:
3641 case i40e_aqc_opc_modify_switching_comp_ets:
3642 case i40e_aqc_opc_disable_switching_comp_ets:
3643 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3644 case i40e_aqc_opc_configure_switching_comp_bw_config:
3645 cmd_param_flag = true;
3646 break;
3647 case i40e_aqc_opc_query_vsi_bw_config:
3648 case i40e_aqc_opc_query_vsi_ets_sla_config:
3649 case i40e_aqc_opc_query_switching_comp_ets_config:
3650 case i40e_aqc_opc_query_port_ets_config:
3651 case i40e_aqc_opc_query_switching_comp_bw_config:
3652 cmd_param_flag = false;
3653 break;
3654 default:
3655 return -EINVAL;
3656 }
3657
3658 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3659
3660 /* Indirect command */
3661 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3662 if (cmd_param_flag)
3663 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3664 if (buff_size > I40E_AQ_LARGE_BUF)
3665 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3666
3667 desc.datalen = cpu_to_le16(buff_size);
3668
3669 cmd->vsi_seid = cpu_to_le16(seid);
3670
3671 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3672
3673 return status;
3674 }
3675
3676 /**
3677 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3678 * @hw: pointer to the hw struct
3679 * @seid: VSI seid
3680 * @credit: BW limit credits (0 = disabled)
3681 * @max_credit: Max BW limit credits
3682 * @cmd_details: pointer to command details structure or NULL
3683 **/
i40e_aq_config_vsi_bw_limit(struct i40e_hw * hw,u16 seid,u16 credit,u8 max_credit,struct i40e_asq_cmd_details * cmd_details)3684 int i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3685 u16 seid, u16 credit, u8 max_credit,
3686 struct i40e_asq_cmd_details *cmd_details)
3687 {
3688 struct i40e_aq_desc desc;
3689 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3690 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3691 int status;
3692
3693 i40e_fill_default_direct_cmd_desc(&desc,
3694 i40e_aqc_opc_configure_vsi_bw_limit);
3695
3696 cmd->vsi_seid = cpu_to_le16(seid);
3697 cmd->credit = cpu_to_le16(credit);
3698 cmd->max_credit = max_credit;
3699
3700 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3701
3702 return status;
3703 }
3704
3705 /**
3706 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3707 * @hw: pointer to the hw struct
3708 * @seid: VSI seid
3709 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3710 * @cmd_details: pointer to command details structure or NULL
3711 **/
i40e_aq_config_vsi_tc_bw(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_vsi_tc_bw_data * bw_data,struct i40e_asq_cmd_details * cmd_details)3712 int i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3713 u16 seid,
3714 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3715 struct i40e_asq_cmd_details *cmd_details)
3716 {
3717 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3718 i40e_aqc_opc_configure_vsi_tc_bw,
3719 cmd_details);
3720 }
3721
3722 /**
3723 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3724 * @hw: pointer to the hw struct
3725 * @seid: seid of the switching component connected to Physical Port
3726 * @ets_data: Buffer holding ETS parameters
3727 * @opcode: Tx scheduler AQ command opcode
3728 * @cmd_details: pointer to command details structure or NULL
3729 **/
3730 int
i40e_aq_config_switch_comp_ets(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_switching_comp_ets_data * ets_data,enum i40e_admin_queue_opc opcode,struct i40e_asq_cmd_details * cmd_details)3731 i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3732 u16 seid,
3733 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3734 enum i40e_admin_queue_opc opcode,
3735 struct i40e_asq_cmd_details *cmd_details)
3736 {
3737 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3738 sizeof(*ets_data), opcode, cmd_details);
3739 }
3740
3741 /**
3742 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3743 * @hw: pointer to the hw struct
3744 * @seid: seid of the switching component
3745 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3746 * @cmd_details: pointer to command details structure or NULL
3747 **/
3748 int
i40e_aq_config_switch_comp_bw_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_configure_switching_comp_bw_config_data * bw_data,struct i40e_asq_cmd_details * cmd_details)3749 i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3750 u16 seid,
3751 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3752 struct i40e_asq_cmd_details *cmd_details)
3753 {
3754 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3755 i40e_aqc_opc_configure_switching_comp_bw_config,
3756 cmd_details);
3757 }
3758
3759 /**
3760 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3761 * @hw: pointer to the hw struct
3762 * @seid: seid of the VSI
3763 * @bw_data: Buffer to hold VSI BW configuration
3764 * @cmd_details: pointer to command details structure or NULL
3765 **/
3766 int
i40e_aq_query_vsi_bw_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_vsi_bw_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)3767 i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3768 u16 seid,
3769 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3770 struct i40e_asq_cmd_details *cmd_details)
3771 {
3772 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3773 i40e_aqc_opc_query_vsi_bw_config,
3774 cmd_details);
3775 }
3776
3777 /**
3778 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3779 * @hw: pointer to the hw struct
3780 * @seid: seid of the VSI
3781 * @bw_data: Buffer to hold VSI BW configuration per TC
3782 * @cmd_details: pointer to command details structure or NULL
3783 **/
3784 int
i40e_aq_query_vsi_ets_sla_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_vsi_ets_sla_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)3785 i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3786 u16 seid,
3787 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3788 struct i40e_asq_cmd_details *cmd_details)
3789 {
3790 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3791 i40e_aqc_opc_query_vsi_ets_sla_config,
3792 cmd_details);
3793 }
3794
3795 /**
3796 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3797 * @hw: pointer to the hw struct
3798 * @seid: seid of the switching component
3799 * @bw_data: Buffer to hold switching component's per TC BW config
3800 * @cmd_details: pointer to command details structure or NULL
3801 **/
3802 int
i40e_aq_query_switch_comp_ets_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_switching_comp_ets_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)3803 i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3804 u16 seid,
3805 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3806 struct i40e_asq_cmd_details *cmd_details)
3807 {
3808 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3809 i40e_aqc_opc_query_switching_comp_ets_config,
3810 cmd_details);
3811 }
3812
3813 /**
3814 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3815 * @hw: pointer to the hw struct
3816 * @seid: seid of the VSI or switching component connected to Physical Port
3817 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3818 * @cmd_details: pointer to command details structure or NULL
3819 **/
3820 int
i40e_aq_query_port_ets_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_port_ets_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)3821 i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3822 u16 seid,
3823 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3824 struct i40e_asq_cmd_details *cmd_details)
3825 {
3826 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3827 i40e_aqc_opc_query_port_ets_config,
3828 cmd_details);
3829 }
3830
3831 /**
3832 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3833 * @hw: pointer to the hw struct
3834 * @seid: seid of the switching component
3835 * @bw_data: Buffer to hold switching component's BW configuration
3836 * @cmd_details: pointer to command details structure or NULL
3837 **/
3838 int
i40e_aq_query_switch_comp_bw_config(struct i40e_hw * hw,u16 seid,struct i40e_aqc_query_switching_comp_bw_config_resp * bw_data,struct i40e_asq_cmd_details * cmd_details)3839 i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3840 u16 seid,
3841 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3842 struct i40e_asq_cmd_details *cmd_details)
3843 {
3844 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3845 i40e_aqc_opc_query_switching_comp_bw_config,
3846 cmd_details);
3847 }
3848
3849 /**
3850 * i40e_validate_filter_settings
3851 * @hw: pointer to the hardware structure
3852 * @settings: Filter control settings
3853 *
3854 * Check and validate the filter control settings passed.
3855 * The function checks for the valid filter/context sizes being
3856 * passed for FCoE and PE.
3857 *
3858 * Returns 0 if the values passed are valid and within
3859 * range else returns an error.
3860 **/
3861 static int
i40e_validate_filter_settings(struct i40e_hw * hw,struct i40e_filter_control_settings * settings)3862 i40e_validate_filter_settings(struct i40e_hw *hw,
3863 struct i40e_filter_control_settings *settings)
3864 {
3865 u32 fcoe_cntx_size, fcoe_filt_size;
3866 u32 fcoe_fmax;
3867 u32 val;
3868
3869 /* Validate FCoE settings passed */
3870 switch (settings->fcoe_filt_num) {
3871 case I40E_HASH_FILTER_SIZE_1K:
3872 case I40E_HASH_FILTER_SIZE_2K:
3873 case I40E_HASH_FILTER_SIZE_4K:
3874 case I40E_HASH_FILTER_SIZE_8K:
3875 case I40E_HASH_FILTER_SIZE_16K:
3876 case I40E_HASH_FILTER_SIZE_32K:
3877 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3878 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3879 break;
3880 default:
3881 return -EINVAL;
3882 }
3883
3884 switch (settings->fcoe_cntx_num) {
3885 case I40E_DMA_CNTX_SIZE_512:
3886 case I40E_DMA_CNTX_SIZE_1K:
3887 case I40E_DMA_CNTX_SIZE_2K:
3888 case I40E_DMA_CNTX_SIZE_4K:
3889 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3890 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3891 break;
3892 default:
3893 return -EINVAL;
3894 }
3895
3896 /* Validate PE settings passed */
3897 switch (settings->pe_filt_num) {
3898 case I40E_HASH_FILTER_SIZE_1K:
3899 case I40E_HASH_FILTER_SIZE_2K:
3900 case I40E_HASH_FILTER_SIZE_4K:
3901 case I40E_HASH_FILTER_SIZE_8K:
3902 case I40E_HASH_FILTER_SIZE_16K:
3903 case I40E_HASH_FILTER_SIZE_32K:
3904 case I40E_HASH_FILTER_SIZE_64K:
3905 case I40E_HASH_FILTER_SIZE_128K:
3906 case I40E_HASH_FILTER_SIZE_256K:
3907 case I40E_HASH_FILTER_SIZE_512K:
3908 case I40E_HASH_FILTER_SIZE_1M:
3909 break;
3910 default:
3911 return -EINVAL;
3912 }
3913
3914 switch (settings->pe_cntx_num) {
3915 case I40E_DMA_CNTX_SIZE_512:
3916 case I40E_DMA_CNTX_SIZE_1K:
3917 case I40E_DMA_CNTX_SIZE_2K:
3918 case I40E_DMA_CNTX_SIZE_4K:
3919 case I40E_DMA_CNTX_SIZE_8K:
3920 case I40E_DMA_CNTX_SIZE_16K:
3921 case I40E_DMA_CNTX_SIZE_32K:
3922 case I40E_DMA_CNTX_SIZE_64K:
3923 case I40E_DMA_CNTX_SIZE_128K:
3924 case I40E_DMA_CNTX_SIZE_256K:
3925 break;
3926 default:
3927 return -EINVAL;
3928 }
3929
3930 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
3931 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3932 fcoe_fmax = FIELD_GET(I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK, val);
3933 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3934 return -EINVAL;
3935
3936 return 0;
3937 }
3938
3939 /**
3940 * i40e_set_filter_control
3941 * @hw: pointer to the hardware structure
3942 * @settings: Filter control settings
3943 *
3944 * Set the Queue Filters for PE/FCoE and enable filters required
3945 * for a single PF. It is expected that these settings are programmed
3946 * at the driver initialization time.
3947 **/
i40e_set_filter_control(struct i40e_hw * hw,struct i40e_filter_control_settings * settings)3948 int i40e_set_filter_control(struct i40e_hw *hw,
3949 struct i40e_filter_control_settings *settings)
3950 {
3951 u32 hash_lut_size = 0;
3952 int ret = 0;
3953 u32 val;
3954
3955 if (!settings)
3956 return -EINVAL;
3957
3958 /* Validate the input settings */
3959 ret = i40e_validate_filter_settings(hw, settings);
3960 if (ret)
3961 return ret;
3962
3963 /* Read the PF Queue Filter control register */
3964 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
3965
3966 /* Program required PE hash buckets for the PF */
3967 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3968 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEHSIZE_MASK, settings->pe_filt_num);
3969 /* Program required PE contexts for the PF */
3970 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3971 val |= FIELD_PREP(I40E_PFQF_CTL_0_PEDSIZE_MASK, settings->pe_cntx_num);
3972
3973 /* Program required FCoE hash buckets for the PF */
3974 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3975 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCHSIZE_MASK,
3976 settings->fcoe_filt_num);
3977 /* Program required FCoE DDP contexts for the PF */
3978 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3979 val |= FIELD_PREP(I40E_PFQF_CTL_0_PFFCDSIZE_MASK,
3980 settings->fcoe_cntx_num);
3981
3982 /* Program Hash LUT size for the PF */
3983 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3984 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3985 hash_lut_size = 1;
3986 val |= FIELD_PREP(I40E_PFQF_CTL_0_HASHLUTSIZE_MASK, hash_lut_size);
3987
3988 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
3989 if (settings->enable_fdir)
3990 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3991 if (settings->enable_ethtype)
3992 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3993 if (settings->enable_macvlan)
3994 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3995
3996 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
3997
3998 return 0;
3999 }
4000
4001 /**
4002 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4003 * @hw: pointer to the hw struct
4004 * @mac_addr: MAC address to use in the filter
4005 * @ethtype: Ethertype to use in the filter
4006 * @flags: Flags that needs to be applied to the filter
4007 * @vsi_seid: seid of the control VSI
4008 * @queue: VSI queue number to send the packet to
4009 * @is_add: Add control packet filter if True else remove
4010 * @stats: Structure to hold information on control filter counts
4011 * @cmd_details: pointer to command details structure or NULL
4012 *
4013 * This command will Add or Remove control packet filter for a control VSI.
4014 * In return it will update the total number of perfect filter count in
4015 * the stats member.
4016 **/
i40e_aq_add_rem_control_packet_filter(struct i40e_hw * hw,u8 * mac_addr,u16 ethtype,u16 flags,u16 vsi_seid,u16 queue,bool is_add,struct i40e_control_filter_stats * stats,struct i40e_asq_cmd_details * cmd_details)4017 int i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4018 u8 *mac_addr, u16 ethtype, u16 flags,
4019 u16 vsi_seid, u16 queue, bool is_add,
4020 struct i40e_control_filter_stats *stats,
4021 struct i40e_asq_cmd_details *cmd_details)
4022 {
4023 struct i40e_aq_desc desc;
4024 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4025 (struct i40e_aqc_add_remove_control_packet_filter *)
4026 &desc.params.raw;
4027 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4028 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4029 &desc.params.raw;
4030 int status;
4031
4032 if (vsi_seid == 0)
4033 return -EINVAL;
4034
4035 if (is_add) {
4036 i40e_fill_default_direct_cmd_desc(&desc,
4037 i40e_aqc_opc_add_control_packet_filter);
4038 cmd->queue = cpu_to_le16(queue);
4039 } else {
4040 i40e_fill_default_direct_cmd_desc(&desc,
4041 i40e_aqc_opc_remove_control_packet_filter);
4042 }
4043
4044 if (mac_addr)
4045 ether_addr_copy(cmd->mac, mac_addr);
4046
4047 cmd->etype = cpu_to_le16(ethtype);
4048 cmd->flags = cpu_to_le16(flags);
4049 cmd->seid = cpu_to_le16(vsi_seid);
4050
4051 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4052
4053 if (!status && stats) {
4054 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4055 stats->etype_used = le16_to_cpu(resp->etype_used);
4056 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4057 stats->etype_free = le16_to_cpu(resp->etype_free);
4058 }
4059
4060 return status;
4061 }
4062
4063 /**
4064 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4065 * @hw: pointer to the hw struct
4066 * @seid: VSI seid to add ethertype filter from
4067 **/
i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw * hw,u16 seid)4068 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4069 u16 seid)
4070 {
4071 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4072 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4073 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4074 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4075 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4076 int status;
4077
4078 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4079 seid, 0, true, NULL,
4080 NULL);
4081 if (status)
4082 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4083 }
4084
4085 /**
4086 * i40e_aq_alternate_read
4087 * @hw: pointer to the hardware structure
4088 * @reg_addr0: address of first dword to be read
4089 * @reg_val0: pointer for data read from 'reg_addr0'
4090 * @reg_addr1: address of second dword to be read
4091 * @reg_val1: pointer for data read from 'reg_addr1'
4092 *
4093 * Read one or two dwords from alternate structure. Fields are indicated
4094 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4095 * is not passed then only register at 'reg_addr0' is read.
4096 *
4097 **/
i40e_aq_alternate_read(struct i40e_hw * hw,u32 reg_addr0,u32 * reg_val0,u32 reg_addr1,u32 * reg_val1)4098 static int i40e_aq_alternate_read(struct i40e_hw *hw,
4099 u32 reg_addr0, u32 *reg_val0,
4100 u32 reg_addr1, u32 *reg_val1)
4101 {
4102 struct i40e_aq_desc desc;
4103 struct i40e_aqc_alternate_write *cmd_resp =
4104 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4105 int status;
4106
4107 if (!reg_val0)
4108 return -EINVAL;
4109
4110 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4111 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4112 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4113
4114 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4115
4116 if (!status) {
4117 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4118
4119 if (reg_val1)
4120 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4121 }
4122
4123 return status;
4124 }
4125
4126 /**
4127 * i40e_aq_suspend_port_tx
4128 * @hw: pointer to the hardware structure
4129 * @seid: port seid
4130 * @cmd_details: pointer to command details structure or NULL
4131 *
4132 * Suspend port's Tx traffic
4133 **/
i40e_aq_suspend_port_tx(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)4134 int i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
4135 struct i40e_asq_cmd_details *cmd_details)
4136 {
4137 struct i40e_aqc_tx_sched_ind *cmd;
4138 struct i40e_aq_desc desc;
4139 int status;
4140
4141 cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4142 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx);
4143 cmd->vsi_seid = cpu_to_le16(seid);
4144 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4145
4146 return status;
4147 }
4148
4149 /**
4150 * i40e_aq_resume_port_tx
4151 * @hw: pointer to the hardware structure
4152 * @cmd_details: pointer to command details structure or NULL
4153 *
4154 * Resume port's Tx traffic
4155 **/
i40e_aq_resume_port_tx(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)4156 int i40e_aq_resume_port_tx(struct i40e_hw *hw,
4157 struct i40e_asq_cmd_details *cmd_details)
4158 {
4159 struct i40e_aq_desc desc;
4160 int status;
4161
4162 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4163
4164 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4165
4166 return status;
4167 }
4168
4169 /**
4170 * i40e_set_pci_config_data - store PCI bus info
4171 * @hw: pointer to hardware structure
4172 * @link_status: the link status word from PCI config space
4173 *
4174 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4175 **/
i40e_set_pci_config_data(struct i40e_hw * hw,u16 link_status)4176 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4177 {
4178 hw->bus.type = i40e_bus_type_pci_express;
4179
4180 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4181 case PCI_EXP_LNKSTA_NLW_X1:
4182 hw->bus.width = i40e_bus_width_pcie_x1;
4183 break;
4184 case PCI_EXP_LNKSTA_NLW_X2:
4185 hw->bus.width = i40e_bus_width_pcie_x2;
4186 break;
4187 case PCI_EXP_LNKSTA_NLW_X4:
4188 hw->bus.width = i40e_bus_width_pcie_x4;
4189 break;
4190 case PCI_EXP_LNKSTA_NLW_X8:
4191 hw->bus.width = i40e_bus_width_pcie_x8;
4192 break;
4193 default:
4194 hw->bus.width = i40e_bus_width_unknown;
4195 break;
4196 }
4197
4198 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4199 case PCI_EXP_LNKSTA_CLS_2_5GB:
4200 hw->bus.speed = i40e_bus_speed_2500;
4201 break;
4202 case PCI_EXP_LNKSTA_CLS_5_0GB:
4203 hw->bus.speed = i40e_bus_speed_5000;
4204 break;
4205 case PCI_EXP_LNKSTA_CLS_8_0GB:
4206 hw->bus.speed = i40e_bus_speed_8000;
4207 break;
4208 default:
4209 hw->bus.speed = i40e_bus_speed_unknown;
4210 break;
4211 }
4212 }
4213
4214 /**
4215 * i40e_aq_debug_dump
4216 * @hw: pointer to the hardware structure
4217 * @cluster_id: specific cluster to dump
4218 * @table_id: table id within cluster
4219 * @start_index: index of line in the block to read
4220 * @buff_size: dump buffer size
4221 * @buff: dump buffer
4222 * @ret_buff_size: actual buffer size returned
4223 * @ret_next_table: next block to read
4224 * @ret_next_index: next index to read
4225 * @cmd_details: pointer to command details structure or NULL
4226 *
4227 * Dump internal FW/HW data for debug purposes.
4228 *
4229 **/
i40e_aq_debug_dump(struct i40e_hw * hw,u8 cluster_id,u8 table_id,u32 start_index,u16 buff_size,void * buff,u16 * ret_buff_size,u8 * ret_next_table,u32 * ret_next_index,struct i40e_asq_cmd_details * cmd_details)4230 int i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4231 u8 table_id, u32 start_index, u16 buff_size,
4232 void *buff, u16 *ret_buff_size,
4233 u8 *ret_next_table, u32 *ret_next_index,
4234 struct i40e_asq_cmd_details *cmd_details)
4235 {
4236 struct i40e_aq_desc desc;
4237 struct i40e_aqc_debug_dump_internals *cmd =
4238 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4239 struct i40e_aqc_debug_dump_internals *resp =
4240 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4241 int status;
4242
4243 if (buff_size == 0 || !buff)
4244 return -EINVAL;
4245
4246 i40e_fill_default_direct_cmd_desc(&desc,
4247 i40e_aqc_opc_debug_dump_internals);
4248 /* Indirect Command */
4249 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4250 if (buff_size > I40E_AQ_LARGE_BUF)
4251 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4252
4253 cmd->cluster_id = cluster_id;
4254 cmd->table_id = table_id;
4255 cmd->idx = cpu_to_le32(start_index);
4256
4257 desc.datalen = cpu_to_le16(buff_size);
4258
4259 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4260 if (!status) {
4261 if (ret_buff_size)
4262 *ret_buff_size = le16_to_cpu(desc.datalen);
4263 if (ret_next_table)
4264 *ret_next_table = resp->table_id;
4265 if (ret_next_index)
4266 *ret_next_index = le32_to_cpu(resp->idx);
4267 }
4268
4269 return status;
4270 }
4271
4272 /**
4273 * i40e_read_bw_from_alt_ram
4274 * @hw: pointer to the hardware structure
4275 * @max_bw: pointer for max_bw read
4276 * @min_bw: pointer for min_bw read
4277 * @min_valid: pointer for bool that is true if min_bw is a valid value
4278 * @max_valid: pointer for bool that is true if max_bw is a valid value
4279 *
4280 * Read bw from the alternate ram for the given pf
4281 **/
i40e_read_bw_from_alt_ram(struct i40e_hw * hw,u32 * max_bw,u32 * min_bw,bool * min_valid,bool * max_valid)4282 int i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4283 u32 *max_bw, u32 *min_bw,
4284 bool *min_valid, bool *max_valid)
4285 {
4286 u32 max_bw_addr, min_bw_addr;
4287 int status;
4288
4289 /* Calculate the address of the min/max bw registers */
4290 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4291 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4292 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4293 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4294 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4295 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4296
4297 /* Read the bandwidths from alt ram */
4298 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4299 min_bw_addr, min_bw);
4300
4301 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4302 *min_valid = true;
4303 else
4304 *min_valid = false;
4305
4306 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4307 *max_valid = true;
4308 else
4309 *max_valid = false;
4310
4311 return status;
4312 }
4313
4314 /**
4315 * i40e_aq_configure_partition_bw
4316 * @hw: pointer to the hardware structure
4317 * @bw_data: Buffer holding valid pfs and bw limits
4318 * @cmd_details: pointer to command details
4319 *
4320 * Configure partitions guaranteed/max bw
4321 **/
4322 int
i40e_aq_configure_partition_bw(struct i40e_hw * hw,struct i40e_aqc_configure_partition_bw_data * bw_data,struct i40e_asq_cmd_details * cmd_details)4323 i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4324 struct i40e_aqc_configure_partition_bw_data *bw_data,
4325 struct i40e_asq_cmd_details *cmd_details)
4326 {
4327 u16 bwd_size = sizeof(*bw_data);
4328 struct i40e_aq_desc desc;
4329 int status;
4330
4331 i40e_fill_default_direct_cmd_desc(&desc,
4332 i40e_aqc_opc_configure_partition_bw);
4333
4334 /* Indirect command */
4335 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4336 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4337
4338 if (bwd_size > I40E_AQ_LARGE_BUF)
4339 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4340
4341 desc.datalen = cpu_to_le16(bwd_size);
4342
4343 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4344 cmd_details);
4345
4346 return status;
4347 }
4348
4349 /**
4350 * i40e_read_phy_register_clause22
4351 * @hw: pointer to the HW structure
4352 * @reg: register address in the page
4353 * @phy_addr: PHY address on MDIO interface
4354 * @value: PHY register value
4355 *
4356 * Reads specified PHY register value
4357 **/
i40e_read_phy_register_clause22(struct i40e_hw * hw,u16 reg,u8 phy_addr,u16 * value)4358 int i40e_read_phy_register_clause22(struct i40e_hw *hw,
4359 u16 reg, u8 phy_addr, u16 *value)
4360 {
4361 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4362 int status = -EIO;
4363 u32 command = 0;
4364 u16 retry = 1000;
4365
4366 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4367 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4368 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4369 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4370 (I40E_GLGEN_MSCA_MDICMD_MASK);
4371 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4372 do {
4373 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4374 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4375 status = 0;
4376 break;
4377 }
4378 udelay(10);
4379 retry--;
4380 } while (retry);
4381
4382 if (status) {
4383 i40e_debug(hw, I40E_DEBUG_PHY,
4384 "PHY: Can't write command to external PHY.\n");
4385 } else {
4386 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4387 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);
4388 }
4389
4390 return status;
4391 }
4392
4393 /**
4394 * i40e_write_phy_register_clause22
4395 * @hw: pointer to the HW structure
4396 * @reg: register address in the page
4397 * @phy_addr: PHY address on MDIO interface
4398 * @value: PHY register value
4399 *
4400 * Writes specified PHY register value
4401 **/
i40e_write_phy_register_clause22(struct i40e_hw * hw,u16 reg,u8 phy_addr,u16 value)4402 int i40e_write_phy_register_clause22(struct i40e_hw *hw,
4403 u16 reg, u8 phy_addr, u16 value)
4404 {
4405 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4406 int status = -EIO;
4407 u32 command = 0;
4408 u16 retry = 1000;
4409
4410 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4411 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4412
4413 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4414 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4415 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4416 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4417 (I40E_GLGEN_MSCA_MDICMD_MASK);
4418
4419 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4420 do {
4421 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4422 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4423 status = 0;
4424 break;
4425 }
4426 udelay(10);
4427 retry--;
4428 } while (retry);
4429
4430 return status;
4431 }
4432
4433 /**
4434 * i40e_read_phy_register_clause45
4435 * @hw: pointer to the HW structure
4436 * @page: registers page number
4437 * @reg: register address in the page
4438 * @phy_addr: PHY address on MDIO interface
4439 * @value: PHY register value
4440 *
4441 * Reads specified PHY register value
4442 **/
i40e_read_phy_register_clause45(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 * value)4443 int i40e_read_phy_register_clause45(struct i40e_hw *hw,
4444 u8 page, u16 reg, u8 phy_addr, u16 *value)
4445 {
4446 u8 port_num = hw->func_caps.mdio_port_num;
4447 int status = -EIO;
4448 u32 command = 0;
4449 u16 retry = 1000;
4450
4451 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4452 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4453 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4454 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4455 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4456 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4457 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4458 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4459 do {
4460 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4461 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4462 status = 0;
4463 break;
4464 }
4465 usleep_range(10, 20);
4466 retry--;
4467 } while (retry);
4468
4469 if (status) {
4470 i40e_debug(hw, I40E_DEBUG_PHY,
4471 "PHY: Can't write command to external PHY.\n");
4472 goto phy_read_end;
4473 }
4474
4475 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4476 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4477 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4478 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4479 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4480 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4481 status = -EIO;
4482 retry = 1000;
4483 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4484 do {
4485 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4486 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4487 status = 0;
4488 break;
4489 }
4490 usleep_range(10, 20);
4491 retry--;
4492 } while (retry);
4493
4494 if (!status) {
4495 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4496 *value = FIELD_GET(I40E_GLGEN_MSRWD_MDIRDDATA_MASK, command);
4497 } else {
4498 i40e_debug(hw, I40E_DEBUG_PHY,
4499 "PHY: Can't read register value from external PHY.\n");
4500 }
4501
4502 phy_read_end:
4503 return status;
4504 }
4505
4506 /**
4507 * i40e_write_phy_register_clause45
4508 * @hw: pointer to the HW structure
4509 * @page: registers page number
4510 * @reg: register address in the page
4511 * @phy_addr: PHY address on MDIO interface
4512 * @value: PHY register value
4513 *
4514 * Writes value to specified PHY register
4515 **/
i40e_write_phy_register_clause45(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 value)4516 int i40e_write_phy_register_clause45(struct i40e_hw *hw,
4517 u8 page, u16 reg, u8 phy_addr, u16 value)
4518 {
4519 u8 port_num = hw->func_caps.mdio_port_num;
4520 int status = -EIO;
4521 u16 retry = 1000;
4522 u32 command = 0;
4523
4524 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4525 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4526 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4527 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4528 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4529 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4530 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4531 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4532 do {
4533 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4534 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4535 status = 0;
4536 break;
4537 }
4538 usleep_range(10, 20);
4539 retry--;
4540 } while (retry);
4541 if (status) {
4542 i40e_debug(hw, I40E_DEBUG_PHY,
4543 "PHY: Can't write command to external PHY.\n");
4544 goto phy_write_end;
4545 }
4546
4547 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4548 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4549
4550 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4551 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4552 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4553 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4554 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4555 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4556 status = -EIO;
4557 retry = 1000;
4558 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4559 do {
4560 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4561 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4562 status = 0;
4563 break;
4564 }
4565 usleep_range(10, 20);
4566 retry--;
4567 } while (retry);
4568
4569 phy_write_end:
4570 return status;
4571 }
4572
4573 /**
4574 * i40e_write_phy_register
4575 * @hw: pointer to the HW structure
4576 * @page: registers page number
4577 * @reg: register address in the page
4578 * @phy_addr: PHY address on MDIO interface
4579 * @value: PHY register value
4580 *
4581 * Writes value to specified PHY register
4582 **/
i40e_write_phy_register(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 value)4583 int i40e_write_phy_register(struct i40e_hw *hw,
4584 u8 page, u16 reg, u8 phy_addr, u16 value)
4585 {
4586 int status;
4587
4588 switch (hw->device_id) {
4589 case I40E_DEV_ID_1G_BASE_T_X722:
4590 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4591 value);
4592 break;
4593 case I40E_DEV_ID_1G_BASE_T_BC:
4594 case I40E_DEV_ID_5G_BASE_T_BC:
4595 case I40E_DEV_ID_10G_BASE_T:
4596 case I40E_DEV_ID_10G_BASE_T4:
4597 case I40E_DEV_ID_10G_BASE_T_BC:
4598 case I40E_DEV_ID_10G_BASE_T_X722:
4599 case I40E_DEV_ID_25G_B:
4600 case I40E_DEV_ID_25G_SFP28:
4601 status = i40e_write_phy_register_clause45(hw, page, reg,
4602 phy_addr, value);
4603 break;
4604 default:
4605 status = -EIO;
4606 break;
4607 }
4608
4609 return status;
4610 }
4611
4612 /**
4613 * i40e_read_phy_register
4614 * @hw: pointer to the HW structure
4615 * @page: registers page number
4616 * @reg: register address in the page
4617 * @phy_addr: PHY address on MDIO interface
4618 * @value: PHY register value
4619 *
4620 * Reads specified PHY register value
4621 **/
i40e_read_phy_register(struct i40e_hw * hw,u8 page,u16 reg,u8 phy_addr,u16 * value)4622 int i40e_read_phy_register(struct i40e_hw *hw,
4623 u8 page, u16 reg, u8 phy_addr, u16 *value)
4624 {
4625 int status;
4626
4627 switch (hw->device_id) {
4628 case I40E_DEV_ID_1G_BASE_T_X722:
4629 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4630 value);
4631 break;
4632 case I40E_DEV_ID_1G_BASE_T_BC:
4633 case I40E_DEV_ID_5G_BASE_T_BC:
4634 case I40E_DEV_ID_10G_BASE_T:
4635 case I40E_DEV_ID_10G_BASE_T4:
4636 case I40E_DEV_ID_10G_BASE_T_BC:
4637 case I40E_DEV_ID_10G_BASE_T_X722:
4638 case I40E_DEV_ID_25G_B:
4639 case I40E_DEV_ID_25G_SFP28:
4640 status = i40e_read_phy_register_clause45(hw, page, reg,
4641 phy_addr, value);
4642 break;
4643 default:
4644 status = -EIO;
4645 break;
4646 }
4647
4648 return status;
4649 }
4650
4651 /**
4652 * i40e_get_phy_address
4653 * @hw: pointer to the HW structure
4654 * @dev_num: PHY port num that address we want
4655 *
4656 * Gets PHY address for current port
4657 **/
i40e_get_phy_address(struct i40e_hw * hw,u8 dev_num)4658 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4659 {
4660 u8 port_num = hw->func_caps.mdio_port_num;
4661 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4662
4663 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4664 }
4665
4666 /**
4667 * i40e_blink_phy_link_led
4668 * @hw: pointer to the HW structure
4669 * @time: time how long led will blinks in secs
4670 * @interval: gap between LED on and off in msecs
4671 *
4672 * Blinks PHY link LED
4673 **/
i40e_blink_phy_link_led(struct i40e_hw * hw,u32 time,u32 interval)4674 int i40e_blink_phy_link_led(struct i40e_hw *hw,
4675 u32 time, u32 interval)
4676 {
4677 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4678 u16 gpio_led_port;
4679 u8 phy_addr = 0;
4680 int status = 0;
4681 u16 led_ctl;
4682 u8 port_num;
4683 u16 led_reg;
4684 u32 i;
4685
4686 i = rd32(hw, I40E_PFGEN_PORTNUM);
4687 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4688 phy_addr = i40e_get_phy_address(hw, port_num);
4689
4690 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4691 led_addr++) {
4692 status = i40e_read_phy_register_clause45(hw,
4693 I40E_PHY_COM_REG_PAGE,
4694 led_addr, phy_addr,
4695 &led_reg);
4696 if (status)
4697 goto phy_blinking_end;
4698 led_ctl = led_reg;
4699 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4700 led_reg = 0;
4701 status = i40e_write_phy_register_clause45(hw,
4702 I40E_PHY_COM_REG_PAGE,
4703 led_addr, phy_addr,
4704 led_reg);
4705 if (status)
4706 goto phy_blinking_end;
4707 break;
4708 }
4709 }
4710
4711 if (time > 0 && interval > 0) {
4712 for (i = 0; i < time * 1000; i += interval) {
4713 status = i40e_read_phy_register_clause45(hw,
4714 I40E_PHY_COM_REG_PAGE,
4715 led_addr, phy_addr, &led_reg);
4716 if (status)
4717 goto restore_config;
4718 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4719 led_reg = 0;
4720 else
4721 led_reg = I40E_PHY_LED_MANUAL_ON;
4722 status = i40e_write_phy_register_clause45(hw,
4723 I40E_PHY_COM_REG_PAGE,
4724 led_addr, phy_addr, led_reg);
4725 if (status)
4726 goto restore_config;
4727 msleep(interval);
4728 }
4729 }
4730
4731 restore_config:
4732 status = i40e_write_phy_register_clause45(hw,
4733 I40E_PHY_COM_REG_PAGE,
4734 led_addr, phy_addr, led_ctl);
4735
4736 phy_blinking_end:
4737 return status;
4738 }
4739
4740 /**
4741 * i40e_led_get_reg - read LED register
4742 * @hw: pointer to the HW structure
4743 * @led_addr: LED register address
4744 * @reg_val: read register value
4745 **/
i40e_led_get_reg(struct i40e_hw * hw,u16 led_addr,u32 * reg_val)4746 static int i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
4747 u32 *reg_val)
4748 {
4749 u8 phy_addr = 0;
4750 u8 port_num;
4751 int status;
4752 u32 i;
4753
4754 *reg_val = 0;
4755 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) {
4756 status =
4757 i40e_aq_get_phy_register(hw,
4758 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
4759 I40E_PHY_COM_REG_PAGE, true,
4760 I40E_PHY_LED_PROV_REG_1,
4761 reg_val, NULL);
4762 } else {
4763 i = rd32(hw, I40E_PFGEN_PORTNUM);
4764 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4765 phy_addr = i40e_get_phy_address(hw, port_num);
4766 status = i40e_read_phy_register_clause45(hw,
4767 I40E_PHY_COM_REG_PAGE,
4768 led_addr, phy_addr,
4769 (u16 *)reg_val);
4770 }
4771 return status;
4772 }
4773
4774 /**
4775 * i40e_led_set_reg - write LED register
4776 * @hw: pointer to the HW structure
4777 * @led_addr: LED register address
4778 * @reg_val: register value to write
4779 **/
i40e_led_set_reg(struct i40e_hw * hw,u16 led_addr,u32 reg_val)4780 static int i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
4781 u32 reg_val)
4782 {
4783 u8 phy_addr = 0;
4784 u8 port_num;
4785 int status;
4786 u32 i;
4787
4788 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) {
4789 status =
4790 i40e_aq_set_phy_register(hw,
4791 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
4792 I40E_PHY_COM_REG_PAGE, true,
4793 I40E_PHY_LED_PROV_REG_1,
4794 reg_val, NULL);
4795 } else {
4796 i = rd32(hw, I40E_PFGEN_PORTNUM);
4797 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4798 phy_addr = i40e_get_phy_address(hw, port_num);
4799 status = i40e_write_phy_register_clause45(hw,
4800 I40E_PHY_COM_REG_PAGE,
4801 led_addr, phy_addr,
4802 (u16)reg_val);
4803 }
4804
4805 return status;
4806 }
4807
4808 /**
4809 * i40e_led_get_phy - return current on/off mode
4810 * @hw: pointer to the hw struct
4811 * @led_addr: address of led register to use
4812 * @val: original value of register to use
4813 *
4814 **/
i40e_led_get_phy(struct i40e_hw * hw,u16 * led_addr,u16 * val)4815 int i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4816 u16 *val)
4817 {
4818 u16 gpio_led_port;
4819 u8 phy_addr = 0;
4820 u32 reg_val_aq;
4821 int status = 0;
4822 u16 temp_addr;
4823 u16 reg_val;
4824 u8 port_num;
4825 u32 i;
4826
4827 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps)) {
4828 status =
4829 i40e_aq_get_phy_register(hw,
4830 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
4831 I40E_PHY_COM_REG_PAGE, true,
4832 I40E_PHY_LED_PROV_REG_1,
4833 ®_val_aq, NULL);
4834 if (status == 0)
4835 *val = (u16)reg_val_aq;
4836 return status;
4837 }
4838 temp_addr = I40E_PHY_LED_PROV_REG_1;
4839 i = rd32(hw, I40E_PFGEN_PORTNUM);
4840 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4841 phy_addr = i40e_get_phy_address(hw, port_num);
4842
4843 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4844 temp_addr++) {
4845 status = i40e_read_phy_register_clause45(hw,
4846 I40E_PHY_COM_REG_PAGE,
4847 temp_addr, phy_addr,
4848 ®_val);
4849 if (status)
4850 return status;
4851 *val = reg_val;
4852 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4853 *led_addr = temp_addr;
4854 break;
4855 }
4856 }
4857 return status;
4858 }
4859
4860 /**
4861 * i40e_led_set_phy
4862 * @hw: pointer to the HW structure
4863 * @on: true or false
4864 * @led_addr: address of led register to use
4865 * @mode: original val plus bit for set or ignore
4866 *
4867 * Set led's on or off when controlled by the PHY
4868 *
4869 **/
i40e_led_set_phy(struct i40e_hw * hw,bool on,u16 led_addr,u32 mode)4870 int i40e_led_set_phy(struct i40e_hw *hw, bool on,
4871 u16 led_addr, u32 mode)
4872 {
4873 u32 led_ctl = 0;
4874 u32 led_reg = 0;
4875 int status = 0;
4876
4877 status = i40e_led_get_reg(hw, led_addr, &led_reg);
4878 if (status)
4879 return status;
4880 led_ctl = led_reg;
4881 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4882 led_reg = 0;
4883 status = i40e_led_set_reg(hw, led_addr, led_reg);
4884 if (status)
4885 return status;
4886 }
4887 status = i40e_led_get_reg(hw, led_addr, &led_reg);
4888 if (status)
4889 goto restore_config;
4890 if (on)
4891 led_reg = I40E_PHY_LED_MANUAL_ON;
4892 else
4893 led_reg = 0;
4894
4895 status = i40e_led_set_reg(hw, led_addr, led_reg);
4896 if (status)
4897 goto restore_config;
4898 if (mode & I40E_PHY_LED_MODE_ORIG) {
4899 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4900 status = i40e_led_set_reg(hw, led_addr, led_ctl);
4901 }
4902 return status;
4903
4904 restore_config:
4905 status = i40e_led_set_reg(hw, led_addr, led_ctl);
4906 return status;
4907 }
4908
4909 /**
4910 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4911 * @hw: pointer to the hw struct
4912 * @reg_addr: register address
4913 * @reg_val: ptr to register value
4914 * @cmd_details: pointer to command details structure or NULL
4915 *
4916 * Use the firmware to read the Rx control register,
4917 * especially useful if the Rx unit is under heavy pressure
4918 **/
i40e_aq_rx_ctl_read_register(struct i40e_hw * hw,u32 reg_addr,u32 * reg_val,struct i40e_asq_cmd_details * cmd_details)4919 int i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4920 u32 reg_addr, u32 *reg_val,
4921 struct i40e_asq_cmd_details *cmd_details)
4922 {
4923 struct i40e_aq_desc desc;
4924 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4925 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4926 int status;
4927
4928 if (!reg_val)
4929 return -EINVAL;
4930
4931 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4932
4933 cmd_resp->address = cpu_to_le32(reg_addr);
4934
4935 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4936
4937 if (status == 0)
4938 *reg_val = le32_to_cpu(cmd_resp->value);
4939
4940 return status;
4941 }
4942
4943 /**
4944 * i40e_read_rx_ctl - read from an Rx control register
4945 * @hw: pointer to the hw struct
4946 * @reg_addr: register address
4947 **/
i40e_read_rx_ctl(struct i40e_hw * hw,u32 reg_addr)4948 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4949 {
4950 bool use_register = false;
4951 int status = 0;
4952 int retry = 5;
4953 u32 val = 0;
4954
4955 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722)
4956 use_register = true;
4957
4958 if (!use_register) {
4959 do_retry:
4960 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4961 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4962 usleep_range(1000, 2000);
4963 retry--;
4964 goto do_retry;
4965 }
4966 }
4967
4968 /* if the AQ access failed, try the old-fashioned way */
4969 if (status || use_register)
4970 val = rd32(hw, reg_addr);
4971
4972 return val;
4973 }
4974
4975 /**
4976 * i40e_aq_rx_ctl_write_register
4977 * @hw: pointer to the hw struct
4978 * @reg_addr: register address
4979 * @reg_val: register value
4980 * @cmd_details: pointer to command details structure or NULL
4981 *
4982 * Use the firmware to write to an Rx control register,
4983 * especially useful if the Rx unit is under heavy pressure
4984 **/
i40e_aq_rx_ctl_write_register(struct i40e_hw * hw,u32 reg_addr,u32 reg_val,struct i40e_asq_cmd_details * cmd_details)4985 int i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4986 u32 reg_addr, u32 reg_val,
4987 struct i40e_asq_cmd_details *cmd_details)
4988 {
4989 struct i40e_aq_desc desc;
4990 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4991 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4992 int status;
4993
4994 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4995
4996 cmd->address = cpu_to_le32(reg_addr);
4997 cmd->value = cpu_to_le32(reg_val);
4998
4999 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5000
5001 return status;
5002 }
5003
5004 /**
5005 * i40e_write_rx_ctl - write to an Rx control register
5006 * @hw: pointer to the hw struct
5007 * @reg_addr: register address
5008 * @reg_val: register value
5009 **/
i40e_write_rx_ctl(struct i40e_hw * hw,u32 reg_addr,u32 reg_val)5010 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5011 {
5012 bool use_register = false;
5013 int status = 0;
5014 int retry = 5;
5015
5016 if (i40e_is_aq_api_ver_lt(hw, 1, 5) || hw->mac.type == I40E_MAC_X722)
5017 use_register = true;
5018
5019 if (!use_register) {
5020 do_retry:
5021 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5022 reg_val, NULL);
5023 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5024 usleep_range(1000, 2000);
5025 retry--;
5026 goto do_retry;
5027 }
5028 }
5029
5030 /* if the AQ access failed, try the old-fashioned way */
5031 if (status || use_register)
5032 wr32(hw, reg_addr, reg_val);
5033 }
5034
5035 /**
5036 * i40e_mdio_if_number_selection - MDIO I/F number selection
5037 * @hw: pointer to the hw struct
5038 * @set_mdio: use MDIO I/F number specified by mdio_num
5039 * @mdio_num: MDIO I/F number
5040 * @cmd: pointer to PHY Register command structure
5041 **/
i40e_mdio_if_number_selection(struct i40e_hw * hw,bool set_mdio,u8 mdio_num,struct i40e_aqc_phy_register_access * cmd)5042 static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio,
5043 u8 mdio_num,
5044 struct i40e_aqc_phy_register_access *cmd)
5045 {
5046 if (!set_mdio ||
5047 cmd->phy_interface != I40E_AQ_PHY_REG_ACCESS_EXTERNAL)
5048 return;
5049
5050 if (test_bit(I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED, hw->caps)) {
5051 cmd->cmd_flags |=
5052 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
5053 FIELD_PREP(I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK,
5054 mdio_num);
5055 } else {
5056 i40e_debug(hw, I40E_DEBUG_PHY, "MDIO I/F number selection not supported by current FW version.\n");
5057 }
5058 }
5059
5060 /**
5061 * i40e_aq_set_phy_register_ext
5062 * @hw: pointer to the hw struct
5063 * @phy_select: select which phy should be accessed
5064 * @dev_addr: PHY device address
5065 * @page_change: flag to indicate if phy page should be updated
5066 * @set_mdio: use MDIO I/F number specified by mdio_num
5067 * @mdio_num: MDIO I/F number
5068 * @reg_addr: PHY register address
5069 * @reg_val: new register value
5070 * @cmd_details: pointer to command details structure or NULL
5071 *
5072 * Write the external PHY register.
5073 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5074 * may use simple wrapper i40e_aq_set_phy_register.
5075 **/
i40e_aq_set_phy_register_ext(struct i40e_hw * hw,u8 phy_select,u8 dev_addr,bool page_change,bool set_mdio,u8 mdio_num,u32 reg_addr,u32 reg_val,struct i40e_asq_cmd_details * cmd_details)5076 int i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
5077 u8 phy_select, u8 dev_addr, bool page_change,
5078 bool set_mdio, u8 mdio_num,
5079 u32 reg_addr, u32 reg_val,
5080 struct i40e_asq_cmd_details *cmd_details)
5081 {
5082 struct i40e_aq_desc desc;
5083 struct i40e_aqc_phy_register_access *cmd =
5084 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5085 int status;
5086
5087 i40e_fill_default_direct_cmd_desc(&desc,
5088 i40e_aqc_opc_set_phy_register);
5089
5090 cmd->phy_interface = phy_select;
5091 cmd->dev_address = dev_addr;
5092 cmd->reg_address = cpu_to_le32(reg_addr);
5093 cmd->reg_value = cpu_to_le32(reg_val);
5094
5095 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5096
5097 if (!page_change)
5098 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5099
5100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5101
5102 return status;
5103 }
5104
5105 /**
5106 * i40e_aq_get_phy_register_ext
5107 * @hw: pointer to the hw struct
5108 * @phy_select: select which phy should be accessed
5109 * @dev_addr: PHY device address
5110 * @page_change: flag to indicate if phy page should be updated
5111 * @set_mdio: use MDIO I/F number specified by mdio_num
5112 * @mdio_num: MDIO I/F number
5113 * @reg_addr: PHY register address
5114 * @reg_val: read register value
5115 * @cmd_details: pointer to command details structure or NULL
5116 *
5117 * Read the external PHY register.
5118 * NOTE: In common cases MDIO I/F number should not be changed, thats why you
5119 * may use simple wrapper i40e_aq_get_phy_register.
5120 **/
i40e_aq_get_phy_register_ext(struct i40e_hw * hw,u8 phy_select,u8 dev_addr,bool page_change,bool set_mdio,u8 mdio_num,u32 reg_addr,u32 * reg_val,struct i40e_asq_cmd_details * cmd_details)5121 int i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
5122 u8 phy_select, u8 dev_addr, bool page_change,
5123 bool set_mdio, u8 mdio_num,
5124 u32 reg_addr, u32 *reg_val,
5125 struct i40e_asq_cmd_details *cmd_details)
5126 {
5127 struct i40e_aq_desc desc;
5128 struct i40e_aqc_phy_register_access *cmd =
5129 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5130 int status;
5131
5132 i40e_fill_default_direct_cmd_desc(&desc,
5133 i40e_aqc_opc_get_phy_register);
5134
5135 cmd->phy_interface = phy_select;
5136 cmd->dev_address = dev_addr;
5137 cmd->reg_address = cpu_to_le32(reg_addr);
5138
5139 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5140
5141 if (!page_change)
5142 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5143
5144 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5145 if (!status)
5146 *reg_val = le32_to_cpu(cmd->reg_value);
5147
5148 return status;
5149 }
5150
5151 /**
5152 * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
5153 * @hw: pointer to the hw struct
5154 * @buff: command buffer (size in bytes = buff_size)
5155 * @buff_size: buffer size in bytes
5156 * @track_id: package tracking id
5157 * @error_offset: returns error offset
5158 * @error_info: returns error information
5159 * @cmd_details: pointer to command details structure or NULL
5160 **/
i40e_aq_write_ddp(struct i40e_hw * hw,void * buff,u16 buff_size,u32 track_id,u32 * error_offset,u32 * error_info,struct i40e_asq_cmd_details * cmd_details)5161 int i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5162 u16 buff_size, u32 track_id,
5163 u32 *error_offset, u32 *error_info,
5164 struct i40e_asq_cmd_details *cmd_details)
5165 {
5166 struct i40e_aq_desc desc;
5167 struct i40e_aqc_write_personalization_profile *cmd =
5168 (struct i40e_aqc_write_personalization_profile *)
5169 &desc.params.raw;
5170 struct i40e_aqc_write_ddp_resp *resp;
5171 int status;
5172
5173 i40e_fill_default_direct_cmd_desc(&desc,
5174 i40e_aqc_opc_write_personalization_profile);
5175
5176 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5177 if (buff_size > I40E_AQ_LARGE_BUF)
5178 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5179
5180 desc.datalen = cpu_to_le16(buff_size);
5181
5182 cmd->profile_track_id = cpu_to_le32(track_id);
5183
5184 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5185 if (!status) {
5186 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5187 if (error_offset)
5188 *error_offset = le32_to_cpu(resp->error_offset);
5189 if (error_info)
5190 *error_info = le32_to_cpu(resp->error_info);
5191 }
5192
5193 return status;
5194 }
5195
5196 /**
5197 * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
5198 * @hw: pointer to the hw struct
5199 * @buff: command buffer (size in bytes = buff_size)
5200 * @buff_size: buffer size in bytes
5201 * @flags: AdminQ command flags
5202 * @cmd_details: pointer to command details structure or NULL
5203 **/
i40e_aq_get_ddp_list(struct i40e_hw * hw,void * buff,u16 buff_size,u8 flags,struct i40e_asq_cmd_details * cmd_details)5204 int i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5205 u16 buff_size, u8 flags,
5206 struct i40e_asq_cmd_details *cmd_details)
5207 {
5208 struct i40e_aq_desc desc;
5209 struct i40e_aqc_get_applied_profiles *cmd =
5210 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5211 int status;
5212
5213 i40e_fill_default_direct_cmd_desc(&desc,
5214 i40e_aqc_opc_get_personalization_profile_list);
5215
5216 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5217 if (buff_size > I40E_AQ_LARGE_BUF)
5218 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5219 desc.datalen = cpu_to_le16(buff_size);
5220
5221 cmd->flags = flags;
5222
5223 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5224
5225 return status;
5226 }
5227
5228 /**
5229 * i40e_find_segment_in_package
5230 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5231 * @pkg_hdr: pointer to the package header to be searched
5232 *
5233 * This function searches a package file for a particular segment type. On
5234 * success it returns a pointer to the segment header, otherwise it will
5235 * return NULL.
5236 **/
5237 struct i40e_generic_seg_header *
i40e_find_segment_in_package(u32 segment_type,struct i40e_package_header * pkg_hdr)5238 i40e_find_segment_in_package(u32 segment_type,
5239 struct i40e_package_header *pkg_hdr)
5240 {
5241 struct i40e_generic_seg_header *segment;
5242 u32 i;
5243
5244 /* Search all package segments for the requested segment type */
5245 for (i = 0; i < pkg_hdr->segment_count; i++) {
5246 segment =
5247 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5248 pkg_hdr->segment_offset[i]);
5249
5250 if (segment->type == segment_type)
5251 return segment;
5252 }
5253
5254 return NULL;
5255 }
5256
5257 /* Get section table in profile */
5258 #define I40E_SECTION_TABLE(profile, sec_tbl) \
5259 do { \
5260 struct i40e_profile_segment *p = (profile); \
5261 u32 count; \
5262 u32 *nvm; \
5263 count = p->device_table_count; \
5264 nvm = (u32 *)&p->device_table[count]; \
5265 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
5266 } while (0)
5267
5268 /* Get section header in profile */
5269 #define I40E_SECTION_HEADER(profile, offset) \
5270 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
5271
5272 /**
5273 * i40e_find_section_in_profile
5274 * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
5275 * @profile: pointer to the i40e segment header to be searched
5276 *
5277 * This function searches i40e segment for a particular section type. On
5278 * success it returns a pointer to the section header, otherwise it will
5279 * return NULL.
5280 **/
5281 struct i40e_profile_section_header *
i40e_find_section_in_profile(u32 section_type,struct i40e_profile_segment * profile)5282 i40e_find_section_in_profile(u32 section_type,
5283 struct i40e_profile_segment *profile)
5284 {
5285 struct i40e_profile_section_header *sec;
5286 struct i40e_section_table *sec_tbl;
5287 u32 sec_off;
5288 u32 i;
5289
5290 if (profile->header.type != SEGMENT_TYPE_I40E)
5291 return NULL;
5292
5293 I40E_SECTION_TABLE(profile, sec_tbl);
5294
5295 for (i = 0; i < sec_tbl->section_count; i++) {
5296 sec_off = sec_tbl->section_offset[i];
5297 sec = I40E_SECTION_HEADER(profile, sec_off);
5298 if (sec->section.type == section_type)
5299 return sec;
5300 }
5301
5302 return NULL;
5303 }
5304
5305 /**
5306 * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
5307 * @hw: pointer to the hw struct
5308 * @aq: command buffer containing all data to execute AQ
5309 **/
i40e_ddp_exec_aq_section(struct i40e_hw * hw,struct i40e_profile_aq_section * aq)5310 static int i40e_ddp_exec_aq_section(struct i40e_hw *hw,
5311 struct i40e_profile_aq_section *aq)
5312 {
5313 struct i40e_aq_desc desc;
5314 u8 *msg = NULL;
5315 u16 msglen;
5316 int status;
5317
5318 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
5319 desc.flags |= cpu_to_le16(aq->flags);
5320 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw));
5321
5322 msglen = aq->datalen;
5323 if (msglen) {
5324 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
5325 I40E_AQ_FLAG_RD));
5326 if (msglen > I40E_AQ_LARGE_BUF)
5327 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5328 desc.datalen = cpu_to_le16(msglen);
5329 msg = &aq->data[0];
5330 }
5331
5332 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
5333
5334 if (status) {
5335 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5336 "unable to exec DDP AQ opcode %u, error %d\n",
5337 aq->opcode, status);
5338 return status;
5339 }
5340
5341 /* copy returned desc to aq_buf */
5342 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw));
5343
5344 return 0;
5345 }
5346
5347 /**
5348 * i40e_validate_profile
5349 * @hw: pointer to the hardware structure
5350 * @profile: pointer to the profile segment of the package to be validated
5351 * @track_id: package tracking id
5352 * @rollback: flag if the profile is for rollback.
5353 *
5354 * Validates supported devices and profile's sections.
5355 */
5356 static int
i40e_validate_profile(struct i40e_hw * hw,struct i40e_profile_segment * profile,u32 track_id,bool rollback)5357 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5358 u32 track_id, bool rollback)
5359 {
5360 struct i40e_profile_section_header *sec = NULL;
5361 struct i40e_section_table *sec_tbl;
5362 u32 vendor_dev_id;
5363 int status = 0;
5364 u32 dev_cnt;
5365 u32 sec_off;
5366 u32 i;
5367
5368 if (track_id == I40E_DDP_TRACKID_INVALID) {
5369 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
5370 return -EOPNOTSUPP;
5371 }
5372
5373 dev_cnt = profile->device_table_count;
5374 for (i = 0; i < dev_cnt; i++) {
5375 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5376 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL &&
5377 hw->device_id == (vendor_dev_id & 0xFFFF))
5378 break;
5379 }
5380 if (dev_cnt && i == dev_cnt) {
5381 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5382 "Device doesn't support DDP\n");
5383 return -ENODEV;
5384 }
5385
5386 I40E_SECTION_TABLE(profile, sec_tbl);
5387
5388 /* Validate sections types */
5389 for (i = 0; i < sec_tbl->section_count; i++) {
5390 sec_off = sec_tbl->section_offset[i];
5391 sec = I40E_SECTION_HEADER(profile, sec_off);
5392 if (rollback) {
5393 if (sec->section.type == SECTION_TYPE_MMIO ||
5394 sec->section.type == SECTION_TYPE_AQ ||
5395 sec->section.type == SECTION_TYPE_RB_AQ) {
5396 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5397 "Not a roll-back package\n");
5398 return -EOPNOTSUPP;
5399 }
5400 } else {
5401 if (sec->section.type == SECTION_TYPE_RB_AQ ||
5402 sec->section.type == SECTION_TYPE_RB_MMIO) {
5403 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5404 "Not an original package\n");
5405 return -EOPNOTSUPP;
5406 }
5407 }
5408 }
5409
5410 return status;
5411 }
5412
5413 /**
5414 * i40e_write_profile
5415 * @hw: pointer to the hardware structure
5416 * @profile: pointer to the profile segment of the package to be downloaded
5417 * @track_id: package tracking id
5418 *
5419 * Handles the download of a complete package.
5420 */
5421 int
i40e_write_profile(struct i40e_hw * hw,struct i40e_profile_segment * profile,u32 track_id)5422 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5423 u32 track_id)
5424 {
5425 struct i40e_profile_section_header *sec = NULL;
5426 struct i40e_profile_aq_section *ddp_aq;
5427 struct i40e_section_table *sec_tbl;
5428 u32 offset = 0, info = 0;
5429 u32 section_size = 0;
5430 int status = 0;
5431 u32 sec_off;
5432 u32 i;
5433
5434 status = i40e_validate_profile(hw, profile, track_id, false);
5435 if (status)
5436 return status;
5437
5438 I40E_SECTION_TABLE(profile, sec_tbl);
5439
5440 for (i = 0; i < sec_tbl->section_count; i++) {
5441 sec_off = sec_tbl->section_offset[i];
5442 sec = I40E_SECTION_HEADER(profile, sec_off);
5443 /* Process generic admin command */
5444 if (sec->section.type == SECTION_TYPE_AQ) {
5445 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
5446 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
5447 if (status) {
5448 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5449 "Failed to execute aq: section %d, opcode %u\n",
5450 i, ddp_aq->opcode);
5451 break;
5452 }
5453 sec->section.type = SECTION_TYPE_RB_AQ;
5454 }
5455
5456 /* Skip any non-mmio sections */
5457 if (sec->section.type != SECTION_TYPE_MMIO)
5458 continue;
5459
5460 section_size = sec->section.size +
5461 sizeof(struct i40e_profile_section_header);
5462
5463 /* Write MMIO section */
5464 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5465 track_id, &offset, &info, NULL);
5466 if (status) {
5467 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5468 "Failed to write profile: section %d, offset %d, info %d\n",
5469 i, offset, info);
5470 break;
5471 }
5472 }
5473 return status;
5474 }
5475
5476 /**
5477 * i40e_rollback_profile
5478 * @hw: pointer to the hardware structure
5479 * @profile: pointer to the profile segment of the package to be removed
5480 * @track_id: package tracking id
5481 *
5482 * Rolls back previously loaded package.
5483 */
5484 int
i40e_rollback_profile(struct i40e_hw * hw,struct i40e_profile_segment * profile,u32 track_id)5485 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5486 u32 track_id)
5487 {
5488 struct i40e_profile_section_header *sec = NULL;
5489 struct i40e_section_table *sec_tbl;
5490 u32 offset = 0, info = 0;
5491 u32 section_size = 0;
5492 int status = 0;
5493 u32 sec_off;
5494 int i;
5495
5496 status = i40e_validate_profile(hw, profile, track_id, true);
5497 if (status)
5498 return status;
5499
5500 I40E_SECTION_TABLE(profile, sec_tbl);
5501
5502 /* For rollback write sections in reverse */
5503 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
5504 sec_off = sec_tbl->section_offset[i];
5505 sec = I40E_SECTION_HEADER(profile, sec_off);
5506
5507 /* Skip any non-rollback sections */
5508 if (sec->section.type != SECTION_TYPE_RB_MMIO)
5509 continue;
5510
5511 section_size = sec->section.size +
5512 sizeof(struct i40e_profile_section_header);
5513
5514 /* Write roll-back MMIO section */
5515 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5516 track_id, &offset, &info, NULL);
5517 if (status) {
5518 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5519 "Failed to write profile: section %d, offset %d, info %d\n",
5520 i, offset, info);
5521 break;
5522 }
5523 }
5524 return status;
5525 }
5526
5527 /**
5528 * i40e_add_pinfo_to_list
5529 * @hw: pointer to the hardware structure
5530 * @profile: pointer to the profile segment of the package
5531 * @profile_info_sec: buffer for information section
5532 * @track_id: package tracking id
5533 *
5534 * Register a profile to the list of loaded profiles.
5535 */
5536 int
i40e_add_pinfo_to_list(struct i40e_hw * hw,struct i40e_profile_segment * profile,u8 * profile_info_sec,u32 track_id)5537 i40e_add_pinfo_to_list(struct i40e_hw *hw,
5538 struct i40e_profile_segment *profile,
5539 u8 *profile_info_sec, u32 track_id)
5540 {
5541 struct i40e_profile_section_header *sec = NULL;
5542 struct i40e_profile_info *pinfo;
5543 u32 offset = 0, info = 0;
5544 int status = 0;
5545
5546 sec = (struct i40e_profile_section_header *)profile_info_sec;
5547 sec->tbl_size = 1;
5548 sec->data_end = sizeof(struct i40e_profile_section_header) +
5549 sizeof(struct i40e_profile_info);
5550 sec->section.type = SECTION_TYPE_INFO;
5551 sec->section.offset = sizeof(struct i40e_profile_section_header);
5552 sec->section.size = sizeof(struct i40e_profile_info);
5553 pinfo = (struct i40e_profile_info *)(profile_info_sec +
5554 sec->section.offset);
5555 pinfo->track_id = track_id;
5556 pinfo->version = profile->version;
5557 pinfo->op = I40E_DDP_ADD_TRACKID;
5558 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5559
5560 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5561 track_id, &offset, &info, NULL);
5562
5563 return status;
5564 }
5565
5566 /**
5567 * i40e_aq_add_cloud_filters
5568 * @hw: pointer to the hardware structure
5569 * @seid: VSI seid to add cloud filters from
5570 * @filters: Buffer which contains the filters to be added
5571 * @filter_count: number of filters contained in the buffer
5572 *
5573 * Set the cloud filters for a given VSI. The contents of the
5574 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5575 * of the function.
5576 *
5577 **/
5578 int
i40e_aq_add_cloud_filters(struct i40e_hw * hw,u16 seid,struct i40e_aqc_cloud_filters_element_data * filters,u8 filter_count)5579 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5580 struct i40e_aqc_cloud_filters_element_data *filters,
5581 u8 filter_count)
5582 {
5583 struct i40e_aq_desc desc;
5584 struct i40e_aqc_add_remove_cloud_filters *cmd =
5585 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5586 u16 buff_len;
5587 int status;
5588
5589 i40e_fill_default_direct_cmd_desc(&desc,
5590 i40e_aqc_opc_add_cloud_filters);
5591
5592 buff_len = filter_count * sizeof(*filters);
5593 desc.datalen = cpu_to_le16(buff_len);
5594 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5595 cmd->num_filters = filter_count;
5596 cmd->seid = cpu_to_le16(seid);
5597
5598 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5599
5600 return status;
5601 }
5602
5603 /**
5604 * i40e_aq_add_cloud_filters_bb
5605 * @hw: pointer to the hardware structure
5606 * @seid: VSI seid to add cloud filters from
5607 * @filters: Buffer which contains the filters in big buffer to be added
5608 * @filter_count: number of filters contained in the buffer
5609 *
5610 * Set the big buffer cloud filters for a given VSI. The contents of the
5611 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5612 * function.
5613 *
5614 **/
5615 int
i40e_aq_add_cloud_filters_bb(struct i40e_hw * hw,u16 seid,struct i40e_aqc_cloud_filters_element_bb * filters,u8 filter_count)5616 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5617 struct i40e_aqc_cloud_filters_element_bb *filters,
5618 u8 filter_count)
5619 {
5620 struct i40e_aq_desc desc;
5621 struct i40e_aqc_add_remove_cloud_filters *cmd =
5622 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5623 u16 buff_len;
5624 int status;
5625 int i;
5626
5627 i40e_fill_default_direct_cmd_desc(&desc,
5628 i40e_aqc_opc_add_cloud_filters);
5629
5630 buff_len = filter_count * sizeof(*filters);
5631 desc.datalen = cpu_to_le16(buff_len);
5632 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5633 cmd->num_filters = filter_count;
5634 cmd->seid = cpu_to_le16(seid);
5635 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5636
5637 for (i = 0; i < filter_count; i++) {
5638 u16 tnl_type;
5639 u32 ti;
5640
5641 tnl_type = le16_get_bits(filters[i].element.flags,
5642 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);
5643
5644 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5645 * one more byte further than normally used for Tenant ID in
5646 * other tunnel types.
5647 */
5648 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5649 ti = le32_to_cpu(filters[i].element.tenant_id);
5650 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5651 }
5652 }
5653
5654 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5655
5656 return status;
5657 }
5658
5659 /**
5660 * i40e_aq_rem_cloud_filters
5661 * @hw: pointer to the hardware structure
5662 * @seid: VSI seid to remove cloud filters from
5663 * @filters: Buffer which contains the filters to be removed
5664 * @filter_count: number of filters contained in the buffer
5665 *
5666 * Remove the cloud filters for a given VSI. The contents of the
5667 * i40e_aqc_cloud_filters_element_data are filled in by the caller
5668 * of the function.
5669 *
5670 **/
5671 int
i40e_aq_rem_cloud_filters(struct i40e_hw * hw,u16 seid,struct i40e_aqc_cloud_filters_element_data * filters,u8 filter_count)5672 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5673 struct i40e_aqc_cloud_filters_element_data *filters,
5674 u8 filter_count)
5675 {
5676 struct i40e_aq_desc desc;
5677 struct i40e_aqc_add_remove_cloud_filters *cmd =
5678 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5679 u16 buff_len;
5680 int status;
5681
5682 i40e_fill_default_direct_cmd_desc(&desc,
5683 i40e_aqc_opc_remove_cloud_filters);
5684
5685 buff_len = filter_count * sizeof(*filters);
5686 desc.datalen = cpu_to_le16(buff_len);
5687 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5688 cmd->num_filters = filter_count;
5689 cmd->seid = cpu_to_le16(seid);
5690
5691 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5692
5693 return status;
5694 }
5695
5696 /**
5697 * i40e_aq_rem_cloud_filters_bb
5698 * @hw: pointer to the hardware structure
5699 * @seid: VSI seid to remove cloud filters from
5700 * @filters: Buffer which contains the filters in big buffer to be removed
5701 * @filter_count: number of filters contained in the buffer
5702 *
5703 * Remove the big buffer cloud filters for a given VSI. The contents of the
5704 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5705 * function.
5706 *
5707 **/
5708 int
i40e_aq_rem_cloud_filters_bb(struct i40e_hw * hw,u16 seid,struct i40e_aqc_cloud_filters_element_bb * filters,u8 filter_count)5709 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5710 struct i40e_aqc_cloud_filters_element_bb *filters,
5711 u8 filter_count)
5712 {
5713 struct i40e_aq_desc desc;
5714 struct i40e_aqc_add_remove_cloud_filters *cmd =
5715 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5716 u16 buff_len;
5717 int status;
5718 int i;
5719
5720 i40e_fill_default_direct_cmd_desc(&desc,
5721 i40e_aqc_opc_remove_cloud_filters);
5722
5723 buff_len = filter_count * sizeof(*filters);
5724 desc.datalen = cpu_to_le16(buff_len);
5725 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5726 cmd->num_filters = filter_count;
5727 cmd->seid = cpu_to_le16(seid);
5728 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5729
5730 for (i = 0; i < filter_count; i++) {
5731 u16 tnl_type;
5732 u32 ti;
5733
5734 tnl_type = le16_get_bits(filters[i].element.flags,
5735 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK);
5736
5737 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5738 * one more byte further than normally used for Tenant ID in
5739 * other tunnel types.
5740 */
5741 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5742 ti = le32_to_cpu(filters[i].element.tenant_id);
5743 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5744 }
5745 }
5746
5747 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5748
5749 return status;
5750 }
5751