1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9 #include <linux/of.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/of_address.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/if_vlan.h>
19 #include <linux/reset.h>
20 #include <linux/tcp.h>
21 #include <linux/interrupt.h>
22 #include <linux/pinctrl/devinfo.h>
23 #include <linux/phylink.h>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
25 #include <linux/jhash.h>
26 #include <linux/bitfield.h>
27 #include <net/dsa.h>
28 #include <net/dst_metadata.h>
29 #include <net/page_pool/helpers.h>
30
31 #include "mtk_eth_soc.h"
32 #include "mtk_wed.h"
33
34 static int mtk_msg_level = -1;
35 module_param_named(msg_level, mtk_msg_level, int, 0);
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
37
38 #define MTK_ETHTOOL_STAT(x) { #x, \
39 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
40
41 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \
42 offsetof(struct mtk_hw_stats, xdp_stats.x) / \
43 sizeof(u64) }
44
45 static const struct mtk_reg_map mtk_reg_map = {
46 .tx_irq_mask = 0x1a1c,
47 .tx_irq_status = 0x1a18,
48 .pdma = {
49 .rx_ptr = 0x0900,
50 .rx_cnt_cfg = 0x0904,
51 .pcrx_ptr = 0x0908,
52 .glo_cfg = 0x0a04,
53 .rst_idx = 0x0a08,
54 .delay_irq = 0x0a0c,
55 .irq_status = 0x0a20,
56 .irq_mask = 0x0a28,
57 .adma_rx_dbg0 = 0x0a38,
58 .int_grp = 0x0a50,
59 },
60 .qdma = {
61 .qtx_cfg = 0x1800,
62 .qtx_sch = 0x1804,
63 .rx_ptr = 0x1900,
64 .rx_cnt_cfg = 0x1904,
65 .qcrx_ptr = 0x1908,
66 .glo_cfg = 0x1a04,
67 .rst_idx = 0x1a08,
68 .delay_irq = 0x1a0c,
69 .fc_th = 0x1a10,
70 .tx_sch_rate = 0x1a14,
71 .int_grp = 0x1a20,
72 .hred = 0x1a44,
73 .ctx_ptr = 0x1b00,
74 .dtx_ptr = 0x1b04,
75 .crx_ptr = 0x1b10,
76 .drx_ptr = 0x1b14,
77 .fq_head = 0x1b20,
78 .fq_tail = 0x1b24,
79 .fq_count = 0x1b28,
80 .fq_blen = 0x1b2c,
81 },
82 .gdm1_cnt = 0x2400,
83 .gdma_to_ppe = {
84 [0] = 0x4444,
85 },
86 .ppe_base = 0x0c00,
87 .wdma_base = {
88 [0] = 0x2800,
89 [1] = 0x2c00,
90 },
91 .pse_iq_sta = 0x0110,
92 .pse_oq_sta = 0x0118,
93 };
94
95 static const struct mtk_reg_map mt7628_reg_map = {
96 .tx_irq_mask = 0x0a28,
97 .tx_irq_status = 0x0a20,
98 .pdma = {
99 .rx_ptr = 0x0900,
100 .rx_cnt_cfg = 0x0904,
101 .pcrx_ptr = 0x0908,
102 .glo_cfg = 0x0a04,
103 .rst_idx = 0x0a08,
104 .delay_irq = 0x0a0c,
105 .irq_status = 0x0a20,
106 .irq_mask = 0x0a28,
107 .int_grp = 0x0a50,
108 },
109 };
110
111 static const struct mtk_reg_map mt7986_reg_map = {
112 .tx_irq_mask = 0x461c,
113 .tx_irq_status = 0x4618,
114 .pdma = {
115 .rx_ptr = 0x4100,
116 .rx_cnt_cfg = 0x4104,
117 .pcrx_ptr = 0x4108,
118 .glo_cfg = 0x4204,
119 .rst_idx = 0x4208,
120 .delay_irq = 0x420c,
121 .irq_status = 0x4220,
122 .irq_mask = 0x4228,
123 .adma_rx_dbg0 = 0x4238,
124 .int_grp = 0x4250,
125 },
126 .qdma = {
127 .qtx_cfg = 0x4400,
128 .qtx_sch = 0x4404,
129 .rx_ptr = 0x4500,
130 .rx_cnt_cfg = 0x4504,
131 .qcrx_ptr = 0x4508,
132 .glo_cfg = 0x4604,
133 .rst_idx = 0x4608,
134 .delay_irq = 0x460c,
135 .fc_th = 0x4610,
136 .int_grp = 0x4620,
137 .hred = 0x4644,
138 .ctx_ptr = 0x4700,
139 .dtx_ptr = 0x4704,
140 .crx_ptr = 0x4710,
141 .drx_ptr = 0x4714,
142 .fq_head = 0x4720,
143 .fq_tail = 0x4724,
144 .fq_count = 0x4728,
145 .fq_blen = 0x472c,
146 .tx_sch_rate = 0x4798,
147 },
148 .gdm1_cnt = 0x1c00,
149 .gdma_to_ppe = {
150 [0] = 0x3333,
151 [1] = 0x4444,
152 },
153 .ppe_base = 0x2000,
154 .wdma_base = {
155 [0] = 0x4800,
156 [1] = 0x4c00,
157 },
158 .pse_iq_sta = 0x0180,
159 .pse_oq_sta = 0x01a0,
160 };
161
162 static const struct mtk_reg_map mt7988_reg_map = {
163 .tx_irq_mask = 0x461c,
164 .tx_irq_status = 0x4618,
165 .pdma = {
166 .rx_ptr = 0x6900,
167 .rx_cnt_cfg = 0x6904,
168 .pcrx_ptr = 0x6908,
169 .glo_cfg = 0x6a04,
170 .rst_idx = 0x6a08,
171 .delay_irq = 0x6a0c,
172 .irq_status = 0x6a20,
173 .irq_mask = 0x6a28,
174 .adma_rx_dbg0 = 0x6a38,
175 .int_grp = 0x6a50,
176 },
177 .qdma = {
178 .qtx_cfg = 0x4400,
179 .qtx_sch = 0x4404,
180 .rx_ptr = 0x4500,
181 .rx_cnt_cfg = 0x4504,
182 .qcrx_ptr = 0x4508,
183 .glo_cfg = 0x4604,
184 .rst_idx = 0x4608,
185 .delay_irq = 0x460c,
186 .fc_th = 0x4610,
187 .int_grp = 0x4620,
188 .hred = 0x4644,
189 .ctx_ptr = 0x4700,
190 .dtx_ptr = 0x4704,
191 .crx_ptr = 0x4710,
192 .drx_ptr = 0x4714,
193 .fq_head = 0x4720,
194 .fq_tail = 0x4724,
195 .fq_count = 0x4728,
196 .fq_blen = 0x472c,
197 .tx_sch_rate = 0x4798,
198 },
199 .gdm1_cnt = 0x1c00,
200 .gdma_to_ppe = {
201 [0] = 0x3333,
202 [1] = 0x4444,
203 [2] = 0xcccc,
204 },
205 .ppe_base = 0x2000,
206 .wdma_base = {
207 [0] = 0x4800,
208 [1] = 0x4c00,
209 [2] = 0x5000,
210 },
211 .pse_iq_sta = 0x0180,
212 .pse_oq_sta = 0x01a0,
213 };
214
215 /* strings used by ethtool */
216 static const struct mtk_ethtool_stats {
217 char str[ETH_GSTRING_LEN];
218 u32 offset;
219 } mtk_ethtool_stats[] = {
220 MTK_ETHTOOL_STAT(tx_bytes),
221 MTK_ETHTOOL_STAT(tx_packets),
222 MTK_ETHTOOL_STAT(tx_skip),
223 MTK_ETHTOOL_STAT(tx_collisions),
224 MTK_ETHTOOL_STAT(rx_bytes),
225 MTK_ETHTOOL_STAT(rx_packets),
226 MTK_ETHTOOL_STAT(rx_overflow),
227 MTK_ETHTOOL_STAT(rx_fcs_errors),
228 MTK_ETHTOOL_STAT(rx_short_errors),
229 MTK_ETHTOOL_STAT(rx_long_errors),
230 MTK_ETHTOOL_STAT(rx_checksum_errors),
231 MTK_ETHTOOL_STAT(rx_flow_control_packets),
232 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect),
233 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass),
234 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop),
235 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx),
236 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors),
237 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit),
238 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors),
239 };
240
241 static const char * const mtk_clks_source_name[] = {
242 "ethif",
243 "sgmiitop",
244 "esw",
245 "gp0",
246 "gp1",
247 "gp2",
248 "gp3",
249 "xgp1",
250 "xgp2",
251 "xgp3",
252 "crypto",
253 "fe",
254 "trgpll",
255 "sgmii_tx250m",
256 "sgmii_rx250m",
257 "sgmii_cdr_ref",
258 "sgmii_cdr_fb",
259 "sgmii2_tx250m",
260 "sgmii2_rx250m",
261 "sgmii2_cdr_ref",
262 "sgmii2_cdr_fb",
263 "sgmii_ck",
264 "eth2pll",
265 "wocpu0",
266 "wocpu1",
267 "netsys0",
268 "netsys1",
269 "ethwarp_wocpu2",
270 "ethwarp_wocpu1",
271 "ethwarp_wocpu0",
272 "top_sgm0_sel",
273 "top_sgm1_sel",
274 "top_eth_gmii_sel",
275 "top_eth_refck_50m_sel",
276 "top_eth_sys_200m_sel",
277 "top_eth_sys_sel",
278 "top_eth_xgmii_sel",
279 "top_eth_mii_sel",
280 "top_netsys_sel",
281 "top_netsys_500m_sel",
282 "top_netsys_pao_2x_sel",
283 "top_netsys_sync_250m_sel",
284 "top_netsys_ppefb_250m_sel",
285 "top_netsys_warp_sel",
286 };
287
mtk_w32(struct mtk_eth * eth,u32 val,unsigned reg)288 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
289 {
290 __raw_writel(val, eth->base + reg);
291 }
292
mtk_r32(struct mtk_eth * eth,unsigned reg)293 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
294 {
295 return __raw_readl(eth->base + reg);
296 }
297
mtk_m32(struct mtk_eth * eth,u32 mask,u32 set,unsigned int reg)298 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg)
299 {
300 u32 val;
301
302 val = mtk_r32(eth, reg);
303 val &= ~mask;
304 val |= set;
305 mtk_w32(eth, val, reg);
306 return reg;
307 }
308
mtk_mdio_busy_wait(struct mtk_eth * eth)309 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
310 {
311 unsigned long t_start = jiffies;
312
313 while (1) {
314 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
315 return 0;
316 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
317 break;
318 cond_resched();
319 }
320
321 dev_err(eth->dev, "mdio: MDIO timeout\n");
322 return -ETIMEDOUT;
323 }
324
_mtk_mdio_write_c22(struct mtk_eth * eth,u32 phy_addr,u32 phy_reg,u32 write_data)325 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
326 u32 write_data)
327 {
328 int ret;
329
330 ret = mtk_mdio_busy_wait(eth);
331 if (ret < 0)
332 return ret;
333
334 mtk_w32(eth, PHY_IAC_ACCESS |
335 PHY_IAC_START_C22 |
336 PHY_IAC_CMD_WRITE |
337 PHY_IAC_REG(phy_reg) |
338 PHY_IAC_ADDR(phy_addr) |
339 PHY_IAC_DATA(write_data),
340 MTK_PHY_IAC);
341
342 ret = mtk_mdio_busy_wait(eth);
343 if (ret < 0)
344 return ret;
345
346 return 0;
347 }
348
_mtk_mdio_write_c45(struct mtk_eth * eth,u32 phy_addr,u32 devad,u32 phy_reg,u32 write_data)349 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr,
350 u32 devad, u32 phy_reg, u32 write_data)
351 {
352 int ret;
353
354 ret = mtk_mdio_busy_wait(eth);
355 if (ret < 0)
356 return ret;
357
358 mtk_w32(eth, PHY_IAC_ACCESS |
359 PHY_IAC_START_C45 |
360 PHY_IAC_CMD_C45_ADDR |
361 PHY_IAC_REG(devad) |
362 PHY_IAC_ADDR(phy_addr) |
363 PHY_IAC_DATA(phy_reg),
364 MTK_PHY_IAC);
365
366 ret = mtk_mdio_busy_wait(eth);
367 if (ret < 0)
368 return ret;
369
370 mtk_w32(eth, PHY_IAC_ACCESS |
371 PHY_IAC_START_C45 |
372 PHY_IAC_CMD_WRITE |
373 PHY_IAC_REG(devad) |
374 PHY_IAC_ADDR(phy_addr) |
375 PHY_IAC_DATA(write_data),
376 MTK_PHY_IAC);
377
378 ret = mtk_mdio_busy_wait(eth);
379 if (ret < 0)
380 return ret;
381
382 return 0;
383 }
384
_mtk_mdio_read_c22(struct mtk_eth * eth,u32 phy_addr,u32 phy_reg)385 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
386 {
387 int ret;
388
389 ret = mtk_mdio_busy_wait(eth);
390 if (ret < 0)
391 return ret;
392
393 mtk_w32(eth, PHY_IAC_ACCESS |
394 PHY_IAC_START_C22 |
395 PHY_IAC_CMD_C22_READ |
396 PHY_IAC_REG(phy_reg) |
397 PHY_IAC_ADDR(phy_addr),
398 MTK_PHY_IAC);
399
400 ret = mtk_mdio_busy_wait(eth);
401 if (ret < 0)
402 return ret;
403
404 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
405 }
406
_mtk_mdio_read_c45(struct mtk_eth * eth,u32 phy_addr,u32 devad,u32 phy_reg)407 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr,
408 u32 devad, u32 phy_reg)
409 {
410 int ret;
411
412 ret = mtk_mdio_busy_wait(eth);
413 if (ret < 0)
414 return ret;
415
416 mtk_w32(eth, PHY_IAC_ACCESS |
417 PHY_IAC_START_C45 |
418 PHY_IAC_CMD_C45_ADDR |
419 PHY_IAC_REG(devad) |
420 PHY_IAC_ADDR(phy_addr) |
421 PHY_IAC_DATA(phy_reg),
422 MTK_PHY_IAC);
423
424 ret = mtk_mdio_busy_wait(eth);
425 if (ret < 0)
426 return ret;
427
428 mtk_w32(eth, PHY_IAC_ACCESS |
429 PHY_IAC_START_C45 |
430 PHY_IAC_CMD_C45_READ |
431 PHY_IAC_REG(devad) |
432 PHY_IAC_ADDR(phy_addr),
433 MTK_PHY_IAC);
434
435 ret = mtk_mdio_busy_wait(eth);
436 if (ret < 0)
437 return ret;
438
439 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
440 }
441
mtk_mdio_write_c22(struct mii_bus * bus,int phy_addr,int phy_reg,u16 val)442 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr,
443 int phy_reg, u16 val)
444 {
445 struct mtk_eth *eth = bus->priv;
446
447 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val);
448 }
449
mtk_mdio_write_c45(struct mii_bus * bus,int phy_addr,int devad,int phy_reg,u16 val)450 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr,
451 int devad, int phy_reg, u16 val)
452 {
453 struct mtk_eth *eth = bus->priv;
454
455 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val);
456 }
457
mtk_mdio_read_c22(struct mii_bus * bus,int phy_addr,int phy_reg)458 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg)
459 {
460 struct mtk_eth *eth = bus->priv;
461
462 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg);
463 }
464
mtk_mdio_read_c45(struct mii_bus * bus,int phy_addr,int devad,int phy_reg)465 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad,
466 int phy_reg)
467 {
468 struct mtk_eth *eth = bus->priv;
469
470 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg);
471 }
472
mt7621_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface)473 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
474 phy_interface_t interface)
475 {
476 u32 val;
477
478 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
479 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
480
481 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
482 ETHSYS_TRGMII_MT7621_MASK, val);
483
484 return 0;
485 }
486
mtk_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface)487 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
488 phy_interface_t interface)
489 {
490 int ret;
491
492 if (interface == PHY_INTERFACE_MODE_TRGMII) {
493 mtk_w32(eth, TRGMII_MODE, INTF_MODE);
494 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000);
495 if (ret)
496 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
497 return;
498 }
499
500 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
501 }
502
mtk_setup_bridge_switch(struct mtk_eth * eth)503 static void mtk_setup_bridge_switch(struct mtk_eth *eth)
504 {
505 /* Force Port1 XGMAC Link Up */
506 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
507 MTK_XGMAC_STS(MTK_GMAC1_ID));
508
509 /* Adjust GSW bridge IPG to 11 */
510 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK,
511 (GSW_IPG_11 << GSWTX_IPG_SHIFT) |
512 (GSW_IPG_11 << GSWRX_IPG_SHIFT),
513 MTK_GSW_CFG);
514 }
515
mtk_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)516 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
517 phy_interface_t interface)
518 {
519 struct mtk_mac *mac = container_of(config, struct mtk_mac,
520 phylink_config);
521 struct mtk_eth *eth = mac->hw;
522 unsigned int sid;
523
524 if (interface == PHY_INTERFACE_MODE_SGMII ||
525 phy_interface_mode_is_8023z(interface)) {
526 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
527 0 : mac->id;
528
529 return eth->sgmii_pcs[sid];
530 }
531
532 return NULL;
533 }
534
mtk_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)535 static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
536 const struct phylink_link_state *state)
537 {
538 struct mtk_mac *mac = container_of(config, struct mtk_mac,
539 phylink_config);
540 struct mtk_eth *eth = mac->hw;
541 int val, ge_mode, err = 0;
542 u32 i;
543
544 /* MT76x8 has no hardware settings between for the MAC */
545 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
546 mac->interface != state->interface) {
547 /* Setup soc pin functions */
548 switch (state->interface) {
549 case PHY_INTERFACE_MODE_TRGMII:
550 case PHY_INTERFACE_MODE_RGMII_TXID:
551 case PHY_INTERFACE_MODE_RGMII_RXID:
552 case PHY_INTERFACE_MODE_RGMII_ID:
553 case PHY_INTERFACE_MODE_RGMII:
554 case PHY_INTERFACE_MODE_MII:
555 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
556 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
557 if (err)
558 goto init_err;
559 }
560 break;
561 case PHY_INTERFACE_MODE_1000BASEX:
562 case PHY_INTERFACE_MODE_2500BASEX:
563 case PHY_INTERFACE_MODE_SGMII:
564 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
565 if (err)
566 goto init_err;
567 break;
568 case PHY_INTERFACE_MODE_GMII:
569 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
570 err = mtk_gmac_gephy_path_setup(eth, mac->id);
571 if (err)
572 goto init_err;
573 }
574 break;
575 case PHY_INTERFACE_MODE_INTERNAL:
576 break;
577 default:
578 goto err_phy;
579 }
580
581 /* Setup clock for 1st gmac */
582 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
583 !phy_interface_mode_is_8023z(state->interface) &&
584 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
585 if (MTK_HAS_CAPS(mac->hw->soc->caps,
586 MTK_TRGMII_MT7621_CLK)) {
587 if (mt7621_gmac0_rgmii_adjust(mac->hw,
588 state->interface))
589 goto err_phy;
590 } else {
591 mtk_gmac0_rgmii_adjust(mac->hw,
592 state->interface);
593
594 /* mt7623_pad_clk_setup */
595 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
596 mtk_w32(mac->hw,
597 TD_DM_DRVP(8) | TD_DM_DRVN(8),
598 TRGMII_TD_ODT(i));
599
600 /* Assert/release MT7623 RXC reset */
601 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
602 TRGMII_RCK_CTRL);
603 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
604 }
605 }
606
607 switch (state->interface) {
608 case PHY_INTERFACE_MODE_MII:
609 case PHY_INTERFACE_MODE_GMII:
610 ge_mode = 1;
611 break;
612 default:
613 ge_mode = 0;
614 break;
615 }
616
617 /* put the gmac into the right mode */
618 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
619 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
620 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
621 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
622
623 mac->interface = state->interface;
624 }
625
626 /* SGMII */
627 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
628 phy_interface_mode_is_8023z(state->interface)) {
629 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
630 * being setup done.
631 */
632 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
633
634 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
635 SYSCFG0_SGMII_MASK,
636 ~(u32)SYSCFG0_SGMII_MASK);
637
638 /* Save the syscfg0 value for mac_finish */
639 mac->syscfg0 = val;
640 } else if (phylink_autoneg_inband(mode)) {
641 dev_err(eth->dev,
642 "In-band mode not supported in non SGMII mode!\n");
643 return;
644 }
645
646 /* Setup gmac */
647 if (mtk_is_netsys_v3_or_greater(eth) &&
648 mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
649 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
650 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
651
652 mtk_setup_bridge_switch(eth);
653 }
654
655 return;
656
657 err_phy:
658 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
659 mac->id, phy_modes(state->interface));
660 return;
661
662 init_err:
663 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
664 mac->id, phy_modes(state->interface), err);
665 }
666
mtk_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)667 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
668 phy_interface_t interface)
669 {
670 struct mtk_mac *mac = container_of(config, struct mtk_mac,
671 phylink_config);
672 struct mtk_eth *eth = mac->hw;
673 u32 mcr_cur, mcr_new;
674
675 /* Enable SGMII */
676 if (interface == PHY_INTERFACE_MODE_SGMII ||
677 phy_interface_mode_is_8023z(interface))
678 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
679 SYSCFG0_SGMII_MASK, mac->syscfg0);
680
681 /* Setup gmac */
682 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
683 mcr_new = mcr_cur;
684 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
685 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS;
686
687 /* Only update control register when needed! */
688 if (mcr_new != mcr_cur)
689 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
690
691 return 0;
692 }
693
mtk_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)694 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
695 phy_interface_t interface)
696 {
697 struct mtk_mac *mac = container_of(config, struct mtk_mac,
698 phylink_config);
699 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
700
701 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK);
702 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
703 }
704
mtk_set_queue_speed(struct mtk_eth * eth,unsigned int idx,int speed)705 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
706 int speed)
707 {
708 const struct mtk_soc_data *soc = eth->soc;
709 u32 ofs, val;
710
711 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
712 return;
713
714 val = MTK_QTX_SCH_MIN_RATE_EN |
715 /* minimum: 10 Mbps */
716 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
717 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
718 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
719 if (mtk_is_netsys_v1(eth))
720 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
721
722 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
723 switch (speed) {
724 case SPEED_10:
725 val |= MTK_QTX_SCH_MAX_RATE_EN |
726 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) |
727 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) |
728 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
729 break;
730 case SPEED_100:
731 val |= MTK_QTX_SCH_MAX_RATE_EN |
732 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) |
733 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3) |
734 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
735 break;
736 case SPEED_1000:
737 val |= MTK_QTX_SCH_MAX_RATE_EN |
738 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) |
739 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) |
740 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10);
741 break;
742 default:
743 break;
744 }
745 } else {
746 switch (speed) {
747 case SPEED_10:
748 val |= MTK_QTX_SCH_MAX_RATE_EN |
749 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
750 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) |
751 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
752 break;
753 case SPEED_100:
754 val |= MTK_QTX_SCH_MAX_RATE_EN |
755 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
756 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) |
757 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
758 break;
759 case SPEED_1000:
760 val |= MTK_QTX_SCH_MAX_RATE_EN |
761 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
762 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 6) |
763 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10);
764 break;
765 default:
766 break;
767 }
768 }
769
770 ofs = MTK_QTX_OFFSET * idx;
771 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
772 }
773
mtk_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)774 static void mtk_mac_link_up(struct phylink_config *config,
775 struct phy_device *phy,
776 unsigned int mode, phy_interface_t interface,
777 int speed, int duplex, bool tx_pause, bool rx_pause)
778 {
779 struct mtk_mac *mac = container_of(config, struct mtk_mac,
780 phylink_config);
781 u32 mcr;
782
783 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
784 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
785 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
786 MAC_MCR_FORCE_RX_FC);
787
788 /* Configure speed */
789 mac->speed = speed;
790 switch (speed) {
791 case SPEED_2500:
792 case SPEED_1000:
793 mcr |= MAC_MCR_SPEED_1000;
794 break;
795 case SPEED_100:
796 mcr |= MAC_MCR_SPEED_100;
797 break;
798 }
799
800 /* Configure duplex */
801 if (duplex == DUPLEX_FULL)
802 mcr |= MAC_MCR_FORCE_DPX;
803
804 /* Configure pause modes - phylink will avoid these for half duplex */
805 if (tx_pause)
806 mcr |= MAC_MCR_FORCE_TX_FC;
807 if (rx_pause)
808 mcr |= MAC_MCR_FORCE_RX_FC;
809
810 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK;
811 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
812 }
813
814 static const struct phylink_mac_ops mtk_phylink_ops = {
815 .mac_select_pcs = mtk_mac_select_pcs,
816 .mac_config = mtk_mac_config,
817 .mac_finish = mtk_mac_finish,
818 .mac_link_down = mtk_mac_link_down,
819 .mac_link_up = mtk_mac_link_up,
820 };
821
mtk_mdio_config(struct mtk_eth * eth)822 static void mtk_mdio_config(struct mtk_eth *eth)
823 {
824 u32 val;
825
826 /* Configure MDC Divider */
827 val = FIELD_PREP(PPSC_MDC_CFG, eth->mdc_divider);
828
829 /* Configure MDC Turbo Mode */
830 if (mtk_is_netsys_v3_or_greater(eth))
831 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);
832 else
833 val |= PPSC_MDC_TURBO;
834
835 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);
836 }
837
mtk_mdio_init(struct mtk_eth * eth)838 static int mtk_mdio_init(struct mtk_eth *eth)
839 {
840 unsigned int max_clk = 2500000;
841 struct device_node *mii_np;
842 int ret;
843 u32 val;
844
845 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
846 if (!mii_np) {
847 dev_err(eth->dev, "no %s child node found", "mdio-bus");
848 return -ENODEV;
849 }
850
851 if (!of_device_is_available(mii_np)) {
852 ret = -ENODEV;
853 goto err_put_node;
854 }
855
856 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
857 if (!eth->mii_bus) {
858 ret = -ENOMEM;
859 goto err_put_node;
860 }
861
862 eth->mii_bus->name = "mdio";
863 eth->mii_bus->read = mtk_mdio_read_c22;
864 eth->mii_bus->write = mtk_mdio_write_c22;
865 eth->mii_bus->read_c45 = mtk_mdio_read_c45;
866 eth->mii_bus->write_c45 = mtk_mdio_write_c45;
867 eth->mii_bus->priv = eth;
868 eth->mii_bus->parent = eth->dev;
869
870 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
871
872 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) {
873 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
874 dev_err(eth->dev, "MDIO clock frequency out of range");
875 ret = -EINVAL;
876 goto err_put_node;
877 }
878 max_clk = val;
879 }
880 eth->mdc_divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
881 mtk_mdio_config(eth);
882 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / eth->mdc_divider);
883 ret = of_mdiobus_register(eth->mii_bus, mii_np);
884
885 err_put_node:
886 of_node_put(mii_np);
887 return ret;
888 }
889
mtk_mdio_cleanup(struct mtk_eth * eth)890 static void mtk_mdio_cleanup(struct mtk_eth *eth)
891 {
892 if (!eth->mii_bus)
893 return;
894
895 mdiobus_unregister(eth->mii_bus);
896 }
897
mtk_tx_irq_disable(struct mtk_eth * eth,u32 mask)898 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
899 {
900 unsigned long flags;
901 u32 val;
902
903 spin_lock_irqsave(ð->tx_irq_lock, flags);
904 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
905 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask);
906 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
907 }
908
mtk_tx_irq_enable(struct mtk_eth * eth,u32 mask)909 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
910 {
911 unsigned long flags;
912 u32 val;
913
914 spin_lock_irqsave(ð->tx_irq_lock, flags);
915 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
916 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask);
917 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
918 }
919
mtk_rx_irq_disable(struct mtk_eth * eth,u32 mask)920 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
921 {
922 unsigned long flags;
923 u32 val;
924
925 spin_lock_irqsave(ð->rx_irq_lock, flags);
926 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
927 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);
928 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
929 }
930
mtk_rx_irq_enable(struct mtk_eth * eth,u32 mask)931 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
932 {
933 unsigned long flags;
934 u32 val;
935
936 spin_lock_irqsave(ð->rx_irq_lock, flags);
937 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
938 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);
939 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
940 }
941
mtk_set_mac_address(struct net_device * dev,void * p)942 static int mtk_set_mac_address(struct net_device *dev, void *p)
943 {
944 int ret = eth_mac_addr(dev, p);
945 struct mtk_mac *mac = netdev_priv(dev);
946 struct mtk_eth *eth = mac->hw;
947 const char *macaddr = dev->dev_addr;
948
949 if (ret)
950 return ret;
951
952 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
953 return -EBUSY;
954
955 spin_lock_bh(&mac->hw->page_lock);
956 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
957 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
958 MT7628_SDM_MAC_ADRH);
959 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
960 (macaddr[4] << 8) | macaddr[5],
961 MT7628_SDM_MAC_ADRL);
962 } else {
963 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
964 MTK_GDMA_MAC_ADRH(mac->id));
965 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
966 (macaddr[4] << 8) | macaddr[5],
967 MTK_GDMA_MAC_ADRL(mac->id));
968 }
969 spin_unlock_bh(&mac->hw->page_lock);
970
971 return 0;
972 }
973
mtk_stats_update_mac(struct mtk_mac * mac)974 void mtk_stats_update_mac(struct mtk_mac *mac)
975 {
976 struct mtk_hw_stats *hw_stats = mac->hw_stats;
977 struct mtk_eth *eth = mac->hw;
978
979 u64_stats_update_begin(&hw_stats->syncp);
980
981 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
982 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
983 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
984 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
985 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
986 hw_stats->rx_checksum_errors +=
987 mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
988 } else {
989 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
990 unsigned int offs = hw_stats->reg_offset;
991 u64 stats;
992
993 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs);
994 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs);
995 if (stats)
996 hw_stats->rx_bytes += (stats << 32);
997 hw_stats->rx_packets +=
998 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs);
999 hw_stats->rx_overflow +=
1000 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs);
1001 hw_stats->rx_fcs_errors +=
1002 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs);
1003 hw_stats->rx_short_errors +=
1004 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs);
1005 hw_stats->rx_long_errors +=
1006 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs);
1007 hw_stats->rx_checksum_errors +=
1008 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
1009 hw_stats->rx_flow_control_packets +=
1010 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
1011
1012 if (mtk_is_netsys_v3_or_greater(eth)) {
1013 hw_stats->tx_skip +=
1014 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs);
1015 hw_stats->tx_collisions +=
1016 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs);
1017 hw_stats->tx_bytes +=
1018 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs);
1019 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs);
1020 if (stats)
1021 hw_stats->tx_bytes += (stats << 32);
1022 hw_stats->tx_packets +=
1023 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs);
1024 } else {
1025 hw_stats->tx_skip +=
1026 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
1027 hw_stats->tx_collisions +=
1028 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
1029 hw_stats->tx_bytes +=
1030 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
1031 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
1032 if (stats)
1033 hw_stats->tx_bytes += (stats << 32);
1034 hw_stats->tx_packets +=
1035 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
1036 }
1037 }
1038
1039 u64_stats_update_end(&hw_stats->syncp);
1040 }
1041
mtk_stats_update(struct mtk_eth * eth)1042 static void mtk_stats_update(struct mtk_eth *eth)
1043 {
1044 int i;
1045
1046 for (i = 0; i < MTK_MAX_DEVS; i++) {
1047 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
1048 continue;
1049 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
1050 mtk_stats_update_mac(eth->mac[i]);
1051 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
1052 }
1053 }
1054 }
1055
mtk_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * storage)1056 static void mtk_get_stats64(struct net_device *dev,
1057 struct rtnl_link_stats64 *storage)
1058 {
1059 struct mtk_mac *mac = netdev_priv(dev);
1060 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1061 unsigned int start;
1062
1063 if (netif_running(dev) && netif_device_present(dev)) {
1064 if (spin_trylock_bh(&hw_stats->stats_lock)) {
1065 mtk_stats_update_mac(mac);
1066 spin_unlock_bh(&hw_stats->stats_lock);
1067 }
1068 }
1069
1070 do {
1071 start = u64_stats_fetch_begin(&hw_stats->syncp);
1072 storage->rx_packets = hw_stats->rx_packets;
1073 storage->tx_packets = hw_stats->tx_packets;
1074 storage->rx_bytes = hw_stats->rx_bytes;
1075 storage->tx_bytes = hw_stats->tx_bytes;
1076 storage->collisions = hw_stats->tx_collisions;
1077 storage->rx_length_errors = hw_stats->rx_short_errors +
1078 hw_stats->rx_long_errors;
1079 storage->rx_over_errors = hw_stats->rx_overflow;
1080 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
1081 storage->rx_errors = hw_stats->rx_checksum_errors;
1082 storage->tx_aborted_errors = hw_stats->tx_skip;
1083 } while (u64_stats_fetch_retry(&hw_stats->syncp, start));
1084
1085 storage->tx_errors = dev->stats.tx_errors;
1086 storage->rx_dropped = dev->stats.rx_dropped;
1087 storage->tx_dropped = dev->stats.tx_dropped;
1088 }
1089
mtk_max_frag_size(int mtu)1090 static inline int mtk_max_frag_size(int mtu)
1091 {
1092 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
1093 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K)
1094 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
1095
1096 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
1097 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1098 }
1099
mtk_max_buf_size(int frag_size)1100 static inline int mtk_max_buf_size(int frag_size)
1101 {
1102 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
1103 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1104
1105 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K);
1106
1107 return buf_size;
1108 }
1109
mtk_rx_get_desc(struct mtk_eth * eth,struct mtk_rx_dma_v2 * rxd,struct mtk_rx_dma_v2 * dma_rxd)1110 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd,
1111 struct mtk_rx_dma_v2 *dma_rxd)
1112 {
1113 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
1114 if (!(rxd->rxd2 & RX_DMA_DONE))
1115 return false;
1116
1117 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
1118 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
1119 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
1120 if (mtk_is_netsys_v3_or_greater(eth)) {
1121 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
1122 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
1123 }
1124
1125 return true;
1126 }
1127
mtk_max_lro_buf_alloc(gfp_t gfp_mask)1128 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
1129 {
1130 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH);
1131 unsigned long data;
1132
1133 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN,
1134 get_order(size));
1135
1136 return (void *)data;
1137 }
1138
1139 /* the qdma core needs scratch memory to be setup */
mtk_init_fq_dma(struct mtk_eth * eth)1140 static int mtk_init_fq_dma(struct mtk_eth *eth)
1141 {
1142 const struct mtk_soc_data *soc = eth->soc;
1143 dma_addr_t phy_ring_tail;
1144 int cnt = soc->tx.fq_dma_size;
1145 dma_addr_t dma_addr;
1146 int i, j, len;
1147
1148 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM))
1149 eth->scratch_ring = eth->sram_base;
1150 else
1151 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
1152 cnt * soc->tx.desc_size,
1153 ð->phy_scratch_ring,
1154 GFP_KERNEL);
1155
1156 if (unlikely(!eth->scratch_ring))
1157 return -ENOMEM;
1158
1159 phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
1160
1161 for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) {
1162 len = min_t(int, cnt - j * MTK_FQ_DMA_LENGTH, MTK_FQ_DMA_LENGTH);
1163 eth->scratch_head[j] = kcalloc(len, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
1164
1165 if (unlikely(!eth->scratch_head[j]))
1166 return -ENOMEM;
1167
1168 dma_addr = dma_map_single(eth->dma_dev,
1169 eth->scratch_head[j], len * MTK_QDMA_PAGE_SIZE,
1170 DMA_FROM_DEVICE);
1171
1172 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
1173 return -ENOMEM;
1174
1175 for (i = 0; i < len; i++) {
1176 struct mtk_tx_dma_v2 *txd;
1177
1178 txd = eth->scratch_ring + (j * MTK_FQ_DMA_LENGTH + i) * soc->tx.desc_size;
1179 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
1180 if (j * MTK_FQ_DMA_LENGTH + i < cnt)
1181 txd->txd2 = eth->phy_scratch_ring +
1182 (j * MTK_FQ_DMA_LENGTH + i + 1) * soc->tx.desc_size;
1183
1184 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
1185 if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA))
1186 txd->txd3 |= TX_DMA_PREP_ADDR64(dma_addr + i * MTK_QDMA_PAGE_SIZE);
1187
1188 txd->txd4 = 0;
1189 if (mtk_is_netsys_v2_or_greater(eth)) {
1190 txd->txd5 = 0;
1191 txd->txd6 = 0;
1192 txd->txd7 = 0;
1193 txd->txd8 = 0;
1194 }
1195 }
1196 }
1197
1198 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head);
1199 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail);
1200 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count);
1201 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen);
1202
1203 return 0;
1204 }
1205
mtk_qdma_phys_to_virt(struct mtk_tx_ring * ring,u32 desc)1206 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
1207 {
1208 return ring->dma + (desc - ring->phys);
1209 }
1210
mtk_desc_to_tx_buf(struct mtk_tx_ring * ring,void * txd,u32 txd_size)1211 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
1212 void *txd, u32 txd_size)
1213 {
1214 int idx = (txd - ring->dma) / txd_size;
1215
1216 return &ring->buf[idx];
1217 }
1218
qdma_to_pdma(struct mtk_tx_ring * ring,struct mtk_tx_dma * dma)1219 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
1220 struct mtk_tx_dma *dma)
1221 {
1222 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma;
1223 }
1224
txd_to_idx(struct mtk_tx_ring * ring,void * dma,u32 txd_size)1225 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size)
1226 {
1227 return (dma - ring->dma) / txd_size;
1228 }
1229
mtk_tx_unmap(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct xdp_frame_bulk * bq,bool napi)1230 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1231 struct xdp_frame_bulk *bq, bool napi)
1232 {
1233 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1234 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
1235 dma_unmap_single(eth->dma_dev,
1236 dma_unmap_addr(tx_buf, dma_addr0),
1237 dma_unmap_len(tx_buf, dma_len0),
1238 DMA_TO_DEVICE);
1239 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
1240 dma_unmap_page(eth->dma_dev,
1241 dma_unmap_addr(tx_buf, dma_addr0),
1242 dma_unmap_len(tx_buf, dma_len0),
1243 DMA_TO_DEVICE);
1244 }
1245 } else {
1246 if (dma_unmap_len(tx_buf, dma_len0)) {
1247 dma_unmap_page(eth->dma_dev,
1248 dma_unmap_addr(tx_buf, dma_addr0),
1249 dma_unmap_len(tx_buf, dma_len0),
1250 DMA_TO_DEVICE);
1251 }
1252
1253 if (dma_unmap_len(tx_buf, dma_len1)) {
1254 dma_unmap_page(eth->dma_dev,
1255 dma_unmap_addr(tx_buf, dma_addr1),
1256 dma_unmap_len(tx_buf, dma_len1),
1257 DMA_TO_DEVICE);
1258 }
1259 }
1260
1261 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
1262 if (tx_buf->type == MTK_TYPE_SKB) {
1263 struct sk_buff *skb = tx_buf->data;
1264
1265 if (napi)
1266 napi_consume_skb(skb, napi);
1267 else
1268 dev_kfree_skb_any(skb);
1269 } else {
1270 struct xdp_frame *xdpf = tx_buf->data;
1271
1272 if (napi && tx_buf->type == MTK_TYPE_XDP_TX)
1273 xdp_return_frame_rx_napi(xdpf);
1274 else if (bq)
1275 xdp_return_frame_bulk(xdpf, bq);
1276 else
1277 xdp_return_frame(xdpf);
1278 }
1279 }
1280 tx_buf->flags = 0;
1281 tx_buf->data = NULL;
1282 }
1283
setup_tx_buf(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct mtk_tx_dma * txd,dma_addr_t mapped_addr,size_t size,int idx)1284 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1285 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
1286 size_t size, int idx)
1287 {
1288 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1289 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1290 dma_unmap_len_set(tx_buf, dma_len0, size);
1291 } else {
1292 if (idx & 1) {
1293 txd->txd3 = mapped_addr;
1294 txd->txd2 |= TX_DMA_PLEN1(size);
1295 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
1296 dma_unmap_len_set(tx_buf, dma_len1, size);
1297 } else {
1298 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1299 txd->txd1 = mapped_addr;
1300 txd->txd2 = TX_DMA_PLEN0(size);
1301 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1302 dma_unmap_len_set(tx_buf, dma_len0, size);
1303 }
1304 }
1305 }
1306
mtk_tx_set_dma_desc_v1(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1307 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd,
1308 struct mtk_tx_dma_desc_info *info)
1309 {
1310 struct mtk_mac *mac = netdev_priv(dev);
1311 struct mtk_eth *eth = mac->hw;
1312 struct mtk_tx_dma *desc = txd;
1313 u32 data;
1314
1315 WRITE_ONCE(desc->txd1, info->addr);
1316
1317 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) |
1318 FIELD_PREP(TX_DMA_PQID, info->qid);
1319 if (info->last)
1320 data |= TX_DMA_LS0;
1321 WRITE_ONCE(desc->txd3, data);
1322
1323 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */
1324 if (info->first) {
1325 if (info->gso)
1326 data |= TX_DMA_TSO;
1327 /* tx checksum offload */
1328 if (info->csum)
1329 data |= TX_DMA_CHKSUM;
1330 /* vlan header offload */
1331 if (info->vlan)
1332 data |= TX_DMA_INS_VLAN | info->vlan_tci;
1333 }
1334 WRITE_ONCE(desc->txd4, data);
1335 }
1336
mtk_tx_set_dma_desc_v2(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1337 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd,
1338 struct mtk_tx_dma_desc_info *info)
1339 {
1340 struct mtk_mac *mac = netdev_priv(dev);
1341 struct mtk_tx_dma_v2 *desc = txd;
1342 struct mtk_eth *eth = mac->hw;
1343 u32 data;
1344
1345 WRITE_ONCE(desc->txd1, info->addr);
1346
1347 data = TX_DMA_PLEN0(info->size);
1348 if (info->last)
1349 data |= TX_DMA_LS0;
1350
1351 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
1352 data |= TX_DMA_PREP_ADDR64(info->addr);
1353
1354 WRITE_ONCE(desc->txd3, data);
1355
1356 /* set forward port */
1357 switch (mac->id) {
1358 case MTK_GMAC1_ID:
1359 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
1360 break;
1361 case MTK_GMAC2_ID:
1362 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
1363 break;
1364 case MTK_GMAC3_ID:
1365 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
1366 break;
1367 }
1368
1369 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
1370 WRITE_ONCE(desc->txd4, data);
1371
1372 data = 0;
1373 if (info->first) {
1374 if (info->gso)
1375 data |= TX_DMA_TSO_V2;
1376 /* tx checksum offload */
1377 if (info->csum)
1378 data |= TX_DMA_CHKSUM_V2;
1379 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev))
1380 data |= TX_DMA_SPTAG_V3;
1381 }
1382 WRITE_ONCE(desc->txd5, data);
1383
1384 data = 0;
1385 if (info->first && info->vlan)
1386 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci;
1387 WRITE_ONCE(desc->txd6, data);
1388
1389 WRITE_ONCE(desc->txd7, 0);
1390 WRITE_ONCE(desc->txd8, 0);
1391 }
1392
mtk_tx_set_dma_desc(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1393 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd,
1394 struct mtk_tx_dma_desc_info *info)
1395 {
1396 struct mtk_mac *mac = netdev_priv(dev);
1397 struct mtk_eth *eth = mac->hw;
1398
1399 if (mtk_is_netsys_v2_or_greater(eth))
1400 mtk_tx_set_dma_desc_v2(dev, txd, info);
1401 else
1402 mtk_tx_set_dma_desc_v1(dev, txd, info);
1403 }
1404
mtk_tx_map(struct sk_buff * skb,struct net_device * dev,int tx_num,struct mtk_tx_ring * ring,bool gso)1405 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
1406 int tx_num, struct mtk_tx_ring *ring, bool gso)
1407 {
1408 struct mtk_tx_dma_desc_info txd_info = {
1409 .size = skb_headlen(skb),
1410 .gso = gso,
1411 .csum = skb->ip_summed == CHECKSUM_PARTIAL,
1412 .vlan = skb_vlan_tag_present(skb),
1413 .qid = skb_get_queue_mapping(skb),
1414 .vlan_tci = skb_vlan_tag_get(skb),
1415 .first = true,
1416 .last = !skb_is_nonlinear(skb),
1417 };
1418 struct netdev_queue *txq;
1419 struct mtk_mac *mac = netdev_priv(dev);
1420 struct mtk_eth *eth = mac->hw;
1421 const struct mtk_soc_data *soc = eth->soc;
1422 struct mtk_tx_dma *itxd, *txd;
1423 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
1424 struct mtk_tx_buf *itx_buf, *tx_buf;
1425 int i, n_desc = 1;
1426 int queue = skb_get_queue_mapping(skb);
1427 int k = 0;
1428
1429 txq = netdev_get_tx_queue(dev, queue);
1430 itxd = ring->next_free;
1431 itxd_pdma = qdma_to_pdma(ring, itxd);
1432 if (itxd == ring->last_free)
1433 return -ENOMEM;
1434
1435 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
1436 memset(itx_buf, 0, sizeof(*itx_buf));
1437
1438 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
1439 DMA_TO_DEVICE);
1440 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1441 return -ENOMEM;
1442
1443 mtk_tx_set_dma_desc(dev, itxd, &txd_info);
1444
1445 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1446 itx_buf->mac_id = mac->id;
1447 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
1448 k++);
1449
1450 /* TX SG offload */
1451 txd = itxd;
1452 txd_pdma = qdma_to_pdma(ring, txd);
1453
1454 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1455 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1456 unsigned int offset = 0;
1457 int frag_size = skb_frag_size(frag);
1458
1459 while (frag_size) {
1460 bool new_desc = true;
1461
1462 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) ||
1463 (i & 0x1)) {
1464 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1465 txd_pdma = qdma_to_pdma(ring, txd);
1466 if (txd == ring->last_free)
1467 goto err_dma;
1468
1469 n_desc++;
1470 } else {
1471 new_desc = false;
1472 }
1473
1474 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1475 txd_info.size = min_t(unsigned int, frag_size,
1476 soc->tx.dma_max_len);
1477 txd_info.qid = queue;
1478 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
1479 !(frag_size - txd_info.size);
1480 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
1481 offset, txd_info.size,
1482 DMA_TO_DEVICE);
1483 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1484 goto err_dma;
1485
1486 mtk_tx_set_dma_desc(dev, txd, &txd_info);
1487
1488 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1489 soc->tx.desc_size);
1490 if (new_desc)
1491 memset(tx_buf, 0, sizeof(*tx_buf));
1492 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1493 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
1494 tx_buf->mac_id = mac->id;
1495
1496 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
1497 txd_info.size, k++);
1498
1499 frag_size -= txd_info.size;
1500 offset += txd_info.size;
1501 }
1502 }
1503
1504 /* store skb to cleanup */
1505 itx_buf->type = MTK_TYPE_SKB;
1506 itx_buf->data = skb;
1507
1508 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1509 if (k & 0x1)
1510 txd_pdma->txd2 |= TX_DMA_LS0;
1511 else
1512 txd_pdma->txd2 |= TX_DMA_LS1;
1513 }
1514
1515 netdev_tx_sent_queue(txq, skb->len);
1516 skb_tx_timestamp(skb);
1517
1518 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1519 atomic_sub(n_desc, &ring->free_count);
1520
1521 /* make sure that all changes to the dma ring are flushed before we
1522 * continue
1523 */
1524 wmb();
1525
1526 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1527 if (netif_xmit_stopped(txq) || !netdev_xmit_more())
1528 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1529 } else {
1530 int next_idx;
1531
1532 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
1533 ring->dma_size);
1534 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1535 }
1536
1537 return 0;
1538
1539 err_dma:
1540 do {
1541 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
1542
1543 /* unmap dma */
1544 mtk_tx_unmap(eth, tx_buf, NULL, false);
1545
1546 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1547 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
1548 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1549
1550 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
1551 itxd_pdma = qdma_to_pdma(ring, itxd);
1552 } while (itxd != txd);
1553
1554 return -ENOMEM;
1555 }
1556
mtk_cal_txd_req(struct mtk_eth * eth,struct sk_buff * skb)1557 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb)
1558 {
1559 int i, nfrags = 1;
1560 skb_frag_t *frag;
1561
1562 if (skb_is_gso(skb)) {
1563 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1564 frag = &skb_shinfo(skb)->frags[i];
1565 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1566 eth->soc->tx.dma_max_len);
1567 }
1568 } else {
1569 nfrags += skb_shinfo(skb)->nr_frags;
1570 }
1571
1572 return nfrags;
1573 }
1574
mtk_queue_stopped(struct mtk_eth * eth)1575 static int mtk_queue_stopped(struct mtk_eth *eth)
1576 {
1577 int i;
1578
1579 for (i = 0; i < MTK_MAX_DEVS; i++) {
1580 if (!eth->netdev[i])
1581 continue;
1582 if (netif_queue_stopped(eth->netdev[i]))
1583 return 1;
1584 }
1585
1586 return 0;
1587 }
1588
mtk_wake_queue(struct mtk_eth * eth)1589 static void mtk_wake_queue(struct mtk_eth *eth)
1590 {
1591 int i;
1592
1593 for (i = 0; i < MTK_MAX_DEVS; i++) {
1594 if (!eth->netdev[i])
1595 continue;
1596 netif_tx_wake_all_queues(eth->netdev[i]);
1597 }
1598 }
1599
mtk_start_xmit(struct sk_buff * skb,struct net_device * dev)1600 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
1601 {
1602 struct mtk_mac *mac = netdev_priv(dev);
1603 struct mtk_eth *eth = mac->hw;
1604 struct mtk_tx_ring *ring = ð->tx_ring;
1605 struct net_device_stats *stats = &dev->stats;
1606 bool gso = false;
1607 int tx_num;
1608
1609 if (skb_vlan_tag_present(skb) &&
1610 !eth_proto_is_802_3(eth_hdr(skb)->h_proto)) {
1611 skb = __vlan_hwaccel_push_inside(skb);
1612 if (!skb)
1613 goto dropped;
1614 }
1615
1616 /* normally we can rely on the stack not calling this more than once,
1617 * however we have 2 queues running on the same ring so we need to lock
1618 * the ring access
1619 */
1620 spin_lock(ð->page_lock);
1621
1622 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1623 goto drop;
1624
1625 tx_num = mtk_cal_txd_req(eth, skb);
1626 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
1627 netif_tx_stop_all_queues(dev);
1628 netif_err(eth, tx_queued, dev,
1629 "Tx Ring full when queue awake!\n");
1630 spin_unlock(ð->page_lock);
1631 return NETDEV_TX_BUSY;
1632 }
1633
1634 /* TSO: fill MSS info in tcp checksum field */
1635 if (skb_is_gso(skb)) {
1636 if (skb_cow_head(skb, 0)) {
1637 netif_warn(eth, tx_err, dev,
1638 "GSO expand head fail.\n");
1639 goto drop;
1640 }
1641
1642 if (skb_shinfo(skb)->gso_type &
1643 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1644 gso = true;
1645 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1646 }
1647 }
1648
1649 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1650 goto drop;
1651
1652 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
1653 netif_tx_stop_all_queues(dev);
1654
1655 spin_unlock(ð->page_lock);
1656
1657 return NETDEV_TX_OK;
1658
1659 drop:
1660 spin_unlock(ð->page_lock);
1661 dev_kfree_skb_any(skb);
1662 dropped:
1663 stats->tx_dropped++;
1664 return NETDEV_TX_OK;
1665 }
1666
mtk_get_rx_ring(struct mtk_eth * eth)1667 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1668 {
1669 int i;
1670 struct mtk_rx_ring *ring;
1671 int idx;
1672
1673 if (!eth->hwlro)
1674 return ð->rx_ring[0];
1675
1676 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1677 struct mtk_rx_dma *rxd;
1678
1679 ring = ð->rx_ring[i];
1680 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1681 rxd = ring->dma + idx * eth->soc->rx.desc_size;
1682 if (rxd->rxd2 & RX_DMA_DONE) {
1683 ring->calc_idx_update = true;
1684 return ring;
1685 }
1686 }
1687
1688 return NULL;
1689 }
1690
mtk_update_rx_cpu_idx(struct mtk_eth * eth)1691 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1692 {
1693 struct mtk_rx_ring *ring;
1694 int i;
1695
1696 if (!eth->hwlro) {
1697 ring = ð->rx_ring[0];
1698 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1699 } else {
1700 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1701 ring = ð->rx_ring[i];
1702 if (ring->calc_idx_update) {
1703 ring->calc_idx_update = false;
1704 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1705 }
1706 }
1707 }
1708 }
1709
mtk_page_pool_enabled(struct mtk_eth * eth)1710 static bool mtk_page_pool_enabled(struct mtk_eth *eth)
1711 {
1712 return mtk_is_netsys_v2_or_greater(eth);
1713 }
1714
mtk_create_page_pool(struct mtk_eth * eth,struct xdp_rxq_info * xdp_q,int id,int size)1715 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
1716 struct xdp_rxq_info *xdp_q,
1717 int id, int size)
1718 {
1719 struct page_pool_params pp_params = {
1720 .order = 0,
1721 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1722 .pool_size = size,
1723 .nid = NUMA_NO_NODE,
1724 .dev = eth->dma_dev,
1725 .offset = MTK_PP_HEADROOM,
1726 .max_len = MTK_PP_MAX_BUF_SIZE,
1727 };
1728 struct page_pool *pp;
1729 int err;
1730
1731 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL
1732 : DMA_FROM_DEVICE;
1733 pp = page_pool_create(&pp_params);
1734 if (IS_ERR(pp))
1735 return pp;
1736
1737 err = __xdp_rxq_info_reg(xdp_q, eth->dummy_dev, id,
1738 eth->rx_napi.napi_id, PAGE_SIZE);
1739 if (err < 0)
1740 goto err_free_pp;
1741
1742 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp);
1743 if (err)
1744 goto err_unregister_rxq;
1745
1746 return pp;
1747
1748 err_unregister_rxq:
1749 xdp_rxq_info_unreg(xdp_q);
1750 err_free_pp:
1751 page_pool_destroy(pp);
1752
1753 return ERR_PTR(err);
1754 }
1755
mtk_page_pool_get_buff(struct page_pool * pp,dma_addr_t * dma_addr,gfp_t gfp_mask)1756 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr,
1757 gfp_t gfp_mask)
1758 {
1759 struct page *page;
1760
1761 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN);
1762 if (!page)
1763 return NULL;
1764
1765 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM;
1766 return page_address(page);
1767 }
1768
mtk_rx_put_buff(struct mtk_rx_ring * ring,void * data,bool napi)1769 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi)
1770 {
1771 if (ring->page_pool)
1772 page_pool_put_full_page(ring->page_pool,
1773 virt_to_head_page(data), napi);
1774 else
1775 skb_free_frag(data);
1776 }
1777
mtk_xdp_frame_map(struct mtk_eth * eth,struct net_device * dev,struct mtk_tx_dma_desc_info * txd_info,struct mtk_tx_dma * txd,struct mtk_tx_buf * tx_buf,void * data,u16 headroom,int index,bool dma_map)1778 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev,
1779 struct mtk_tx_dma_desc_info *txd_info,
1780 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf,
1781 void *data, u16 headroom, int index, bool dma_map)
1782 {
1783 struct mtk_tx_ring *ring = ð->tx_ring;
1784 struct mtk_mac *mac = netdev_priv(dev);
1785 struct mtk_tx_dma *txd_pdma;
1786
1787 if (dma_map) { /* ndo_xdp_xmit */
1788 txd_info->addr = dma_map_single(eth->dma_dev, data,
1789 txd_info->size, DMA_TO_DEVICE);
1790 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr)))
1791 return -ENOMEM;
1792
1793 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1794 } else {
1795 struct page *page = virt_to_head_page(data);
1796
1797 txd_info->addr = page_pool_get_dma_addr(page) +
1798 sizeof(struct xdp_frame) + headroom;
1799 dma_sync_single_for_device(eth->dma_dev, txd_info->addr,
1800 txd_info->size, DMA_BIDIRECTIONAL);
1801 }
1802 mtk_tx_set_dma_desc(dev, txd, txd_info);
1803
1804 tx_buf->mac_id = mac->id;
1805 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
1806 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1807
1808 txd_pdma = qdma_to_pdma(ring, txd);
1809 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size,
1810 index);
1811
1812 return 0;
1813 }
1814
mtk_xdp_submit_frame(struct mtk_eth * eth,struct xdp_frame * xdpf,struct net_device * dev,bool dma_map)1815 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf,
1816 struct net_device *dev, bool dma_map)
1817 {
1818 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
1819 const struct mtk_soc_data *soc = eth->soc;
1820 struct mtk_tx_ring *ring = ð->tx_ring;
1821 struct mtk_mac *mac = netdev_priv(dev);
1822 struct mtk_tx_dma_desc_info txd_info = {
1823 .size = xdpf->len,
1824 .first = true,
1825 .last = !xdp_frame_has_frags(xdpf),
1826 .qid = mac->id,
1827 };
1828 int err, index = 0, n_desc = 1, nr_frags;
1829 struct mtk_tx_buf *htx_buf, *tx_buf;
1830 struct mtk_tx_dma *htxd, *txd;
1831 void *data = xdpf->data;
1832
1833 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1834 return -EBUSY;
1835
1836 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
1837 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags))
1838 return -EBUSY;
1839
1840 spin_lock(ð->page_lock);
1841
1842 txd = ring->next_free;
1843 if (txd == ring->last_free) {
1844 spin_unlock(ð->page_lock);
1845 return -ENOMEM;
1846 }
1847 htxd = txd;
1848
1849 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
1850 memset(tx_buf, 0, sizeof(*tx_buf));
1851 htx_buf = tx_buf;
1852
1853 for (;;) {
1854 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf,
1855 data, xdpf->headroom, index, dma_map);
1856 if (err < 0)
1857 goto unmap;
1858
1859 if (txd_info.last)
1860 break;
1861
1862 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) {
1863 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1864 if (txd == ring->last_free)
1865 goto unmap;
1866
1867 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1868 soc->tx.desc_size);
1869 memset(tx_buf, 0, sizeof(*tx_buf));
1870 n_desc++;
1871 }
1872
1873 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1874 txd_info.size = skb_frag_size(&sinfo->frags[index]);
1875 txd_info.last = index + 1 == nr_frags;
1876 txd_info.qid = mac->id;
1877 data = skb_frag_address(&sinfo->frags[index]);
1878
1879 index++;
1880 }
1881 /* store xdpf for cleanup */
1882 htx_buf->data = xdpf;
1883
1884 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1885 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd);
1886
1887 if (index & 1)
1888 txd_pdma->txd2 |= TX_DMA_LS0;
1889 else
1890 txd_pdma->txd2 |= TX_DMA_LS1;
1891 }
1892
1893 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1894 atomic_sub(n_desc, &ring->free_count);
1895
1896 /* make sure that all changes to the dma ring are flushed before we
1897 * continue
1898 */
1899 wmb();
1900
1901 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1902 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1903 } else {
1904 int idx;
1905
1906 idx = txd_to_idx(ring, txd, soc->tx.desc_size);
1907 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
1908 MT7628_TX_CTX_IDX0);
1909 }
1910
1911 spin_unlock(ð->page_lock);
1912
1913 return 0;
1914
1915 unmap:
1916 while (htxd != txd) {
1917 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
1918 mtk_tx_unmap(eth, tx_buf, NULL, false);
1919
1920 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1921 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1922 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd);
1923
1924 txd_pdma->txd2 = TX_DMA_DESP2_DEF;
1925 }
1926
1927 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2);
1928 }
1929
1930 spin_unlock(ð->page_lock);
1931
1932 return err;
1933 }
1934
mtk_xdp_xmit(struct net_device * dev,int num_frame,struct xdp_frame ** frames,u32 flags)1935 static int mtk_xdp_xmit(struct net_device *dev, int num_frame,
1936 struct xdp_frame **frames, u32 flags)
1937 {
1938 struct mtk_mac *mac = netdev_priv(dev);
1939 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1940 struct mtk_eth *eth = mac->hw;
1941 int i, nxmit = 0;
1942
1943 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
1944 return -EINVAL;
1945
1946 for (i = 0; i < num_frame; i++) {
1947 if (mtk_xdp_submit_frame(eth, frames[i], dev, true))
1948 break;
1949 nxmit++;
1950 }
1951
1952 u64_stats_update_begin(&hw_stats->syncp);
1953 hw_stats->xdp_stats.tx_xdp_xmit += nxmit;
1954 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit;
1955 u64_stats_update_end(&hw_stats->syncp);
1956
1957 return nxmit;
1958 }
1959
mtk_xdp_run(struct mtk_eth * eth,struct mtk_rx_ring * ring,struct xdp_buff * xdp,struct net_device * dev)1960 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring,
1961 struct xdp_buff *xdp, struct net_device *dev)
1962 {
1963 struct mtk_mac *mac = netdev_priv(dev);
1964 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1965 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop;
1966 struct bpf_prog *prog;
1967 u32 act = XDP_PASS;
1968
1969 rcu_read_lock();
1970
1971 prog = rcu_dereference(eth->prog);
1972 if (!prog)
1973 goto out;
1974
1975 act = bpf_prog_run_xdp(prog, xdp);
1976 switch (act) {
1977 case XDP_PASS:
1978 count = &hw_stats->xdp_stats.rx_xdp_pass;
1979 goto update_stats;
1980 case XDP_REDIRECT:
1981 if (unlikely(xdp_do_redirect(dev, xdp, prog))) {
1982 act = XDP_DROP;
1983 break;
1984 }
1985
1986 count = &hw_stats->xdp_stats.rx_xdp_redirect;
1987 goto update_stats;
1988 case XDP_TX: {
1989 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
1990
1991 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) {
1992 count = &hw_stats->xdp_stats.rx_xdp_tx_errors;
1993 act = XDP_DROP;
1994 break;
1995 }
1996
1997 count = &hw_stats->xdp_stats.rx_xdp_tx;
1998 goto update_stats;
1999 }
2000 default:
2001 bpf_warn_invalid_xdp_action(dev, prog, act);
2002 fallthrough;
2003 case XDP_ABORTED:
2004 trace_xdp_exception(dev, prog, act);
2005 fallthrough;
2006 case XDP_DROP:
2007 break;
2008 }
2009
2010 page_pool_put_full_page(ring->page_pool,
2011 virt_to_head_page(xdp->data), true);
2012
2013 update_stats:
2014 u64_stats_update_begin(&hw_stats->syncp);
2015 *count = *count + 1;
2016 u64_stats_update_end(&hw_stats->syncp);
2017 out:
2018 rcu_read_unlock();
2019
2020 return act;
2021 }
2022
mtk_poll_rx(struct napi_struct * napi,int budget,struct mtk_eth * eth)2023 static int mtk_poll_rx(struct napi_struct *napi, int budget,
2024 struct mtk_eth *eth)
2025 {
2026 struct dim_sample dim_sample = {};
2027 struct mtk_rx_ring *ring;
2028 bool xdp_flush = false;
2029 int idx;
2030 struct sk_buff *skb;
2031 u64 addr64 = 0;
2032 u8 *data, *new_data;
2033 struct mtk_rx_dma_v2 *rxd, trxd;
2034 int done = 0, bytes = 0;
2035 dma_addr_t dma_addr = DMA_MAPPING_ERROR;
2036 int ppe_idx = 0;
2037
2038 while (done < budget) {
2039 unsigned int pktlen, *rxdcsum;
2040 struct net_device *netdev;
2041 u32 hash, reason;
2042 int mac = 0;
2043
2044 ring = mtk_get_rx_ring(eth);
2045 if (unlikely(!ring))
2046 goto rx_done;
2047
2048 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
2049 rxd = ring->dma + idx * eth->soc->rx.desc_size;
2050 data = ring->data[idx];
2051
2052 if (!mtk_rx_get_desc(eth, &trxd, rxd))
2053 break;
2054
2055 /* find out which mac the packet come from. values start at 1 */
2056 if (mtk_is_netsys_v3_or_greater(eth)) {
2057 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
2058
2059 switch (val) {
2060 case PSE_GDM1_PORT:
2061 case PSE_GDM2_PORT:
2062 mac = val - 1;
2063 break;
2064 case PSE_GDM3_PORT:
2065 mac = MTK_GMAC3_ID;
2066 break;
2067 default:
2068 break;
2069 }
2070 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
2071 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) {
2072 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
2073 }
2074
2075 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
2076 !eth->netdev[mac]))
2077 goto release_desc;
2078
2079 netdev = eth->netdev[mac];
2080 ppe_idx = eth->mac[mac]->ppe_idx;
2081
2082 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
2083 goto release_desc;
2084
2085 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
2086
2087 /* alloc new buffer */
2088 if (ring->page_pool) {
2089 struct page *page = virt_to_head_page(data);
2090 struct xdp_buff xdp;
2091 u32 ret;
2092
2093 new_data = mtk_page_pool_get_buff(ring->page_pool,
2094 &dma_addr,
2095 GFP_ATOMIC);
2096 if (unlikely(!new_data)) {
2097 netdev->stats.rx_dropped++;
2098 goto release_desc;
2099 }
2100
2101 dma_sync_single_for_cpu(eth->dma_dev,
2102 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM,
2103 pktlen, page_pool_get_dma_dir(ring->page_pool));
2104
2105 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q);
2106 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen,
2107 false);
2108 xdp_buff_clear_frags_flag(&xdp);
2109
2110 ret = mtk_xdp_run(eth, ring, &xdp, netdev);
2111 if (ret == XDP_REDIRECT)
2112 xdp_flush = true;
2113
2114 if (ret != XDP_PASS)
2115 goto skip_rx;
2116
2117 skb = build_skb(data, PAGE_SIZE);
2118 if (unlikely(!skb)) {
2119 page_pool_put_full_page(ring->page_pool,
2120 page, true);
2121 netdev->stats.rx_dropped++;
2122 goto skip_rx;
2123 }
2124
2125 skb_reserve(skb, xdp.data - xdp.data_hard_start);
2126 skb_put(skb, xdp.data_end - xdp.data);
2127 skb_mark_for_recycle(skb);
2128 } else {
2129 if (ring->frag_size <= PAGE_SIZE)
2130 new_data = napi_alloc_frag(ring->frag_size);
2131 else
2132 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC);
2133
2134 if (unlikely(!new_data)) {
2135 netdev->stats.rx_dropped++;
2136 goto release_desc;
2137 }
2138
2139 dma_addr = dma_map_single(eth->dma_dev,
2140 new_data + NET_SKB_PAD + eth->ip_align,
2141 ring->buf_size, DMA_FROM_DEVICE);
2142 if (unlikely(dma_mapping_error(eth->dma_dev,
2143 dma_addr))) {
2144 skb_free_frag(new_data);
2145 netdev->stats.rx_dropped++;
2146 goto release_desc;
2147 }
2148
2149 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2150 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2);
2151
2152 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64),
2153 ring->buf_size, DMA_FROM_DEVICE);
2154
2155 skb = build_skb(data, ring->frag_size);
2156 if (unlikely(!skb)) {
2157 netdev->stats.rx_dropped++;
2158 skb_free_frag(data);
2159 goto skip_rx;
2160 }
2161
2162 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
2163 skb_put(skb, pktlen);
2164 }
2165
2166 skb->dev = netdev;
2167 bytes += skb->len;
2168
2169 if (mtk_is_netsys_v3_or_greater(eth)) {
2170 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
2171 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
2172 if (hash != MTK_RXD5_FOE_ENTRY)
2173 skb_set_hash(skb, jhash_1word(hash, 0),
2174 PKT_HASH_TYPE_L4);
2175 rxdcsum = &trxd.rxd3;
2176 } else {
2177 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);
2178 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
2179 if (hash != MTK_RXD4_FOE_ENTRY)
2180 skb_set_hash(skb, jhash_1word(hash, 0),
2181 PKT_HASH_TYPE_L4);
2182 rxdcsum = &trxd.rxd4;
2183 }
2184
2185 if (*rxdcsum & eth->soc->rx.dma_l4_valid)
2186 skb->ip_summed = CHECKSUM_UNNECESSARY;
2187 else
2188 skb_checksum_none_assert(skb);
2189 skb->protocol = eth_type_trans(skb, netdev);
2190
2191 /* When using VLAN untagging in combination with DSA, the
2192 * hardware treats the MTK special tag as a VLAN and untags it.
2193 */
2194 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) &&
2195 netdev_uses_dsa(netdev)) {
2196 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
2197
2198 if (port < ARRAY_SIZE(eth->dsa_meta) &&
2199 eth->dsa_meta[port])
2200 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst);
2201 }
2202
2203 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
2204 mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash);
2205
2206 skb_record_rx_queue(skb, 0);
2207 napi_gro_receive(napi, skb);
2208
2209 skip_rx:
2210 ring->data[idx] = new_data;
2211 rxd->rxd1 = (unsigned int)dma_addr;
2212 release_desc:
2213 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
2214 if (unlikely(dma_addr == DMA_MAPPING_ERROR))
2215 addr64 = FIELD_GET(RX_DMA_ADDR64_MASK,
2216 rxd->rxd2);
2217 else
2218 addr64 = RX_DMA_PREP_ADDR64(dma_addr);
2219 }
2220
2221 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2222 rxd->rxd2 = RX_DMA_LSO;
2223 else
2224 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size) | addr64;
2225
2226 ring->calc_idx = idx;
2227 done++;
2228 }
2229
2230 rx_done:
2231 if (done) {
2232 /* make sure that all changes to the dma ring are flushed before
2233 * we continue
2234 */
2235 wmb();
2236 mtk_update_rx_cpu_idx(eth);
2237 }
2238
2239 eth->rx_packets += done;
2240 eth->rx_bytes += bytes;
2241 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes,
2242 &dim_sample);
2243 net_dim(ð->rx_dim, dim_sample);
2244
2245 if (xdp_flush)
2246 xdp_do_flush();
2247
2248 return done;
2249 }
2250
2251 struct mtk_poll_state {
2252 struct netdev_queue *txq;
2253 unsigned int total;
2254 unsigned int done;
2255 unsigned int bytes;
2256 };
2257
2258 static void
mtk_poll_tx_done(struct mtk_eth * eth,struct mtk_poll_state * state,u8 mac,struct sk_buff * skb)2259 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac,
2260 struct sk_buff *skb)
2261 {
2262 struct netdev_queue *txq;
2263 struct net_device *dev;
2264 unsigned int bytes = skb->len;
2265
2266 state->total++;
2267 eth->tx_packets++;
2268 eth->tx_bytes += bytes;
2269
2270 dev = eth->netdev[mac];
2271 if (!dev)
2272 return;
2273
2274 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
2275 if (state->txq == txq) {
2276 state->done++;
2277 state->bytes += bytes;
2278 return;
2279 }
2280
2281 if (state->txq)
2282 netdev_tx_completed_queue(state->txq, state->done, state->bytes);
2283
2284 state->txq = txq;
2285 state->done = 1;
2286 state->bytes = bytes;
2287 }
2288
mtk_poll_tx_qdma(struct mtk_eth * eth,int budget,struct mtk_poll_state * state)2289 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
2290 struct mtk_poll_state *state)
2291 {
2292 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2293 struct mtk_tx_ring *ring = ð->tx_ring;
2294 struct mtk_tx_buf *tx_buf;
2295 struct xdp_frame_bulk bq;
2296 struct mtk_tx_dma *desc;
2297 u32 cpu, dma;
2298
2299 cpu = ring->last_free_ptr;
2300 dma = mtk_r32(eth, reg_map->qdma.drx_ptr);
2301
2302 desc = mtk_qdma_phys_to_virt(ring, cpu);
2303 xdp_frame_bulk_init(&bq);
2304
2305 while ((cpu != dma) && budget) {
2306 u32 next_cpu = desc->txd2;
2307
2308 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
2309 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
2310 break;
2311
2312 tx_buf = mtk_desc_to_tx_buf(ring, desc,
2313 eth->soc->tx.desc_size);
2314 if (!tx_buf->data)
2315 break;
2316
2317 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2318 if (tx_buf->type == MTK_TYPE_SKB)
2319 mtk_poll_tx_done(eth, state, tx_buf->mac_id,
2320 tx_buf->data);
2321
2322 budget--;
2323 }
2324 mtk_tx_unmap(eth, tx_buf, &bq, true);
2325
2326 ring->last_free = desc;
2327 atomic_inc(&ring->free_count);
2328
2329 cpu = next_cpu;
2330 }
2331 xdp_flush_frame_bulk(&bq);
2332
2333 ring->last_free_ptr = cpu;
2334 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr);
2335
2336 return budget;
2337 }
2338
mtk_poll_tx_pdma(struct mtk_eth * eth,int budget,struct mtk_poll_state * state)2339 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
2340 struct mtk_poll_state *state)
2341 {
2342 struct mtk_tx_ring *ring = ð->tx_ring;
2343 struct mtk_tx_buf *tx_buf;
2344 struct xdp_frame_bulk bq;
2345 struct mtk_tx_dma *desc;
2346 u32 cpu, dma;
2347
2348 cpu = ring->cpu_idx;
2349 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
2350 xdp_frame_bulk_init(&bq);
2351
2352 while ((cpu != dma) && budget) {
2353 tx_buf = &ring->buf[cpu];
2354 if (!tx_buf->data)
2355 break;
2356
2357 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2358 if (tx_buf->type == MTK_TYPE_SKB)
2359 mtk_poll_tx_done(eth, state, 0, tx_buf->data);
2360 budget--;
2361 }
2362 mtk_tx_unmap(eth, tx_buf, &bq, true);
2363
2364 desc = ring->dma + cpu * eth->soc->tx.desc_size;
2365 ring->last_free = desc;
2366 atomic_inc(&ring->free_count);
2367
2368 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
2369 }
2370 xdp_flush_frame_bulk(&bq);
2371
2372 ring->cpu_idx = cpu;
2373
2374 return budget;
2375 }
2376
mtk_poll_tx(struct mtk_eth * eth,int budget)2377 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
2378 {
2379 struct mtk_tx_ring *ring = ð->tx_ring;
2380 struct dim_sample dim_sample = {};
2381 struct mtk_poll_state state = {};
2382
2383 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2384 budget = mtk_poll_tx_qdma(eth, budget, &state);
2385 else
2386 budget = mtk_poll_tx_pdma(eth, budget, &state);
2387
2388 if (state.txq)
2389 netdev_tx_completed_queue(state.txq, state.done, state.bytes);
2390
2391 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
2392 &dim_sample);
2393 net_dim(ð->tx_dim, dim_sample);
2394
2395 if (mtk_queue_stopped(eth) &&
2396 (atomic_read(&ring->free_count) > ring->thresh))
2397 mtk_wake_queue(eth);
2398
2399 return state.total;
2400 }
2401
mtk_handle_status_irq(struct mtk_eth * eth)2402 static void mtk_handle_status_irq(struct mtk_eth *eth)
2403 {
2404 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
2405
2406 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
2407 mtk_stats_update(eth);
2408 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
2409 MTK_INT_STATUS2);
2410 }
2411 }
2412
mtk_napi_tx(struct napi_struct * napi,int budget)2413 static int mtk_napi_tx(struct napi_struct *napi, int budget)
2414 {
2415 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
2416 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2417 int tx_done = 0;
2418
2419 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2420 mtk_handle_status_irq(eth);
2421 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status);
2422 tx_done = mtk_poll_tx(eth, budget);
2423
2424 if (unlikely(netif_msg_intr(eth))) {
2425 dev_info(eth->dev,
2426 "done tx %d, intr 0x%08x/0x%x\n", tx_done,
2427 mtk_r32(eth, reg_map->tx_irq_status),
2428 mtk_r32(eth, reg_map->tx_irq_mask));
2429 }
2430
2431 if (tx_done == budget)
2432 return budget;
2433
2434 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
2435 return budget;
2436
2437 if (napi_complete_done(napi, tx_done))
2438 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2439
2440 return tx_done;
2441 }
2442
mtk_napi_rx(struct napi_struct * napi,int budget)2443 static int mtk_napi_rx(struct napi_struct *napi, int budget)
2444 {
2445 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
2446 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2447 int rx_done_total = 0;
2448
2449 mtk_handle_status_irq(eth);
2450
2451 do {
2452 int rx_done;
2453
2454 mtk_w32(eth, eth->soc->rx.irq_done_mask,
2455 reg_map->pdma.irq_status);
2456 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
2457 rx_done_total += rx_done;
2458
2459 if (unlikely(netif_msg_intr(eth))) {
2460 dev_info(eth->dev,
2461 "done rx %d, intr 0x%08x/0x%x\n", rx_done,
2462 mtk_r32(eth, reg_map->pdma.irq_status),
2463 mtk_r32(eth, reg_map->pdma.irq_mask));
2464 }
2465
2466 if (rx_done_total == budget)
2467 return budget;
2468
2469 } while (mtk_r32(eth, reg_map->pdma.irq_status) &
2470 eth->soc->rx.irq_done_mask);
2471
2472 if (napi_complete_done(napi, rx_done_total))
2473 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
2474
2475 return rx_done_total;
2476 }
2477
mtk_tx_alloc(struct mtk_eth * eth)2478 static int mtk_tx_alloc(struct mtk_eth *eth)
2479 {
2480 const struct mtk_soc_data *soc = eth->soc;
2481 struct mtk_tx_ring *ring = ð->tx_ring;
2482 int i, sz = soc->tx.desc_size;
2483 struct mtk_tx_dma_v2 *txd;
2484 int ring_size;
2485 u32 ofs, val;
2486
2487 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA))
2488 ring_size = MTK_QDMA_RING_SIZE;
2489 else
2490 ring_size = soc->tx.dma_size;
2491
2492 ring->buf = kcalloc(ring_size, sizeof(*ring->buf),
2493 GFP_KERNEL);
2494 if (!ring->buf)
2495 goto no_tx_mem;
2496
2497 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) {
2498 ring->dma = eth->sram_base + soc->tx.fq_dma_size * sz;
2499 ring->phys = eth->phy_scratch_ring + soc->tx.fq_dma_size * (dma_addr_t)sz;
2500 } else {
2501 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
2502 &ring->phys, GFP_KERNEL);
2503 }
2504
2505 if (!ring->dma)
2506 goto no_tx_mem;
2507
2508 for (i = 0; i < ring_size; i++) {
2509 int next = (i + 1) % ring_size;
2510 u32 next_ptr = ring->phys + next * sz;
2511
2512 txd = ring->dma + i * sz;
2513 txd->txd2 = next_ptr;
2514 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
2515 txd->txd4 = 0;
2516 if (mtk_is_netsys_v2_or_greater(eth)) {
2517 txd->txd5 = 0;
2518 txd->txd6 = 0;
2519 txd->txd7 = 0;
2520 txd->txd8 = 0;
2521 }
2522 }
2523
2524 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
2525 * only as the framework. The real HW descriptors are the PDMA
2526 * descriptors in ring->dma_pdma.
2527 */
2528 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2529 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
2530 &ring->phys_pdma, GFP_KERNEL);
2531 if (!ring->dma_pdma)
2532 goto no_tx_mem;
2533
2534 for (i = 0; i < ring_size; i++) {
2535 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
2536 ring->dma_pdma[i].txd4 = 0;
2537 }
2538 }
2539
2540 ring->dma_size = ring_size;
2541 atomic_set(&ring->free_count, ring_size - 2);
2542 ring->next_free = ring->dma;
2543 ring->last_free = (void *)txd;
2544 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz));
2545 ring->thresh = MAX_SKB_FRAGS;
2546
2547 /* make sure that all changes to the dma ring are flushed before we
2548 * continue
2549 */
2550 wmb();
2551
2552 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2553 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
2554 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
2555 mtk_w32(eth,
2556 ring->phys + ((ring_size - 1) * sz),
2557 soc->reg_map->qdma.crx_ptr);
2558 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
2559
2560 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) {
2561 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES;
2562 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
2563
2564 val = MTK_QTX_SCH_MIN_RATE_EN |
2565 /* minimum: 10 Mbps */
2566 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
2567 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
2568 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
2569 if (mtk_is_netsys_v1(eth))
2570 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
2571 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
2572 ofs += MTK_QTX_OFFSET;
2573 }
2574 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16);
2575 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
2576 if (mtk_is_netsys_v2_or_greater(eth))
2577 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
2578 } else {
2579 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
2580 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
2581 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
2582 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
2583 }
2584
2585 return 0;
2586
2587 no_tx_mem:
2588 return -ENOMEM;
2589 }
2590
mtk_tx_clean(struct mtk_eth * eth)2591 static void mtk_tx_clean(struct mtk_eth *eth)
2592 {
2593 const struct mtk_soc_data *soc = eth->soc;
2594 struct mtk_tx_ring *ring = ð->tx_ring;
2595 int i;
2596
2597 if (ring->buf) {
2598 for (i = 0; i < ring->dma_size; i++)
2599 mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
2600 kfree(ring->buf);
2601 ring->buf = NULL;
2602 }
2603 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
2604 dma_free_coherent(eth->dma_dev,
2605 ring->dma_size * soc->tx.desc_size,
2606 ring->dma, ring->phys);
2607 ring->dma = NULL;
2608 }
2609
2610 if (ring->dma_pdma) {
2611 dma_free_coherent(eth->dma_dev,
2612 ring->dma_size * soc->tx.desc_size,
2613 ring->dma_pdma, ring->phys_pdma);
2614 ring->dma_pdma = NULL;
2615 }
2616 }
2617
mtk_rx_alloc(struct mtk_eth * eth,int ring_no,int rx_flag)2618 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
2619 {
2620 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2621 const struct mtk_soc_data *soc = eth->soc;
2622 struct mtk_rx_ring *ring;
2623 int rx_data_len, rx_dma_size, tx_ring_size;
2624 int i;
2625
2626 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2627 tx_ring_size = MTK_QDMA_RING_SIZE;
2628 else
2629 tx_ring_size = soc->tx.dma_size;
2630
2631 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2632 if (ring_no)
2633 return -EINVAL;
2634 ring = ð->rx_ring_qdma;
2635 } else {
2636 ring = ð->rx_ring[ring_no];
2637 }
2638
2639 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
2640 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
2641 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
2642 } else {
2643 rx_data_len = ETH_DATA_LEN;
2644 rx_dma_size = soc->rx.dma_size;
2645 }
2646
2647 ring->frag_size = mtk_max_frag_size(rx_data_len);
2648 ring->buf_size = mtk_max_buf_size(ring->frag_size);
2649 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
2650 GFP_KERNEL);
2651 if (!ring->data)
2652 return -ENOMEM;
2653
2654 if (mtk_page_pool_enabled(eth)) {
2655 struct page_pool *pp;
2656
2657 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no,
2658 rx_dma_size);
2659 if (IS_ERR(pp))
2660 return PTR_ERR(pp);
2661
2662 ring->page_pool = pp;
2663 }
2664
2665 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
2666 rx_flag != MTK_RX_FLAGS_NORMAL) {
2667 ring->dma = dma_alloc_coherent(eth->dma_dev,
2668 rx_dma_size * eth->soc->rx.desc_size,
2669 &ring->phys, GFP_KERNEL);
2670 } else {
2671 struct mtk_tx_ring *tx_ring = ð->tx_ring;
2672
2673 ring->dma = tx_ring->dma + tx_ring_size *
2674 eth->soc->tx.desc_size * (ring_no + 1);
2675 ring->phys = tx_ring->phys + tx_ring_size *
2676 eth->soc->tx.desc_size * (ring_no + 1);
2677 }
2678
2679 if (!ring->dma)
2680 return -ENOMEM;
2681
2682 for (i = 0; i < rx_dma_size; i++) {
2683 struct mtk_rx_dma_v2 *rxd;
2684 dma_addr_t dma_addr;
2685 void *data;
2686
2687 rxd = ring->dma + i * eth->soc->rx.desc_size;
2688 if (ring->page_pool) {
2689 data = mtk_page_pool_get_buff(ring->page_pool,
2690 &dma_addr, GFP_KERNEL);
2691 if (!data)
2692 return -ENOMEM;
2693 } else {
2694 if (ring->frag_size <= PAGE_SIZE)
2695 data = netdev_alloc_frag(ring->frag_size);
2696 else
2697 data = mtk_max_lro_buf_alloc(GFP_KERNEL);
2698
2699 if (!data)
2700 return -ENOMEM;
2701
2702 dma_addr = dma_map_single(eth->dma_dev,
2703 data + NET_SKB_PAD + eth->ip_align,
2704 ring->buf_size, DMA_FROM_DEVICE);
2705 if (unlikely(dma_mapping_error(eth->dma_dev,
2706 dma_addr))) {
2707 skb_free_frag(data);
2708 return -ENOMEM;
2709 }
2710 }
2711 rxd->rxd1 = (unsigned int)dma_addr;
2712 ring->data[i] = data;
2713
2714 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2715 rxd->rxd2 = RX_DMA_LSO;
2716 else
2717 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
2718
2719 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2720 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr);
2721
2722 rxd->rxd3 = 0;
2723 rxd->rxd4 = 0;
2724 if (mtk_is_netsys_v3_or_greater(eth)) {
2725 rxd->rxd5 = 0;
2726 rxd->rxd6 = 0;
2727 rxd->rxd7 = 0;
2728 rxd->rxd8 = 0;
2729 }
2730 }
2731
2732 ring->dma_size = rx_dma_size;
2733 ring->calc_idx_update = false;
2734 ring->calc_idx = rx_dma_size - 1;
2735 if (rx_flag == MTK_RX_FLAGS_QDMA)
2736 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr +
2737 ring_no * MTK_QRX_OFFSET;
2738 else
2739 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr +
2740 ring_no * MTK_QRX_OFFSET;
2741 /* make sure that all changes to the dma ring are flushed before we
2742 * continue
2743 */
2744 wmb();
2745
2746 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2747 mtk_w32(eth, ring->phys,
2748 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2749 mtk_w32(eth, rx_dma_size,
2750 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2751 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2752 reg_map->qdma.rst_idx);
2753 } else {
2754 mtk_w32(eth, ring->phys,
2755 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2756 mtk_w32(eth, rx_dma_size,
2757 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2758 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2759 reg_map->pdma.rst_idx);
2760 }
2761 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
2762
2763 return 0;
2764 }
2765
mtk_rx_clean(struct mtk_eth * eth,struct mtk_rx_ring * ring,bool in_sram)2766 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
2767 {
2768 u64 addr64 = 0;
2769 int i;
2770
2771 if (ring->data && ring->dma) {
2772 for (i = 0; i < ring->dma_size; i++) {
2773 struct mtk_rx_dma *rxd;
2774
2775 if (!ring->data[i])
2776 continue;
2777
2778 rxd = ring->dma + i * eth->soc->rx.desc_size;
2779 if (!rxd->rxd1)
2780 continue;
2781
2782 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2783 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2);
2784
2785 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64),
2786 ring->buf_size, DMA_FROM_DEVICE);
2787 mtk_rx_put_buff(ring, ring->data[i], false);
2788 }
2789 kfree(ring->data);
2790 ring->data = NULL;
2791 }
2792
2793 if (!in_sram && ring->dma) {
2794 dma_free_coherent(eth->dma_dev,
2795 ring->dma_size * eth->soc->rx.desc_size,
2796 ring->dma, ring->phys);
2797 ring->dma = NULL;
2798 }
2799
2800 if (ring->page_pool) {
2801 if (xdp_rxq_info_is_reg(&ring->xdp_q))
2802 xdp_rxq_info_unreg(&ring->xdp_q);
2803 page_pool_destroy(ring->page_pool);
2804 ring->page_pool = NULL;
2805 }
2806 }
2807
mtk_hwlro_rx_init(struct mtk_eth * eth)2808 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
2809 {
2810 int i;
2811 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
2812 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
2813
2814 /* set LRO rings to auto-learn modes */
2815 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
2816
2817 /* validate LRO ring */
2818 ring_ctrl_dw2 |= MTK_RING_VLD;
2819
2820 /* set AGE timer (unit: 20us) */
2821 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
2822 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
2823
2824 /* set max AGG timer (unit: 20us) */
2825 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
2826
2827 /* set max LRO AGG count */
2828 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
2829 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
2830
2831 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2832 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
2833 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
2834 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
2835 }
2836
2837 /* IPv4 checksum update enable */
2838 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
2839
2840 /* switch priority comparison to packet count mode */
2841 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
2842
2843 /* bandwidth threshold setting */
2844 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
2845
2846 /* auto-learn score delta setting */
2847 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
2848
2849 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
2850 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
2851 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
2852
2853 /* set HW LRO mode & the max aggregation count for rx packets */
2854 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
2855
2856 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
2857 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
2858
2859 /* enable HW LRO */
2860 lro_ctrl_dw0 |= MTK_LRO_EN;
2861
2862 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
2863 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
2864
2865 return 0;
2866 }
2867
mtk_hwlro_rx_uninit(struct mtk_eth * eth)2868 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
2869 {
2870 int i;
2871 u32 val;
2872
2873 /* relinquish lro rings, flush aggregated packets */
2874 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
2875
2876 /* wait for relinquishments done */
2877 for (i = 0; i < 10; i++) {
2878 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
2879 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
2880 msleep(20);
2881 continue;
2882 }
2883 break;
2884 }
2885
2886 /* invalidate lro rings */
2887 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2888 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
2889
2890 /* disable HW LRO */
2891 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
2892 }
2893
mtk_hwlro_val_ipaddr(struct mtk_eth * eth,int idx,__be32 ip)2894 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
2895 {
2896 u32 reg_val;
2897
2898 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2899
2900 /* invalidate the IP setting */
2901 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2902
2903 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
2904
2905 /* validate the IP setting */
2906 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2907 }
2908
mtk_hwlro_inval_ipaddr(struct mtk_eth * eth,int idx)2909 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
2910 {
2911 u32 reg_val;
2912
2913 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2914
2915 /* invalidate the IP setting */
2916 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2917
2918 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
2919 }
2920
mtk_hwlro_get_ip_cnt(struct mtk_mac * mac)2921 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
2922 {
2923 int cnt = 0;
2924 int i;
2925
2926 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2927 if (mac->hwlro_ip[i])
2928 cnt++;
2929 }
2930
2931 return cnt;
2932 }
2933
mtk_hwlro_add_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)2934 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
2935 struct ethtool_rxnfc *cmd)
2936 {
2937 struct ethtool_rx_flow_spec *fsp =
2938 (struct ethtool_rx_flow_spec *)&cmd->fs;
2939 struct mtk_mac *mac = netdev_priv(dev);
2940 struct mtk_eth *eth = mac->hw;
2941 int hwlro_idx;
2942
2943 if ((fsp->flow_type != TCP_V4_FLOW) ||
2944 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
2945 (fsp->location > 1))
2946 return -EINVAL;
2947
2948 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
2949 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2950
2951 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2952
2953 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
2954
2955 return 0;
2956 }
2957
mtk_hwlro_del_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)2958 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
2959 struct ethtool_rxnfc *cmd)
2960 {
2961 struct ethtool_rx_flow_spec *fsp =
2962 (struct ethtool_rx_flow_spec *)&cmd->fs;
2963 struct mtk_mac *mac = netdev_priv(dev);
2964 struct mtk_eth *eth = mac->hw;
2965 int hwlro_idx;
2966
2967 if (fsp->location > 1)
2968 return -EINVAL;
2969
2970 mac->hwlro_ip[fsp->location] = 0;
2971 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2972
2973 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2974
2975 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2976
2977 return 0;
2978 }
2979
mtk_hwlro_netdev_disable(struct net_device * dev)2980 static void mtk_hwlro_netdev_disable(struct net_device *dev)
2981 {
2982 struct mtk_mac *mac = netdev_priv(dev);
2983 struct mtk_eth *eth = mac->hw;
2984 int i, hwlro_idx;
2985
2986 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2987 mac->hwlro_ip[i] = 0;
2988 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
2989
2990 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
2991 }
2992
2993 mac->hwlro_ip_cnt = 0;
2994 }
2995
mtk_hwlro_get_fdir_entry(struct net_device * dev,struct ethtool_rxnfc * cmd)2996 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
2997 struct ethtool_rxnfc *cmd)
2998 {
2999 struct mtk_mac *mac = netdev_priv(dev);
3000 struct ethtool_rx_flow_spec *fsp =
3001 (struct ethtool_rx_flow_spec *)&cmd->fs;
3002
3003 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip))
3004 return -EINVAL;
3005
3006 /* only tcp dst ipv4 is meaningful, others are meaningless */
3007 fsp->flow_type = TCP_V4_FLOW;
3008 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
3009 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
3010
3011 fsp->h_u.tcp_ip4_spec.ip4src = 0;
3012 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
3013 fsp->h_u.tcp_ip4_spec.psrc = 0;
3014 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
3015 fsp->h_u.tcp_ip4_spec.pdst = 0;
3016 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
3017 fsp->h_u.tcp_ip4_spec.tos = 0;
3018 fsp->m_u.tcp_ip4_spec.tos = 0xff;
3019
3020 return 0;
3021 }
3022
mtk_hwlro_get_fdir_all(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3023 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
3024 struct ethtool_rxnfc *cmd,
3025 u32 *rule_locs)
3026 {
3027 struct mtk_mac *mac = netdev_priv(dev);
3028 int cnt = 0;
3029 int i;
3030
3031 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
3032 if (cnt == cmd->rule_cnt)
3033 return -EMSGSIZE;
3034
3035 if (mac->hwlro_ip[i]) {
3036 rule_locs[cnt] = i;
3037 cnt++;
3038 }
3039 }
3040
3041 cmd->rule_cnt = cnt;
3042
3043 return 0;
3044 }
3045
mtk_fix_features(struct net_device * dev,netdev_features_t features)3046 static netdev_features_t mtk_fix_features(struct net_device *dev,
3047 netdev_features_t features)
3048 {
3049 if (!(features & NETIF_F_LRO)) {
3050 struct mtk_mac *mac = netdev_priv(dev);
3051 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
3052
3053 if (ip_cnt) {
3054 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
3055
3056 features |= NETIF_F_LRO;
3057 }
3058 }
3059
3060 return features;
3061 }
3062
mtk_set_features(struct net_device * dev,netdev_features_t features)3063 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
3064 {
3065 netdev_features_t diff = dev->features ^ features;
3066
3067 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO))
3068 mtk_hwlro_netdev_disable(dev);
3069
3070 return 0;
3071 }
3072
3073 /* wait for DMA to finish whatever it is doing before we start using it again */
mtk_dma_busy_wait(struct mtk_eth * eth)3074 static int mtk_dma_busy_wait(struct mtk_eth *eth)
3075 {
3076 unsigned int reg;
3077 int ret;
3078 u32 val;
3079
3080 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3081 reg = eth->soc->reg_map->qdma.glo_cfg;
3082 else
3083 reg = eth->soc->reg_map->pdma.glo_cfg;
3084
3085 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
3086 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
3087 5, MTK_DMA_BUSY_TIMEOUT_US);
3088 if (ret)
3089 dev_err(eth->dev, "DMA init timeout\n");
3090
3091 return ret;
3092 }
3093
mtk_dma_init(struct mtk_eth * eth)3094 static int mtk_dma_init(struct mtk_eth *eth)
3095 {
3096 int err;
3097 u32 i;
3098
3099 if (mtk_dma_busy_wait(eth))
3100 return -EBUSY;
3101
3102 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3103 /* QDMA needs scratch memory for internal reordering of the
3104 * descriptors
3105 */
3106 err = mtk_init_fq_dma(eth);
3107 if (err)
3108 return err;
3109 }
3110
3111 err = mtk_tx_alloc(eth);
3112 if (err)
3113 return err;
3114
3115 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3116 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
3117 if (err)
3118 return err;
3119 }
3120
3121 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
3122 if (err)
3123 return err;
3124
3125 if (eth->hwlro) {
3126 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
3127 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
3128 if (err)
3129 return err;
3130 }
3131 err = mtk_hwlro_rx_init(eth);
3132 if (err)
3133 return err;
3134 }
3135
3136 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3137 /* Enable random early drop and set drop threshold
3138 * automatically
3139 */
3140 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
3141 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th);
3142 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred);
3143 }
3144
3145 return 0;
3146 }
3147
mtk_dma_free(struct mtk_eth * eth)3148 static void mtk_dma_free(struct mtk_eth *eth)
3149 {
3150 const struct mtk_soc_data *soc = eth->soc;
3151 int i, j, txqs = 1;
3152
3153 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3154 txqs = MTK_QDMA_NUM_QUEUES;
3155
3156 for (i = 0; i < MTK_MAX_DEVS; i++) {
3157 if (!eth->netdev[i])
3158 continue;
3159
3160 for (j = 0; j < txqs; j++)
3161 netdev_tx_reset_subqueue(eth->netdev[i], j);
3162 }
3163
3164 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
3165 dma_free_coherent(eth->dma_dev,
3166 MTK_QDMA_RING_SIZE * soc->tx.desc_size,
3167 eth->scratch_ring, eth->phy_scratch_ring);
3168 eth->scratch_ring = NULL;
3169 eth->phy_scratch_ring = 0;
3170 }
3171 mtk_tx_clean(eth);
3172 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM));
3173 mtk_rx_clean(eth, ð->rx_ring_qdma, false);
3174
3175 if (eth->hwlro) {
3176 mtk_hwlro_rx_uninit(eth);
3177 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
3178 mtk_rx_clean(eth, ð->rx_ring[i], false);
3179 }
3180
3181 for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) {
3182 kfree(eth->scratch_head[i]);
3183 eth->scratch_head[i] = NULL;
3184 }
3185 }
3186
mtk_hw_reset_check(struct mtk_eth * eth)3187 static bool mtk_hw_reset_check(struct mtk_eth *eth)
3188 {
3189 u32 val = mtk_r32(eth, MTK_INT_STATUS2);
3190
3191 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) ||
3192 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) ||
3193 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL);
3194 }
3195
mtk_tx_timeout(struct net_device * dev,unsigned int txqueue)3196 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
3197 {
3198 struct mtk_mac *mac = netdev_priv(dev);
3199 struct mtk_eth *eth = mac->hw;
3200
3201 if (test_bit(MTK_RESETTING, ð->state))
3202 return;
3203
3204 if (!mtk_hw_reset_check(eth))
3205 return;
3206
3207 eth->netdev[mac->id]->stats.tx_errors++;
3208 netif_err(eth, tx_err, dev, "transmit timed out\n");
3209
3210 schedule_work(ð->pending_work);
3211 }
3212
mtk_handle_irq_rx(int irq,void * _eth)3213 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
3214 {
3215 struct mtk_eth *eth = _eth;
3216
3217 eth->rx_events++;
3218 if (likely(napi_schedule_prep(ð->rx_napi))) {
3219 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
3220 __napi_schedule(ð->rx_napi);
3221 }
3222
3223 return IRQ_HANDLED;
3224 }
3225
mtk_handle_irq_tx(int irq,void * _eth)3226 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
3227 {
3228 struct mtk_eth *eth = _eth;
3229
3230 eth->tx_events++;
3231 if (likely(napi_schedule_prep(ð->tx_napi))) {
3232 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3233 __napi_schedule(ð->tx_napi);
3234 }
3235
3236 return IRQ_HANDLED;
3237 }
3238
mtk_handle_irq(int irq,void * _eth)3239 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
3240 {
3241 struct mtk_eth *eth = _eth;
3242 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3243
3244 if (mtk_r32(eth, reg_map->pdma.irq_mask) &
3245 eth->soc->rx.irq_done_mask) {
3246 if (mtk_r32(eth, reg_map->pdma.irq_status) &
3247 eth->soc->rx.irq_done_mask)
3248 mtk_handle_irq_rx(irq, _eth);
3249 }
3250 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
3251 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
3252 mtk_handle_irq_tx(irq, _eth);
3253 }
3254
3255 return IRQ_HANDLED;
3256 }
3257
3258 #ifdef CONFIG_NET_POLL_CONTROLLER
mtk_poll_controller(struct net_device * dev)3259 static void mtk_poll_controller(struct net_device *dev)
3260 {
3261 struct mtk_mac *mac = netdev_priv(dev);
3262 struct mtk_eth *eth = mac->hw;
3263
3264 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3265 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
3266 mtk_handle_irq_rx(eth->irq[2], dev);
3267 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
3268 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
3269 }
3270 #endif
3271
mtk_start_dma(struct mtk_eth * eth)3272 static int mtk_start_dma(struct mtk_eth *eth)
3273 {
3274 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
3275 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3276 int err;
3277
3278 err = mtk_dma_init(eth);
3279 if (err) {
3280 mtk_dma_free(eth);
3281 return err;
3282 }
3283
3284 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3285 val = mtk_r32(eth, reg_map->qdma.glo_cfg);
3286 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3287 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
3288 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
3289
3290 if (mtk_is_netsys_v2_or_greater(eth))
3291 val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
3292 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
3293 MTK_CHK_DDONE_EN;
3294 else
3295 val |= MTK_RX_BT_32DWORDS;
3296 mtk_w32(eth, val, reg_map->qdma.glo_cfg);
3297
3298 mtk_w32(eth,
3299 MTK_RX_DMA_EN | rx_2b_offset |
3300 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
3301 reg_map->pdma.glo_cfg);
3302 } else {
3303 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3304 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
3305 reg_map->pdma.glo_cfg);
3306 }
3307
3308 return 0;
3309 }
3310
mtk_gdm_config(struct mtk_eth * eth,u32 id,u32 config)3311 static void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config)
3312 {
3313 u32 val;
3314
3315 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3316 return;
3317
3318 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(id));
3319
3320 /* default setup the forward port to send frame to PDMA */
3321 val &= ~0xffff;
3322
3323 /* Enable RX checksum */
3324 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
3325
3326 val |= config;
3327
3328 if (eth->netdev[id] && netdev_uses_dsa(eth->netdev[id]))
3329 val |= MTK_GDMA_SPECIAL_TAG;
3330
3331 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(id));
3332 }
3333
3334
mtk_uses_dsa(struct net_device * dev)3335 static bool mtk_uses_dsa(struct net_device *dev)
3336 {
3337 #if IS_ENABLED(CONFIG_NET_DSA)
3338 return netdev_uses_dsa(dev) &&
3339 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK;
3340 #else
3341 return false;
3342 #endif
3343 }
3344
mtk_device_event(struct notifier_block * n,unsigned long event,void * ptr)3345 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr)
3346 {
3347 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier);
3348 struct mtk_eth *eth = mac->hw;
3349 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3350 struct ethtool_link_ksettings s;
3351 struct net_device *ldev;
3352 struct list_head *iter;
3353 struct dsa_port *dp;
3354
3355 if (event != NETDEV_CHANGE)
3356 return NOTIFY_DONE;
3357
3358 netdev_for_each_lower_dev(dev, ldev, iter) {
3359 if (netdev_priv(ldev) == mac)
3360 goto found;
3361 }
3362
3363 return NOTIFY_DONE;
3364
3365 found:
3366 if (!dsa_user_dev_check(dev))
3367 return NOTIFY_DONE;
3368
3369 if (__ethtool_get_link_ksettings(dev, &s))
3370 return NOTIFY_DONE;
3371
3372 if (s.base.speed == 0 || s.base.speed == ((__u32)-1))
3373 return NOTIFY_DONE;
3374
3375 dp = dsa_port_from_netdev(dev);
3376 if (dp->index >= MTK_QDMA_NUM_QUEUES)
3377 return NOTIFY_DONE;
3378
3379 if (mac->speed > 0 && mac->speed <= s.base.speed)
3380 s.base.speed = 0;
3381
3382 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed);
3383
3384 return NOTIFY_DONE;
3385 }
3386
mtk_open(struct net_device * dev)3387 static int mtk_open(struct net_device *dev)
3388 {
3389 struct mtk_mac *mac = netdev_priv(dev);
3390 struct mtk_eth *eth = mac->hw;
3391 struct mtk_mac *target_mac;
3392 int i, err, ppe_num;
3393
3394 ppe_num = eth->soc->ppe_num;
3395
3396 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
3397 if (err) {
3398 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
3399 err);
3400 return err;
3401 }
3402
3403 /* we run 2 netdevs on the same dma ring so we only bring it up once */
3404 if (!refcount_read(ð->dma_refcnt)) {
3405 const struct mtk_soc_data *soc = eth->soc;
3406 u32 gdm_config;
3407 int i;
3408
3409 err = mtk_start_dma(eth);
3410 if (err) {
3411 phylink_disconnect_phy(mac->phylink);
3412 return err;
3413 }
3414
3415 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3416 mtk_ppe_start(eth->ppe[i]);
3417
3418 for (i = 0; i < MTK_MAX_DEVS; i++) {
3419 if (!eth->netdev[i])
3420 continue;
3421
3422 target_mac = netdev_priv(eth->netdev[i]);
3423 if (!soc->offload_version) {
3424 target_mac->ppe_idx = 0;
3425 gdm_config = MTK_GDMA_TO_PDMA;
3426 } else if (ppe_num >= 3 && target_mac->id == 2) {
3427 target_mac->ppe_idx = 2;
3428 gdm_config = soc->reg_map->gdma_to_ppe[2];
3429 } else if (ppe_num >= 2 && target_mac->id == 1) {
3430 target_mac->ppe_idx = 1;
3431 gdm_config = soc->reg_map->gdma_to_ppe[1];
3432 } else {
3433 target_mac->ppe_idx = 0;
3434 gdm_config = soc->reg_map->gdma_to_ppe[0];
3435 }
3436 mtk_gdm_config(eth, target_mac->id, gdm_config);
3437 }
3438
3439 napi_enable(ð->tx_napi);
3440 napi_enable(ð->rx_napi);
3441 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
3442 mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
3443 refcount_set(ð->dma_refcnt, 1);
3444 } else {
3445 refcount_inc(ð->dma_refcnt);
3446 }
3447
3448 phylink_start(mac->phylink);
3449 netif_tx_start_all_queues(dev);
3450
3451 if (mtk_is_netsys_v2_or_greater(eth))
3452 return 0;
3453
3454 if (mtk_uses_dsa(dev) && !eth->prog) {
3455 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
3456 struct metadata_dst *md_dst = eth->dsa_meta[i];
3457
3458 if (md_dst)
3459 continue;
3460
3461 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX,
3462 GFP_KERNEL);
3463 if (!md_dst)
3464 return -ENOMEM;
3465
3466 md_dst->u.port_info.port_id = i;
3467 eth->dsa_meta[i] = md_dst;
3468 }
3469 } else {
3470 /* Hardware DSA untagging and VLAN RX offloading need to be
3471 * disabled if at least one MAC does not use DSA.
3472 */
3473 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
3474
3475 val &= ~MTK_CDMP_STAG_EN;
3476 mtk_w32(eth, val, MTK_CDMP_IG_CTRL);
3477
3478 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
3479 }
3480
3481 return 0;
3482 }
3483
mtk_stop_dma(struct mtk_eth * eth,u32 glo_cfg)3484 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
3485 {
3486 u32 val;
3487 int i;
3488
3489 /* stop the dma engine */
3490 spin_lock_bh(ð->page_lock);
3491 val = mtk_r32(eth, glo_cfg);
3492 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
3493 glo_cfg);
3494 spin_unlock_bh(ð->page_lock);
3495
3496 /* wait for dma stop */
3497 for (i = 0; i < 10; i++) {
3498 val = mtk_r32(eth, glo_cfg);
3499 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
3500 msleep(20);
3501 continue;
3502 }
3503 break;
3504 }
3505 }
3506
mtk_stop(struct net_device * dev)3507 static int mtk_stop(struct net_device *dev)
3508 {
3509 struct mtk_mac *mac = netdev_priv(dev);
3510 struct mtk_eth *eth = mac->hw;
3511 int i;
3512
3513 phylink_stop(mac->phylink);
3514
3515 netif_tx_disable(dev);
3516
3517 phylink_disconnect_phy(mac->phylink);
3518
3519 /* only shutdown DMA if this is the last user */
3520 if (!refcount_dec_and_test(ð->dma_refcnt))
3521 return 0;
3522
3523 for (i = 0; i < MTK_MAX_DEVS; i++)
3524 mtk_gdm_config(eth, i, MTK_GDMA_DROP_ALL);
3525
3526 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3527 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
3528 napi_disable(ð->tx_napi);
3529 napi_disable(ð->rx_napi);
3530
3531 cancel_work_sync(ð->rx_dim.work);
3532 cancel_work_sync(ð->tx_dim.work);
3533
3534 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3535 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg);
3536 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg);
3537
3538 mtk_dma_free(eth);
3539
3540 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3541 mtk_ppe_stop(eth->ppe[i]);
3542
3543 return 0;
3544 }
3545
mtk_xdp_setup(struct net_device * dev,struct bpf_prog * prog,struct netlink_ext_ack * extack)3546 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
3547 struct netlink_ext_ack *extack)
3548 {
3549 struct mtk_mac *mac = netdev_priv(dev);
3550 struct mtk_eth *eth = mac->hw;
3551 struct bpf_prog *old_prog;
3552 bool need_update;
3553
3554 if (eth->hwlro) {
3555 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO");
3556 return -EOPNOTSUPP;
3557 }
3558
3559 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) {
3560 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP");
3561 return -EOPNOTSUPP;
3562 }
3563
3564 need_update = !!eth->prog != !!prog;
3565 if (netif_running(dev) && need_update)
3566 mtk_stop(dev);
3567
3568 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held());
3569 if (old_prog)
3570 bpf_prog_put(old_prog);
3571
3572 if (netif_running(dev) && need_update)
3573 return mtk_open(dev);
3574
3575 return 0;
3576 }
3577
mtk_xdp(struct net_device * dev,struct netdev_bpf * xdp)3578 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3579 {
3580 switch (xdp->command) {
3581 case XDP_SETUP_PROG:
3582 return mtk_xdp_setup(dev, xdp->prog, xdp->extack);
3583 default:
3584 return -EINVAL;
3585 }
3586 }
3587
ethsys_reset(struct mtk_eth * eth,u32 reset_bits)3588 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
3589 {
3590 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3591 reset_bits,
3592 reset_bits);
3593
3594 usleep_range(1000, 1100);
3595 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3596 reset_bits,
3597 ~reset_bits);
3598 mdelay(10);
3599 }
3600
mtk_clk_disable(struct mtk_eth * eth)3601 static void mtk_clk_disable(struct mtk_eth *eth)
3602 {
3603 int clk;
3604
3605 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
3606 clk_disable_unprepare(eth->clks[clk]);
3607 }
3608
mtk_clk_enable(struct mtk_eth * eth)3609 static int mtk_clk_enable(struct mtk_eth *eth)
3610 {
3611 int clk, ret;
3612
3613 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
3614 ret = clk_prepare_enable(eth->clks[clk]);
3615 if (ret)
3616 goto err_disable_clks;
3617 }
3618
3619 return 0;
3620
3621 err_disable_clks:
3622 while (--clk >= 0)
3623 clk_disable_unprepare(eth->clks[clk]);
3624
3625 return ret;
3626 }
3627
mtk_dim_rx(struct work_struct * work)3628 static void mtk_dim_rx(struct work_struct *work)
3629 {
3630 struct dim *dim = container_of(work, struct dim, work);
3631 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
3632 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3633 struct dim_cq_moder cur_profile;
3634 u32 val, cur;
3635
3636 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode,
3637 dim->profile_ix);
3638 spin_lock_bh(ð->dim_lock);
3639
3640 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3641 val &= MTK_PDMA_DELAY_TX_MASK;
3642 val |= MTK_PDMA_DELAY_RX_EN;
3643
3644 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3645 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT;
3646
3647 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3648 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
3649
3650 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3651 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3652 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3653
3654 spin_unlock_bh(ð->dim_lock);
3655
3656 dim->state = DIM_START_MEASURE;
3657 }
3658
mtk_dim_tx(struct work_struct * work)3659 static void mtk_dim_tx(struct work_struct *work)
3660 {
3661 struct dim *dim = container_of(work, struct dim, work);
3662 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
3663 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3664 struct dim_cq_moder cur_profile;
3665 u32 val, cur;
3666
3667 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode,
3668 dim->profile_ix);
3669 spin_lock_bh(ð->dim_lock);
3670
3671 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3672 val &= MTK_PDMA_DELAY_RX_MASK;
3673 val |= MTK_PDMA_DELAY_TX_EN;
3674
3675 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3676 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT;
3677
3678 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3679 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
3680
3681 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3682 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3683 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3684
3685 spin_unlock_bh(ð->dim_lock);
3686
3687 dim->state = DIM_START_MEASURE;
3688 }
3689
mtk_set_mcr_max_rx(struct mtk_mac * mac,u32 val)3690 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val)
3691 {
3692 struct mtk_eth *eth = mac->hw;
3693 u32 mcr_cur, mcr_new;
3694
3695 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3696 return;
3697
3698 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
3699 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK;
3700
3701 if (val <= 1518)
3702 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518);
3703 else if (val <= 1536)
3704 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536);
3705 else if (val <= 1552)
3706 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552);
3707 else
3708 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048);
3709
3710 if (mcr_new != mcr_cur)
3711 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
3712 }
3713
mtk_hw_reset(struct mtk_eth * eth)3714 static void mtk_hw_reset(struct mtk_eth *eth)
3715 {
3716 u32 val;
3717
3718 if (mtk_is_netsys_v2_or_greater(eth))
3719 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
3720
3721 if (mtk_is_netsys_v3_or_greater(eth)) {
3722 val = RSTCTRL_PPE0_V3;
3723
3724 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3725 val |= RSTCTRL_PPE1_V3;
3726
3727 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
3728 val |= RSTCTRL_PPE2;
3729
3730 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
3731 } else if (mtk_is_netsys_v2_or_greater(eth)) {
3732 val = RSTCTRL_PPE0_V2;
3733
3734 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3735 val |= RSTCTRL_PPE1;
3736 } else {
3737 val = RSTCTRL_PPE0;
3738 }
3739
3740 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
3741
3742 if (mtk_is_netsys_v3_or_greater(eth))
3743 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3744 0x6f8ff);
3745 else if (mtk_is_netsys_v2_or_greater(eth))
3746 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3747 0x3ffffff);
3748 }
3749
mtk_hw_reset_read(struct mtk_eth * eth)3750 static u32 mtk_hw_reset_read(struct mtk_eth *eth)
3751 {
3752 u32 val;
3753
3754 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val);
3755 return val;
3756 }
3757
mtk_hw_warm_reset(struct mtk_eth * eth)3758 static void mtk_hw_warm_reset(struct mtk_eth *eth)
3759 {
3760 u32 rst_mask, val;
3761
3762 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE,
3763 RSTCTRL_FE);
3764 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val,
3765 val & RSTCTRL_FE, 1, 1000)) {
3766 dev_err(eth->dev, "warm reset failed\n");
3767 mtk_hw_reset(eth);
3768 return;
3769 }
3770
3771 if (mtk_is_netsys_v3_or_greater(eth)) {
3772 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3;
3773 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3774 rst_mask |= RSTCTRL_PPE1_V3;
3775 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
3776 rst_mask |= RSTCTRL_PPE2;
3777
3778 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
3779 } else if (mtk_is_netsys_v2_or_greater(eth)) {
3780 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
3781 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3782 rst_mask |= RSTCTRL_PPE1;
3783 } else {
3784 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
3785 }
3786
3787 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
3788
3789 udelay(1);
3790 val = mtk_hw_reset_read(eth);
3791 if (!(val & rst_mask))
3792 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n",
3793 val, rst_mask);
3794
3795 rst_mask |= RSTCTRL_FE;
3796 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask);
3797
3798 udelay(1);
3799 val = mtk_hw_reset_read(eth);
3800 if (val & rst_mask)
3801 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n",
3802 val, rst_mask);
3803 }
3804
mtk_hw_check_dma_hang(struct mtk_eth * eth)3805 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth)
3806 {
3807 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3808 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx;
3809 bool oq_hang, cdm1_busy, adma_busy;
3810 bool wtx_busy, cdm_full, oq_free;
3811 u32 wdidx, val, gdm1_fc, gdm2_fc;
3812 bool qfsm_hang, qfwd_hang;
3813 bool ret = false;
3814
3815 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3816 return false;
3817
3818 /* WDMA sanity checks */
3819 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc);
3820
3821 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204);
3822 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val);
3823
3824 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230);
3825 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val);
3826
3827 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) &&
3828 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) &&
3829 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16)));
3830
3831 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) {
3832 if (++eth->reset.wdma_hang_count > 2) {
3833 eth->reset.wdma_hang_count = 0;
3834 ret = true;
3835 }
3836 goto out;
3837 }
3838
3839 /* QDMA sanity checks */
3840 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234);
3841 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308);
3842
3843 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0;
3844 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0;
3845 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1;
3846 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1;
3847 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24);
3848 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64);
3849
3850 if (qfsm_hang && qfwd_hang &&
3851 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) ||
3852 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) {
3853 if (++eth->reset.qdma_hang_count > 2) {
3854 eth->reset.qdma_hang_count = 0;
3855 ret = true;
3856 }
3857 goto out;
3858 }
3859
3860 /* ADMA sanity checks */
3861 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0));
3862 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16));
3863 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) &&
3864 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6));
3865
3866 if (oq_hang && cdm1_busy && adma_busy) {
3867 if (++eth->reset.adma_hang_count > 2) {
3868 eth->reset.adma_hang_count = 0;
3869 ret = true;
3870 }
3871 goto out;
3872 }
3873
3874 eth->reset.wdma_hang_count = 0;
3875 eth->reset.qdma_hang_count = 0;
3876 eth->reset.adma_hang_count = 0;
3877 out:
3878 eth->reset.wdidx = wdidx;
3879
3880 return ret;
3881 }
3882
mtk_hw_reset_monitor_work(struct work_struct * work)3883 static void mtk_hw_reset_monitor_work(struct work_struct *work)
3884 {
3885 struct delayed_work *del_work = to_delayed_work(work);
3886 struct mtk_eth *eth = container_of(del_work, struct mtk_eth,
3887 reset.monitor_work);
3888
3889 if (test_bit(MTK_RESETTING, ð->state))
3890 goto out;
3891
3892 /* DMA stuck checks */
3893 if (mtk_hw_check_dma_hang(eth))
3894 schedule_work(ð->pending_work);
3895
3896 out:
3897 schedule_delayed_work(ð->reset.monitor_work,
3898 MTK_DMA_MONITOR_TIMEOUT);
3899 }
3900
mtk_hw_init(struct mtk_eth * eth,bool reset)3901 static int mtk_hw_init(struct mtk_eth *eth, bool reset)
3902 {
3903 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
3904 ETHSYS_DMA_AG_MAP_PPE;
3905 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3906 int i, val, ret;
3907
3908 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state))
3909 return 0;
3910
3911 if (!reset) {
3912 pm_runtime_enable(eth->dev);
3913 pm_runtime_get_sync(eth->dev);
3914
3915 ret = mtk_clk_enable(eth);
3916 if (ret)
3917 goto err_disable_pm;
3918 }
3919
3920 if (eth->ethsys)
3921 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
3922 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);
3923
3924 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3925 ret = device_reset(eth->dev);
3926 if (ret) {
3927 dev_err(eth->dev, "MAC reset failed!\n");
3928 goto err_disable_pm;
3929 }
3930
3931 /* set interrupt delays based on current Net DIM sample */
3932 mtk_dim_rx(ð->rx_dim.work);
3933 mtk_dim_tx(ð->tx_dim.work);
3934
3935 /* disable delay and normal interrupt */
3936 mtk_tx_irq_disable(eth, ~0);
3937 mtk_rx_irq_disable(eth, ~0);
3938
3939 return 0;
3940 }
3941
3942 msleep(100);
3943
3944 if (reset)
3945 mtk_hw_warm_reset(eth);
3946 else
3947 mtk_hw_reset(eth);
3948
3949 /* No MT7628/88 support yet */
3950 if (reset && !MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3951 mtk_mdio_config(eth);
3952
3953 if (mtk_is_netsys_v3_or_greater(eth)) {
3954 /* Set FE to PDMAv2 if necessary */
3955 val = mtk_r32(eth, MTK_FE_GLO_MISC);
3956 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
3957 }
3958
3959 if (eth->pctl) {
3960 /* Set GE2 driving and slew rate */
3961 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
3962
3963 /* set GE2 TDSEL */
3964 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
3965
3966 /* set GE2 TUNE */
3967 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
3968 }
3969
3970 /* Set linkdown as the default for each GMAC. Its own MCR would be set
3971 * up with the more appropriate value when mtk_mac_config call is being
3972 * invoked.
3973 */
3974 for (i = 0; i < MTK_MAX_DEVS; i++) {
3975 struct net_device *dev = eth->netdev[i];
3976
3977 if (!dev)
3978 continue;
3979
3980 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
3981 mtk_set_mcr_max_rx(netdev_priv(dev),
3982 dev->mtu + MTK_RX_ETH_HLEN);
3983 }
3984
3985 /* Indicates CDM to parse the MTK special tag from CPU
3986 * which also is working out for untag packets.
3987 */
3988 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
3989 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
3990 if (mtk_is_netsys_v1(eth)) {
3991 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
3992 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
3993
3994 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
3995 }
3996
3997 /* set interrupt delays based on current Net DIM sample */
3998 mtk_dim_rx(ð->rx_dim.work);
3999 mtk_dim_tx(ð->tx_dim.work);
4000
4001 /* disable delay and normal interrupt */
4002 mtk_tx_irq_disable(eth, ~0);
4003 mtk_rx_irq_disable(eth, ~0);
4004
4005 /* FE int grouping */
4006 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
4007 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
4008 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
4009 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
4010 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
4011
4012 if (mtk_is_netsys_v3_or_greater(eth)) {
4013 /* PSE dummy page mechanism */
4014 mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) |
4015 PSE_DUMMY_WORK_GDM(3) | DUMMY_PAGE_THR, PSE_DUMY_REQ);
4016
4017 /* PSE free buffer drop threshold */
4018 mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
4019
4020 /* PSE should not drop port8, port9 and port13 packets from
4021 * WDMA Tx
4022 */
4023 mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
4024
4025 /* PSE should drop packets to port8, port9 and port13 on WDMA Rx
4026 * ring full
4027 */
4028 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0));
4029 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1));
4030 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2));
4031
4032 /* GDM and CDM Threshold */
4033 mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
4034 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
4035
4036 /* Disable GDM1 RX CRC stripping */
4037 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
4038
4039 /* PSE GDM3 MIB counter has incorrect hw default values,
4040 * so the driver ought to read clear the values beforehand
4041 * in case ethtool retrieve wrong mib values.
4042 */
4043 for (i = 0; i < 0x80; i += 0x4)
4044 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i);
4045 } else if (!mtk_is_netsys_v1(eth)) {
4046 /* PSE should not drop port8 and port9 packets from WDMA Tx */
4047 mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
4048
4049 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */
4050 mtk_w32(eth, 0x00000300, PSE_PPE_DROP(0));
4051
4052 /* PSE Free Queue Flow Control */
4053 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
4054
4055 /* PSE config input queue threshold */
4056 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
4057 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
4058 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
4059 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4));
4060 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5));
4061 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6));
4062 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
4063 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
4064
4065 /* PSE config output queue threshold */
4066 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
4067 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
4068 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
4069 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4));
4070 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5));
4071 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
4072 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
4073 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
4074
4075 /* GDM and CDM Threshold */
4076 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
4077 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
4078 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
4079 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
4080 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
4081 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
4082 }
4083
4084 return 0;
4085
4086 err_disable_pm:
4087 if (!reset) {
4088 pm_runtime_put_sync(eth->dev);
4089 pm_runtime_disable(eth->dev);
4090 }
4091
4092 return ret;
4093 }
4094
mtk_hw_deinit(struct mtk_eth * eth)4095 static int mtk_hw_deinit(struct mtk_eth *eth)
4096 {
4097 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
4098 return 0;
4099
4100 mtk_clk_disable(eth);
4101
4102 pm_runtime_put_sync(eth->dev);
4103 pm_runtime_disable(eth->dev);
4104
4105 return 0;
4106 }
4107
mtk_uninit(struct net_device * dev)4108 static void mtk_uninit(struct net_device *dev)
4109 {
4110 struct mtk_mac *mac = netdev_priv(dev);
4111 struct mtk_eth *eth = mac->hw;
4112
4113 phylink_disconnect_phy(mac->phylink);
4114 mtk_tx_irq_disable(eth, ~0);
4115 mtk_rx_irq_disable(eth, ~0);
4116 }
4117
mtk_change_mtu(struct net_device * dev,int new_mtu)4118 static int mtk_change_mtu(struct net_device *dev, int new_mtu)
4119 {
4120 int length = new_mtu + MTK_RX_ETH_HLEN;
4121 struct mtk_mac *mac = netdev_priv(dev);
4122 struct mtk_eth *eth = mac->hw;
4123
4124 if (rcu_access_pointer(eth->prog) &&
4125 length > MTK_PP_MAX_BUF_SIZE) {
4126 netdev_err(dev, "Invalid MTU for XDP mode\n");
4127 return -EINVAL;
4128 }
4129
4130 mtk_set_mcr_max_rx(mac, length);
4131 WRITE_ONCE(dev->mtu, new_mtu);
4132
4133 return 0;
4134 }
4135
mtk_do_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)4136 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4137 {
4138 struct mtk_mac *mac = netdev_priv(dev);
4139
4140 switch (cmd) {
4141 case SIOCGMIIPHY:
4142 case SIOCGMIIREG:
4143 case SIOCSMIIREG:
4144 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
4145 default:
4146 break;
4147 }
4148
4149 return -EOPNOTSUPP;
4150 }
4151
mtk_prepare_for_reset(struct mtk_eth * eth)4152 static void mtk_prepare_for_reset(struct mtk_eth *eth)
4153 {
4154 u32 val;
4155 int i;
4156
4157 /* set FE PPE ports link down */
4158 for (i = MTK_GMAC1_ID;
4159 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
4160 i += 2) {
4161 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
4162 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
4163 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
4164 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
4165 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
4166 mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
4167 }
4168
4169 /* adjust PPE configurations to prepare for reset */
4170 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
4171 mtk_ppe_prepare_reset(eth->ppe[i]);
4172
4173 /* disable NETSYS interrupts */
4174 mtk_w32(eth, 0, MTK_FE_INT_ENABLE);
4175
4176 /* force link down GMAC */
4177 for (i = 0; i < 2; i++) {
4178 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK;
4179 mtk_w32(eth, val, MTK_MAC_MCR(i));
4180 }
4181 }
4182
mtk_pending_work(struct work_struct * work)4183 static void mtk_pending_work(struct work_struct *work)
4184 {
4185 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
4186 unsigned long restart = 0;
4187 u32 val;
4188 int i;
4189
4190 rtnl_lock();
4191 set_bit(MTK_RESETTING, ð->state);
4192
4193 mtk_prepare_for_reset(eth);
4194 mtk_wed_fe_reset();
4195 /* Run again reset preliminary configuration in order to avoid any
4196 * possible race during FE reset since it can run releasing RTNL lock.
4197 */
4198 mtk_prepare_for_reset(eth);
4199
4200 /* stop all devices to make sure that dma is properly shut down */
4201 for (i = 0; i < MTK_MAX_DEVS; i++) {
4202 if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
4203 continue;
4204
4205 mtk_stop(eth->netdev[i]);
4206 __set_bit(i, &restart);
4207 }
4208
4209 usleep_range(15000, 16000);
4210
4211 if (eth->dev->pins)
4212 pinctrl_select_state(eth->dev->pins->p,
4213 eth->dev->pins->default_state);
4214 mtk_hw_init(eth, true);
4215
4216 /* restart DMA and enable IRQs */
4217 for (i = 0; i < MTK_MAX_DEVS; i++) {
4218 if (!eth->netdev[i] || !test_bit(i, &restart))
4219 continue;
4220
4221 if (mtk_open(eth->netdev[i])) {
4222 netif_alert(eth, ifup, eth->netdev[i],
4223 "Driver up/down cycle failed\n");
4224 dev_close(eth->netdev[i]);
4225 }
4226 }
4227
4228 /* set FE PPE ports link up */
4229 for (i = MTK_GMAC1_ID;
4230 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
4231 i += 2) {
4232 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
4233 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
4234 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
4235 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
4236 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
4237
4238 mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
4239 }
4240
4241 clear_bit(MTK_RESETTING, ð->state);
4242
4243 mtk_wed_fe_reset_complete();
4244
4245 rtnl_unlock();
4246 }
4247
mtk_free_dev(struct mtk_eth * eth)4248 static int mtk_free_dev(struct mtk_eth *eth)
4249 {
4250 int i;
4251
4252 for (i = 0; i < MTK_MAX_DEVS; i++) {
4253 if (!eth->netdev[i])
4254 continue;
4255 free_netdev(eth->netdev[i]);
4256 }
4257
4258 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
4259 if (!eth->dsa_meta[i])
4260 break;
4261 metadata_dst_free(eth->dsa_meta[i]);
4262 }
4263
4264 return 0;
4265 }
4266
mtk_unreg_dev(struct mtk_eth * eth)4267 static int mtk_unreg_dev(struct mtk_eth *eth)
4268 {
4269 int i;
4270
4271 for (i = 0; i < MTK_MAX_DEVS; i++) {
4272 struct mtk_mac *mac;
4273 if (!eth->netdev[i])
4274 continue;
4275 mac = netdev_priv(eth->netdev[i]);
4276 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
4277 unregister_netdevice_notifier(&mac->device_notifier);
4278 unregister_netdev(eth->netdev[i]);
4279 }
4280
4281 return 0;
4282 }
4283
mtk_sgmii_destroy(struct mtk_eth * eth)4284 static void mtk_sgmii_destroy(struct mtk_eth *eth)
4285 {
4286 int i;
4287
4288 for (i = 0; i < MTK_MAX_DEVS; i++)
4289 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]);
4290 }
4291
mtk_cleanup(struct mtk_eth * eth)4292 static int mtk_cleanup(struct mtk_eth *eth)
4293 {
4294 mtk_sgmii_destroy(eth);
4295 mtk_unreg_dev(eth);
4296 mtk_free_dev(eth);
4297 cancel_work_sync(ð->pending_work);
4298 cancel_delayed_work_sync(ð->reset.monitor_work);
4299
4300 return 0;
4301 }
4302
mtk_get_link_ksettings(struct net_device * ndev,struct ethtool_link_ksettings * cmd)4303 static int mtk_get_link_ksettings(struct net_device *ndev,
4304 struct ethtool_link_ksettings *cmd)
4305 {
4306 struct mtk_mac *mac = netdev_priv(ndev);
4307
4308 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4309 return -EBUSY;
4310
4311 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
4312 }
4313
mtk_set_link_ksettings(struct net_device * ndev,const struct ethtool_link_ksettings * cmd)4314 static int mtk_set_link_ksettings(struct net_device *ndev,
4315 const struct ethtool_link_ksettings *cmd)
4316 {
4317 struct mtk_mac *mac = netdev_priv(ndev);
4318
4319 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4320 return -EBUSY;
4321
4322 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
4323 }
4324
mtk_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)4325 static void mtk_get_drvinfo(struct net_device *dev,
4326 struct ethtool_drvinfo *info)
4327 {
4328 struct mtk_mac *mac = netdev_priv(dev);
4329
4330 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
4331 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
4332 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
4333 }
4334
mtk_get_msglevel(struct net_device * dev)4335 static u32 mtk_get_msglevel(struct net_device *dev)
4336 {
4337 struct mtk_mac *mac = netdev_priv(dev);
4338
4339 return mac->hw->msg_enable;
4340 }
4341
mtk_set_msglevel(struct net_device * dev,u32 value)4342 static void mtk_set_msglevel(struct net_device *dev, u32 value)
4343 {
4344 struct mtk_mac *mac = netdev_priv(dev);
4345
4346 mac->hw->msg_enable = value;
4347 }
4348
mtk_nway_reset(struct net_device * dev)4349 static int mtk_nway_reset(struct net_device *dev)
4350 {
4351 struct mtk_mac *mac = netdev_priv(dev);
4352
4353 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4354 return -EBUSY;
4355
4356 if (!mac->phylink)
4357 return -ENOTSUPP;
4358
4359 return phylink_ethtool_nway_reset(mac->phylink);
4360 }
4361
mtk_get_strings(struct net_device * dev,u32 stringset,u8 * data)4362 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4363 {
4364 int i;
4365
4366 switch (stringset) {
4367 case ETH_SS_STATS: {
4368 struct mtk_mac *mac = netdev_priv(dev);
4369
4370 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
4371 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
4372 data += ETH_GSTRING_LEN;
4373 }
4374 if (mtk_page_pool_enabled(mac->hw))
4375 page_pool_ethtool_stats_get_strings(data);
4376 break;
4377 }
4378 default:
4379 break;
4380 }
4381 }
4382
mtk_get_sset_count(struct net_device * dev,int sset)4383 static int mtk_get_sset_count(struct net_device *dev, int sset)
4384 {
4385 switch (sset) {
4386 case ETH_SS_STATS: {
4387 int count = ARRAY_SIZE(mtk_ethtool_stats);
4388 struct mtk_mac *mac = netdev_priv(dev);
4389
4390 if (mtk_page_pool_enabled(mac->hw))
4391 count += page_pool_ethtool_stats_get_count();
4392 return count;
4393 }
4394 default:
4395 return -EOPNOTSUPP;
4396 }
4397 }
4398
mtk_ethtool_pp_stats(struct mtk_eth * eth,u64 * data)4399 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data)
4400 {
4401 struct page_pool_stats stats = {};
4402 int i;
4403
4404 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) {
4405 struct mtk_rx_ring *ring = ð->rx_ring[i];
4406
4407 if (!ring->page_pool)
4408 continue;
4409
4410 page_pool_get_stats(ring->page_pool, &stats);
4411 }
4412 page_pool_ethtool_stats_get(data, &stats);
4413 }
4414
mtk_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)4415 static void mtk_get_ethtool_stats(struct net_device *dev,
4416 struct ethtool_stats *stats, u64 *data)
4417 {
4418 struct mtk_mac *mac = netdev_priv(dev);
4419 struct mtk_hw_stats *hwstats = mac->hw_stats;
4420 u64 *data_src, *data_dst;
4421 unsigned int start;
4422 int i;
4423
4424 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4425 return;
4426
4427 if (netif_running(dev) && netif_device_present(dev)) {
4428 if (spin_trylock_bh(&hwstats->stats_lock)) {
4429 mtk_stats_update_mac(mac);
4430 spin_unlock_bh(&hwstats->stats_lock);
4431 }
4432 }
4433
4434 data_src = (u64 *)hwstats;
4435
4436 do {
4437 data_dst = data;
4438 start = u64_stats_fetch_begin(&hwstats->syncp);
4439
4440 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
4441 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
4442 if (mtk_page_pool_enabled(mac->hw))
4443 mtk_ethtool_pp_stats(mac->hw, data_dst);
4444 } while (u64_stats_fetch_retry(&hwstats->syncp, start));
4445 }
4446
mtk_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)4447 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
4448 u32 *rule_locs)
4449 {
4450 int ret = -EOPNOTSUPP;
4451
4452 switch (cmd->cmd) {
4453 case ETHTOOL_GRXRINGS:
4454 if (dev->hw_features & NETIF_F_LRO) {
4455 cmd->data = MTK_MAX_RX_RING_NUM;
4456 ret = 0;
4457 }
4458 break;
4459 case ETHTOOL_GRXCLSRLCNT:
4460 if (dev->hw_features & NETIF_F_LRO) {
4461 struct mtk_mac *mac = netdev_priv(dev);
4462
4463 cmd->rule_cnt = mac->hwlro_ip_cnt;
4464 ret = 0;
4465 }
4466 break;
4467 case ETHTOOL_GRXCLSRULE:
4468 if (dev->hw_features & NETIF_F_LRO)
4469 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
4470 break;
4471 case ETHTOOL_GRXCLSRLALL:
4472 if (dev->hw_features & NETIF_F_LRO)
4473 ret = mtk_hwlro_get_fdir_all(dev, cmd,
4474 rule_locs);
4475 break;
4476 default:
4477 break;
4478 }
4479
4480 return ret;
4481 }
4482
mtk_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)4483 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
4484 {
4485 int ret = -EOPNOTSUPP;
4486
4487 switch (cmd->cmd) {
4488 case ETHTOOL_SRXCLSRLINS:
4489 if (dev->hw_features & NETIF_F_LRO)
4490 ret = mtk_hwlro_add_ipaddr(dev, cmd);
4491 break;
4492 case ETHTOOL_SRXCLSRLDEL:
4493 if (dev->hw_features & NETIF_F_LRO)
4494 ret = mtk_hwlro_del_ipaddr(dev, cmd);
4495 break;
4496 default:
4497 break;
4498 }
4499
4500 return ret;
4501 }
4502
mtk_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)4503 static void mtk_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause)
4504 {
4505 struct mtk_mac *mac = netdev_priv(dev);
4506
4507 phylink_ethtool_get_pauseparam(mac->phylink, pause);
4508 }
4509
mtk_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)4510 static int mtk_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause)
4511 {
4512 struct mtk_mac *mac = netdev_priv(dev);
4513
4514 return phylink_ethtool_set_pauseparam(mac->phylink, pause);
4515 }
4516
mtk_select_queue(struct net_device * dev,struct sk_buff * skb,struct net_device * sb_dev)4517 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb,
4518 struct net_device *sb_dev)
4519 {
4520 struct mtk_mac *mac = netdev_priv(dev);
4521 unsigned int queue = 0;
4522
4523 if (netdev_uses_dsa(dev))
4524 queue = skb_get_queue_mapping(skb) + 3;
4525 else
4526 queue = mac->id;
4527
4528 if (queue >= dev->num_tx_queues)
4529 queue = 0;
4530
4531 return queue;
4532 }
4533
4534 static const struct ethtool_ops mtk_ethtool_ops = {
4535 .get_link_ksettings = mtk_get_link_ksettings,
4536 .set_link_ksettings = mtk_set_link_ksettings,
4537 .get_drvinfo = mtk_get_drvinfo,
4538 .get_msglevel = mtk_get_msglevel,
4539 .set_msglevel = mtk_set_msglevel,
4540 .nway_reset = mtk_nway_reset,
4541 .get_link = ethtool_op_get_link,
4542 .get_strings = mtk_get_strings,
4543 .get_sset_count = mtk_get_sset_count,
4544 .get_ethtool_stats = mtk_get_ethtool_stats,
4545 .get_pauseparam = mtk_get_pauseparam,
4546 .set_pauseparam = mtk_set_pauseparam,
4547 .get_rxnfc = mtk_get_rxnfc,
4548 .set_rxnfc = mtk_set_rxnfc,
4549 };
4550
4551 static const struct net_device_ops mtk_netdev_ops = {
4552 .ndo_uninit = mtk_uninit,
4553 .ndo_open = mtk_open,
4554 .ndo_stop = mtk_stop,
4555 .ndo_start_xmit = mtk_start_xmit,
4556 .ndo_set_mac_address = mtk_set_mac_address,
4557 .ndo_validate_addr = eth_validate_addr,
4558 .ndo_eth_ioctl = mtk_do_ioctl,
4559 .ndo_change_mtu = mtk_change_mtu,
4560 .ndo_tx_timeout = mtk_tx_timeout,
4561 .ndo_get_stats64 = mtk_get_stats64,
4562 .ndo_fix_features = mtk_fix_features,
4563 .ndo_set_features = mtk_set_features,
4564 #ifdef CONFIG_NET_POLL_CONTROLLER
4565 .ndo_poll_controller = mtk_poll_controller,
4566 #endif
4567 .ndo_setup_tc = mtk_eth_setup_tc,
4568 .ndo_bpf = mtk_xdp,
4569 .ndo_xdp_xmit = mtk_xdp_xmit,
4570 .ndo_select_queue = mtk_select_queue,
4571 };
4572
mtk_add_mac(struct mtk_eth * eth,struct device_node * np)4573 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
4574 {
4575 const __be32 *_id = of_get_property(np, "reg", NULL);
4576 phy_interface_t phy_mode;
4577 struct phylink *phylink;
4578 struct mtk_mac *mac;
4579 int id, err;
4580 int txqs = 1;
4581 u32 val;
4582
4583 if (!_id) {
4584 dev_err(eth->dev, "missing mac id\n");
4585 return -EINVAL;
4586 }
4587
4588 id = be32_to_cpup(_id);
4589 if (id >= MTK_MAX_DEVS) {
4590 dev_err(eth->dev, "%d is not a valid mac id\n", id);
4591 return -EINVAL;
4592 }
4593
4594 if (eth->netdev[id]) {
4595 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
4596 return -EINVAL;
4597 }
4598
4599 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
4600 txqs = MTK_QDMA_NUM_QUEUES;
4601
4602 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1);
4603 if (!eth->netdev[id]) {
4604 dev_err(eth->dev, "alloc_etherdev failed\n");
4605 return -ENOMEM;
4606 }
4607 mac = netdev_priv(eth->netdev[id]);
4608 eth->mac[id] = mac;
4609 mac->id = id;
4610 mac->hw = eth;
4611 mac->of_node = np;
4612
4613 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
4614 if (err == -EPROBE_DEFER)
4615 return err;
4616
4617 if (err) {
4618 /* If the mac address is invalid, use random mac address */
4619 eth_hw_addr_random(eth->netdev[id]);
4620 dev_err(eth->dev, "generated random MAC address %pM\n",
4621 eth->netdev[id]->dev_addr);
4622 }
4623
4624 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
4625 mac->hwlro_ip_cnt = 0;
4626
4627 mac->hw_stats = devm_kzalloc(eth->dev,
4628 sizeof(*mac->hw_stats),
4629 GFP_KERNEL);
4630 if (!mac->hw_stats) {
4631 dev_err(eth->dev, "failed to allocate counter memory\n");
4632 err = -ENOMEM;
4633 goto free_netdev;
4634 }
4635 spin_lock_init(&mac->hw_stats->stats_lock);
4636 u64_stats_init(&mac->hw_stats->syncp);
4637
4638 if (mtk_is_netsys_v3_or_greater(eth))
4639 mac->hw_stats->reg_offset = id * 0x80;
4640 else
4641 mac->hw_stats->reg_offset = id * 0x40;
4642
4643 /* phylink create */
4644 err = of_get_phy_mode(np, &phy_mode);
4645 if (err) {
4646 dev_err(eth->dev, "incorrect phy-mode\n");
4647 goto free_netdev;
4648 }
4649
4650 /* mac config is not set */
4651 mac->interface = PHY_INTERFACE_MODE_NA;
4652 mac->speed = SPEED_UNKNOWN;
4653
4654 mac->phylink_config.dev = ð->netdev[id]->dev;
4655 mac->phylink_config.type = PHYLINK_NETDEV;
4656 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
4657 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
4658
4659 /* MT7623 gmac0 is now missing its speed-specific PLL configuration
4660 * in its .mac_config method (since state->speed is not valid there.
4661 * Disable support for MII, GMII and RGMII.
4662 */
4663 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) {
4664 __set_bit(PHY_INTERFACE_MODE_MII,
4665 mac->phylink_config.supported_interfaces);
4666 __set_bit(PHY_INTERFACE_MODE_GMII,
4667 mac->phylink_config.supported_interfaces);
4668
4669 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
4670 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
4671 }
4672
4673 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
4674 __set_bit(PHY_INTERFACE_MODE_TRGMII,
4675 mac->phylink_config.supported_interfaces);
4676
4677 /* TRGMII is not permitted on MT7621 if using DDR2 */
4678 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
4679 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) {
4680 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
4681 if (val & SYSCFG_DRAM_TYPE_DDR2)
4682 __clear_bit(PHY_INTERFACE_MODE_TRGMII,
4683 mac->phylink_config.supported_interfaces);
4684 }
4685
4686 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
4687 __set_bit(PHY_INTERFACE_MODE_SGMII,
4688 mac->phylink_config.supported_interfaces);
4689 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
4690 mac->phylink_config.supported_interfaces);
4691 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
4692 mac->phylink_config.supported_interfaces);
4693 }
4694
4695 if (mtk_is_netsys_v3_or_greater(mac->hw) &&
4696 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW) &&
4697 id == MTK_GMAC1_ID) {
4698 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
4699 MAC_SYM_PAUSE |
4700 MAC_10000FD;
4701 phy_interface_zero(mac->phylink_config.supported_interfaces);
4702 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
4703 mac->phylink_config.supported_interfaces);
4704 }
4705
4706 phylink = phylink_create(&mac->phylink_config,
4707 of_fwnode_handle(mac->of_node),
4708 phy_mode, &mtk_phylink_ops);
4709 if (IS_ERR(phylink)) {
4710 err = PTR_ERR(phylink);
4711 goto free_netdev;
4712 }
4713
4714 mac->phylink = phylink;
4715
4716 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
4717 eth->netdev[id]->watchdog_timeo = 5 * HZ;
4718 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
4719 eth->netdev[id]->base_addr = (unsigned long)eth->base;
4720
4721 eth->netdev[id]->hw_features = eth->soc->hw_features;
4722 if (eth->hwlro)
4723 eth->netdev[id]->hw_features |= NETIF_F_LRO;
4724
4725 eth->netdev[id]->vlan_features = eth->soc->hw_features &
4726 ~NETIF_F_HW_VLAN_CTAG_TX;
4727 eth->netdev[id]->features |= eth->soc->hw_features;
4728 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
4729
4730 eth->netdev[id]->irq = eth->irq[0];
4731 eth->netdev[id]->dev.of_node = np;
4732
4733 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
4734 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
4735 else
4736 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
4737
4738 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
4739 mac->device_notifier.notifier_call = mtk_device_event;
4740 register_netdevice_notifier(&mac->device_notifier);
4741 }
4742
4743 if (mtk_page_pool_enabled(eth))
4744 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC |
4745 NETDEV_XDP_ACT_REDIRECT |
4746 NETDEV_XDP_ACT_NDO_XMIT |
4747 NETDEV_XDP_ACT_NDO_XMIT_SG;
4748
4749 return 0;
4750
4751 free_netdev:
4752 free_netdev(eth->netdev[id]);
4753 return err;
4754 }
4755
mtk_eth_set_dma_device(struct mtk_eth * eth,struct device * dma_dev)4756 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
4757 {
4758 struct net_device *dev, *tmp;
4759 LIST_HEAD(dev_list);
4760 int i;
4761
4762 rtnl_lock();
4763
4764 for (i = 0; i < MTK_MAX_DEVS; i++) {
4765 dev = eth->netdev[i];
4766
4767 if (!dev || !(dev->flags & IFF_UP))
4768 continue;
4769
4770 list_add_tail(&dev->close_list, &dev_list);
4771 }
4772
4773 dev_close_many(&dev_list, false);
4774
4775 eth->dma_dev = dma_dev;
4776
4777 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) {
4778 list_del_init(&dev->close_list);
4779 dev_open(dev, NULL);
4780 }
4781
4782 rtnl_unlock();
4783 }
4784
mtk_sgmii_init(struct mtk_eth * eth)4785 static int mtk_sgmii_init(struct mtk_eth *eth)
4786 {
4787 struct device_node *np;
4788 struct regmap *regmap;
4789 u32 flags;
4790 int i;
4791
4792 for (i = 0; i < MTK_MAX_DEVS; i++) {
4793 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i);
4794 if (!np)
4795 break;
4796
4797 regmap = syscon_node_to_regmap(np);
4798 flags = 0;
4799 if (of_property_read_bool(np, "mediatek,pnswap"))
4800 flags |= MTK_SGMII_FLAG_PN_SWAP;
4801
4802 of_node_put(np);
4803
4804 if (IS_ERR(regmap))
4805 return PTR_ERR(regmap);
4806
4807 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap,
4808 eth->soc->ana_rgc3,
4809 flags);
4810 }
4811
4812 return 0;
4813 }
4814
mtk_probe(struct platform_device * pdev)4815 static int mtk_probe(struct platform_device *pdev)
4816 {
4817 struct resource *res = NULL, *res_sram;
4818 struct device_node *mac_np;
4819 struct mtk_eth *eth;
4820 int err, i;
4821
4822 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
4823 if (!eth)
4824 return -ENOMEM;
4825
4826 eth->soc = of_device_get_match_data(&pdev->dev);
4827
4828 eth->dev = &pdev->dev;
4829 eth->dma_dev = &pdev->dev;
4830 eth->base = devm_platform_ioremap_resource(pdev, 0);
4831 if (IS_ERR(eth->base))
4832 return PTR_ERR(eth->base);
4833
4834 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
4835 eth->ip_align = NET_IP_ALIGN;
4836
4837 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
4838 /* SRAM is actual memory and supports transparent access just like DRAM.
4839 * Hence we don't require __iomem being set and don't need to use accessor
4840 * functions to read from or write to SRAM.
4841 */
4842 if (mtk_is_netsys_v3_or_greater(eth)) {
4843 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1);
4844 if (IS_ERR(eth->sram_base))
4845 return PTR_ERR(eth->sram_base);
4846 } else {
4847 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET;
4848 }
4849 }
4850
4851 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
4852 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
4853 if (!err)
4854 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
4855
4856 if (err) {
4857 dev_err(&pdev->dev, "Wrong DMA config\n");
4858 return -EINVAL;
4859 }
4860 }
4861
4862 spin_lock_init(ð->page_lock);
4863 spin_lock_init(ð->tx_irq_lock);
4864 spin_lock_init(ð->rx_irq_lock);
4865 spin_lock_init(ð->dim_lock);
4866
4867 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4868 INIT_WORK(ð->rx_dim.work, mtk_dim_rx);
4869 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work);
4870
4871 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4872 INIT_WORK(ð->tx_dim.work, mtk_dim_tx);
4873
4874 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4875 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4876 "mediatek,ethsys");
4877 if (IS_ERR(eth->ethsys)) {
4878 dev_err(&pdev->dev, "no ethsys regmap found\n");
4879 return PTR_ERR(eth->ethsys);
4880 }
4881 }
4882
4883 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
4884 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4885 "mediatek,infracfg");
4886 if (IS_ERR(eth->infra)) {
4887 dev_err(&pdev->dev, "no infracfg regmap found\n");
4888 return PTR_ERR(eth->infra);
4889 }
4890 }
4891
4892 if (of_dma_is_coherent(pdev->dev.of_node)) {
4893 struct regmap *cci;
4894
4895 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4896 "cci-control-port");
4897 /* enable CPU/bus coherency */
4898 if (!IS_ERR(cci))
4899 regmap_write(cci, 0, 3);
4900 }
4901
4902 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
4903 err = mtk_sgmii_init(eth);
4904
4905 if (err)
4906 return err;
4907 }
4908
4909 if (eth->soc->required_pctl) {
4910 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4911 "mediatek,pctl");
4912 if (IS_ERR(eth->pctl)) {
4913 dev_err(&pdev->dev, "no pctl regmap found\n");
4914 err = PTR_ERR(eth->pctl);
4915 goto err_destroy_sgmii;
4916 }
4917 }
4918
4919 if (mtk_is_netsys_v2_or_greater(eth)) {
4920 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4921 if (!res) {
4922 err = -EINVAL;
4923 goto err_destroy_sgmii;
4924 }
4925 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
4926 if (mtk_is_netsys_v3_or_greater(eth)) {
4927 res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
4928 if (!res_sram) {
4929 err = -EINVAL;
4930 goto err_destroy_sgmii;
4931 }
4932 eth->phy_scratch_ring = res_sram->start;
4933 } else {
4934 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET;
4935 }
4936 }
4937 }
4938
4939 if (eth->soc->offload_version) {
4940 for (i = 0;; i++) {
4941 struct device_node *np;
4942 phys_addr_t wdma_phy;
4943 u32 wdma_base;
4944
4945 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base))
4946 break;
4947
4948 np = of_parse_phandle(pdev->dev.of_node,
4949 "mediatek,wed", i);
4950 if (!np)
4951 break;
4952
4953 wdma_base = eth->soc->reg_map->wdma_base[i];
4954 wdma_phy = res ? res->start + wdma_base : 0;
4955 mtk_wed_add_hw(np, eth, eth->base + wdma_base,
4956 wdma_phy, i);
4957 }
4958 }
4959
4960 for (i = 0; i < 3; i++) {
4961 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
4962 eth->irq[i] = eth->irq[0];
4963 else
4964 eth->irq[i] = platform_get_irq(pdev, i);
4965 if (eth->irq[i] < 0) {
4966 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
4967 err = -ENXIO;
4968 goto err_wed_exit;
4969 }
4970 }
4971 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
4972 eth->clks[i] = devm_clk_get(eth->dev,
4973 mtk_clks_source_name[i]);
4974 if (IS_ERR(eth->clks[i])) {
4975 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) {
4976 err = -EPROBE_DEFER;
4977 goto err_wed_exit;
4978 }
4979 if (eth->soc->required_clks & BIT(i)) {
4980 dev_err(&pdev->dev, "clock %s not found\n",
4981 mtk_clks_source_name[i]);
4982 err = -EINVAL;
4983 goto err_wed_exit;
4984 }
4985 eth->clks[i] = NULL;
4986 }
4987 }
4988
4989 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
4990 INIT_WORK(ð->pending_work, mtk_pending_work);
4991
4992 err = mtk_hw_init(eth, false);
4993 if (err)
4994 goto err_wed_exit;
4995
4996 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
4997
4998 for_each_child_of_node(pdev->dev.of_node, mac_np) {
4999 if (!of_device_is_compatible(mac_np,
5000 "mediatek,eth-mac"))
5001 continue;
5002
5003 if (!of_device_is_available(mac_np))
5004 continue;
5005
5006 err = mtk_add_mac(eth, mac_np);
5007 if (err) {
5008 of_node_put(mac_np);
5009 goto err_deinit_hw;
5010 }
5011 }
5012
5013 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
5014 err = devm_request_irq(eth->dev, eth->irq[0],
5015 mtk_handle_irq, 0,
5016 dev_name(eth->dev), eth);
5017 } else {
5018 err = devm_request_irq(eth->dev, eth->irq[1],
5019 mtk_handle_irq_tx, 0,
5020 dev_name(eth->dev), eth);
5021 if (err)
5022 goto err_free_dev;
5023
5024 err = devm_request_irq(eth->dev, eth->irq[2],
5025 mtk_handle_irq_rx, 0,
5026 dev_name(eth->dev), eth);
5027 }
5028 if (err)
5029 goto err_free_dev;
5030
5031 /* No MT7628/88 support yet */
5032 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
5033 err = mtk_mdio_init(eth);
5034 if (err)
5035 goto err_free_dev;
5036 }
5037
5038 if (eth->soc->offload_version) {
5039 u8 ppe_num = eth->soc->ppe_num;
5040
5041 ppe_num = min_t(u8, ARRAY_SIZE(eth->ppe), ppe_num);
5042 for (i = 0; i < ppe_num; i++) {
5043 u32 ppe_addr = eth->soc->reg_map->ppe_base;
5044
5045 ppe_addr += (i == 2 ? 0xc00 : i * 0x400);
5046 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i);
5047
5048 if (!eth->ppe[i]) {
5049 err = -ENOMEM;
5050 goto err_deinit_ppe;
5051 }
5052 err = mtk_eth_offload_init(eth, i);
5053
5054 if (err)
5055 goto err_deinit_ppe;
5056 }
5057 }
5058
5059 for (i = 0; i < MTK_MAX_DEVS; i++) {
5060 if (!eth->netdev[i])
5061 continue;
5062
5063 err = register_netdev(eth->netdev[i]);
5064 if (err) {
5065 dev_err(eth->dev, "error bringing up device\n");
5066 goto err_deinit_ppe;
5067 } else
5068 netif_info(eth, probe, eth->netdev[i],
5069 "mediatek frame engine at 0x%08lx, irq %d\n",
5070 eth->netdev[i]->base_addr, eth->irq[0]);
5071 }
5072
5073 /* we run 2 devices on the same DMA ring so we need a dummy device
5074 * for NAPI to work
5075 */
5076 eth->dummy_dev = alloc_netdev_dummy(0);
5077 if (!eth->dummy_dev) {
5078 err = -ENOMEM;
5079 dev_err(eth->dev, "failed to allocated dummy device\n");
5080 goto err_unreg_netdev;
5081 }
5082 netif_napi_add(eth->dummy_dev, ð->tx_napi, mtk_napi_tx);
5083 netif_napi_add(eth->dummy_dev, ð->rx_napi, mtk_napi_rx);
5084
5085 platform_set_drvdata(pdev, eth);
5086 schedule_delayed_work(ð->reset.monitor_work,
5087 MTK_DMA_MONITOR_TIMEOUT);
5088
5089 return 0;
5090
5091 err_unreg_netdev:
5092 mtk_unreg_dev(eth);
5093 err_deinit_ppe:
5094 mtk_ppe_deinit(eth);
5095 mtk_mdio_cleanup(eth);
5096 err_free_dev:
5097 mtk_free_dev(eth);
5098 err_deinit_hw:
5099 mtk_hw_deinit(eth);
5100 err_wed_exit:
5101 mtk_wed_exit();
5102 err_destroy_sgmii:
5103 mtk_sgmii_destroy(eth);
5104
5105 return err;
5106 }
5107
mtk_remove(struct platform_device * pdev)5108 static void mtk_remove(struct platform_device *pdev)
5109 {
5110 struct mtk_eth *eth = platform_get_drvdata(pdev);
5111 struct mtk_mac *mac;
5112 int i;
5113
5114 /* stop all devices to make sure that dma is properly shut down */
5115 for (i = 0; i < MTK_MAX_DEVS; i++) {
5116 if (!eth->netdev[i])
5117 continue;
5118 mtk_stop(eth->netdev[i]);
5119 mac = netdev_priv(eth->netdev[i]);
5120 phylink_disconnect_phy(mac->phylink);
5121 }
5122
5123 mtk_wed_exit();
5124 mtk_hw_deinit(eth);
5125
5126 netif_napi_del(ð->tx_napi);
5127 netif_napi_del(ð->rx_napi);
5128 mtk_cleanup(eth);
5129 free_netdev(eth->dummy_dev);
5130 mtk_mdio_cleanup(eth);
5131 }
5132
5133 static const struct mtk_soc_data mt2701_data = {
5134 .reg_map = &mtk_reg_map,
5135 .caps = MT7623_CAPS | MTK_HWLRO,
5136 .hw_features = MTK_HW_FEATURES,
5137 .required_clks = MT7623_CLKS_BITMAP,
5138 .required_pctl = true,
5139 .version = 1,
5140 .tx = {
5141 .desc_size = sizeof(struct mtk_tx_dma),
5142 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5143 .dma_len_offset = 16,
5144 .dma_size = MTK_DMA_SIZE(2K),
5145 .fq_dma_size = MTK_DMA_SIZE(2K),
5146 },
5147 .rx = {
5148 .desc_size = sizeof(struct mtk_rx_dma),
5149 .irq_done_mask = MTK_RX_DONE_INT,
5150 .dma_l4_valid = RX_DMA_L4_VALID,
5151 .dma_size = MTK_DMA_SIZE(2K),
5152 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5153 .dma_len_offset = 16,
5154 },
5155 };
5156
5157 static const struct mtk_soc_data mt7621_data = {
5158 .reg_map = &mtk_reg_map,
5159 .caps = MT7621_CAPS,
5160 .hw_features = MTK_HW_FEATURES,
5161 .required_clks = MT7621_CLKS_BITMAP,
5162 .required_pctl = false,
5163 .version = 1,
5164 .offload_version = 1,
5165 .ppe_num = 1,
5166 .hash_offset = 2,
5167 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
5168 .tx = {
5169 .desc_size = sizeof(struct mtk_tx_dma),
5170 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5171 .dma_len_offset = 16,
5172 .dma_size = MTK_DMA_SIZE(2K),
5173 .fq_dma_size = MTK_DMA_SIZE(2K),
5174 },
5175 .rx = {
5176 .desc_size = sizeof(struct mtk_rx_dma),
5177 .irq_done_mask = MTK_RX_DONE_INT,
5178 .dma_l4_valid = RX_DMA_L4_VALID,
5179 .dma_size = MTK_DMA_SIZE(2K),
5180 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5181 .dma_len_offset = 16,
5182 },
5183 };
5184
5185 static const struct mtk_soc_data mt7622_data = {
5186 .reg_map = &mtk_reg_map,
5187 .ana_rgc3 = 0x2028,
5188 .caps = MT7622_CAPS | MTK_HWLRO,
5189 .hw_features = MTK_HW_FEATURES,
5190 .required_clks = MT7622_CLKS_BITMAP,
5191 .required_pctl = false,
5192 .version = 1,
5193 .offload_version = 2,
5194 .ppe_num = 1,
5195 .hash_offset = 2,
5196 .has_accounting = true,
5197 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
5198 .tx = {
5199 .desc_size = sizeof(struct mtk_tx_dma),
5200 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5201 .dma_len_offset = 16,
5202 .dma_size = MTK_DMA_SIZE(2K),
5203 .fq_dma_size = MTK_DMA_SIZE(2K),
5204 },
5205 .rx = {
5206 .desc_size = sizeof(struct mtk_rx_dma),
5207 .irq_done_mask = MTK_RX_DONE_INT,
5208 .dma_l4_valid = RX_DMA_L4_VALID,
5209 .dma_size = MTK_DMA_SIZE(2K),
5210 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5211 .dma_len_offset = 16,
5212 },
5213 };
5214
5215 static const struct mtk_soc_data mt7623_data = {
5216 .reg_map = &mtk_reg_map,
5217 .caps = MT7623_CAPS | MTK_HWLRO,
5218 .hw_features = MTK_HW_FEATURES,
5219 .required_clks = MT7623_CLKS_BITMAP,
5220 .required_pctl = true,
5221 .version = 1,
5222 .offload_version = 1,
5223 .ppe_num = 1,
5224 .hash_offset = 2,
5225 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
5226 .disable_pll_modes = true,
5227 .tx = {
5228 .desc_size = sizeof(struct mtk_tx_dma),
5229 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5230 .dma_len_offset = 16,
5231 .dma_size = MTK_DMA_SIZE(2K),
5232 .fq_dma_size = MTK_DMA_SIZE(2K),
5233 },
5234 .rx = {
5235 .desc_size = sizeof(struct mtk_rx_dma),
5236 .irq_done_mask = MTK_RX_DONE_INT,
5237 .dma_l4_valid = RX_DMA_L4_VALID,
5238 .dma_size = MTK_DMA_SIZE(2K),
5239 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5240 .dma_len_offset = 16,
5241 },
5242 };
5243
5244 static const struct mtk_soc_data mt7629_data = {
5245 .reg_map = &mtk_reg_map,
5246 .ana_rgc3 = 0x128,
5247 .caps = MT7629_CAPS | MTK_HWLRO,
5248 .hw_features = MTK_HW_FEATURES,
5249 .required_clks = MT7629_CLKS_BITMAP,
5250 .required_pctl = false,
5251 .has_accounting = true,
5252 .version = 1,
5253 .tx = {
5254 .desc_size = sizeof(struct mtk_tx_dma),
5255 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5256 .dma_len_offset = 16,
5257 .dma_size = MTK_DMA_SIZE(2K),
5258 .fq_dma_size = MTK_DMA_SIZE(2K),
5259 },
5260 .rx = {
5261 .desc_size = sizeof(struct mtk_rx_dma),
5262 .irq_done_mask = MTK_RX_DONE_INT,
5263 .dma_l4_valid = RX_DMA_L4_VALID,
5264 .dma_size = MTK_DMA_SIZE(2K),
5265 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5266 .dma_len_offset = 16,
5267 },
5268 };
5269
5270 static const struct mtk_soc_data mt7981_data = {
5271 .reg_map = &mt7986_reg_map,
5272 .ana_rgc3 = 0x128,
5273 .caps = MT7981_CAPS,
5274 .hw_features = MTK_HW_FEATURES,
5275 .required_clks = MT7981_CLKS_BITMAP,
5276 .required_pctl = false,
5277 .version = 2,
5278 .offload_version = 2,
5279 .ppe_num = 2,
5280 .hash_offset = 4,
5281 .has_accounting = true,
5282 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
5283 .tx = {
5284 .desc_size = sizeof(struct mtk_tx_dma_v2),
5285 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5286 .dma_len_offset = 8,
5287 .dma_size = MTK_DMA_SIZE(2K),
5288 .fq_dma_size = MTK_DMA_SIZE(2K),
5289 },
5290 .rx = {
5291 .desc_size = sizeof(struct mtk_rx_dma),
5292 .irq_done_mask = MTK_RX_DONE_INT,
5293 .dma_l4_valid = RX_DMA_L4_VALID_V2,
5294 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5295 .dma_len_offset = 16,
5296 .dma_size = MTK_DMA_SIZE(2K),
5297 },
5298 };
5299
5300 static const struct mtk_soc_data mt7986_data = {
5301 .reg_map = &mt7986_reg_map,
5302 .ana_rgc3 = 0x128,
5303 .caps = MT7986_CAPS,
5304 .hw_features = MTK_HW_FEATURES,
5305 .required_clks = MT7986_CLKS_BITMAP,
5306 .required_pctl = false,
5307 .version = 2,
5308 .offload_version = 2,
5309 .ppe_num = 2,
5310 .hash_offset = 4,
5311 .has_accounting = true,
5312 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
5313 .tx = {
5314 .desc_size = sizeof(struct mtk_tx_dma_v2),
5315 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5316 .dma_len_offset = 8,
5317 .dma_size = MTK_DMA_SIZE(2K),
5318 .fq_dma_size = MTK_DMA_SIZE(2K),
5319 },
5320 .rx = {
5321 .desc_size = sizeof(struct mtk_rx_dma),
5322 .irq_done_mask = MTK_RX_DONE_INT,
5323 .dma_l4_valid = RX_DMA_L4_VALID_V2,
5324 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5325 .dma_len_offset = 16,
5326 .dma_size = MTK_DMA_SIZE(2K),
5327 },
5328 };
5329
5330 static const struct mtk_soc_data mt7988_data = {
5331 .reg_map = &mt7988_reg_map,
5332 .ana_rgc3 = 0x128,
5333 .caps = MT7988_CAPS,
5334 .hw_features = MTK_HW_FEATURES,
5335 .required_clks = MT7988_CLKS_BITMAP,
5336 .required_pctl = false,
5337 .version = 3,
5338 .offload_version = 2,
5339 .ppe_num = 3,
5340 .hash_offset = 4,
5341 .has_accounting = true,
5342 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
5343 .tx = {
5344 .desc_size = sizeof(struct mtk_tx_dma_v2),
5345 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5346 .dma_len_offset = 8,
5347 .dma_size = MTK_DMA_SIZE(2K),
5348 .fq_dma_size = MTK_DMA_SIZE(4K),
5349 },
5350 .rx = {
5351 .desc_size = sizeof(struct mtk_rx_dma_v2),
5352 .irq_done_mask = MTK_RX_DONE_INT_V2,
5353 .dma_l4_valid = RX_DMA_L4_VALID_V2,
5354 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5355 .dma_len_offset = 8,
5356 .dma_size = MTK_DMA_SIZE(2K),
5357 },
5358 };
5359
5360 static const struct mtk_soc_data rt5350_data = {
5361 .reg_map = &mt7628_reg_map,
5362 .caps = MT7628_CAPS,
5363 .hw_features = MTK_HW_FEATURES_MT7628,
5364 .required_clks = MT7628_CLKS_BITMAP,
5365 .required_pctl = false,
5366 .version = 1,
5367 .tx = {
5368 .desc_size = sizeof(struct mtk_tx_dma),
5369 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5370 .dma_len_offset = 16,
5371 .dma_size = MTK_DMA_SIZE(2K),
5372 },
5373 .rx = {
5374 .desc_size = sizeof(struct mtk_rx_dma),
5375 .irq_done_mask = MTK_RX_DONE_INT,
5376 .dma_l4_valid = RX_DMA_L4_VALID_PDMA,
5377 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5378 .dma_len_offset = 16,
5379 .dma_size = MTK_DMA_SIZE(2K),
5380 },
5381 };
5382
5383 const struct of_device_id of_mtk_match[] = {
5384 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
5385 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
5386 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
5387 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
5388 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
5389 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
5390 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
5391 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
5392 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
5393 {},
5394 };
5395 MODULE_DEVICE_TABLE(of, of_mtk_match);
5396
5397 static struct platform_driver mtk_driver = {
5398 .probe = mtk_probe,
5399 .remove_new = mtk_remove,
5400 .driver = {
5401 .name = "mtk_soc_eth",
5402 .of_match_table = of_mtk_match,
5403 },
5404 };
5405
5406 module_platform_driver(mtk_driver);
5407
5408 MODULE_LICENSE("GPL");
5409 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
5410 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
5411