1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/in.h>
22 #include <linux/io.h>
23 #include <linux/ip.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/bitfield.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <linux/unaligned.h>
32 #include <net/ip6_checksum.h>
33 #include <net/netdev_queues.h>
34
35 #include "r8169.h"
36 #include "r8169_firmware.h"
37
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
58 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw"
59 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw"
60 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw"
61
62 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
63 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
64
65 #define R8169_REGS_SIZE 256
66 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
67 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
68 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
69 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
70 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
71 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1)
72 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS)
73
74 #define OCP_STD_PHY_BASE 0xa400
75
76 #define RTL_CFG_NO_GBIT 1
77
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
90
91 static const struct {
92 const char *name;
93 const char *fw_name;
94 } rtl_chip_infos[] = {
95 /* PCI devices. */
96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
101 /* PCI-E devices. */
102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" },
106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
107 [RTL_GIGA_MAC_VER_14] = {"RTL8401" },
108 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
109 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
110 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
111 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
112 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
113 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
114 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
115 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
116 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
117 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
118 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
119 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
120 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
121 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
122 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
123 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
124 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
125 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
126 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
127 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
128 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
129 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
130 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
131 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
132 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
133 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
134 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
135 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
136 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
137 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
138 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", },
139 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
140 /* reserve 62 for CFG_METHOD_4 in the vendor driver */
141 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
142 [RTL_GIGA_MAC_VER_64] = {"RTL8125D", FIRMWARE_8125D_1},
143 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2},
144 [RTL_GIGA_MAC_VER_66] = {"RTL8126A", FIRMWARE_8126A_3},
145 };
146
147 static const struct pci_device_id rtl8169_pci_tbl[] = {
148 { PCI_VDEVICE(REALTEK, 0x2502) },
149 { PCI_VDEVICE(REALTEK, 0x2600) },
150 { PCI_VDEVICE(REALTEK, 0x8129) },
151 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
152 { PCI_VDEVICE(REALTEK, 0x8161) },
153 { PCI_VDEVICE(REALTEK, 0x8162) },
154 { PCI_VDEVICE(REALTEK, 0x8167) },
155 { PCI_VDEVICE(REALTEK, 0x8168) },
156 { PCI_VDEVICE(NCUBE, 0x8168) },
157 { PCI_VDEVICE(REALTEK, 0x8169) },
158 { PCI_VENDOR_ID_DLINK, 0x4300,
159 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
160 { PCI_VDEVICE(DLINK, 0x4300) },
161 { PCI_VDEVICE(DLINK, 0x4302) },
162 { PCI_VDEVICE(AT, 0xc107) },
163 { PCI_VDEVICE(USR, 0x0116) },
164 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
165 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
166 { PCI_VDEVICE(REALTEK, 0x8125) },
167 { PCI_VDEVICE(REALTEK, 0x8126) },
168 { PCI_VDEVICE(REALTEK, 0x3000) },
169 {}
170 };
171
172 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
173
174 enum rtl_registers {
175 MAC0 = 0, /* Ethernet hardware address. */
176 MAC4 = 4,
177 MAR0 = 8, /* Multicast filter. */
178 CounterAddrLow = 0x10,
179 CounterAddrHigh = 0x14,
180 TxDescStartAddrLow = 0x20,
181 TxDescStartAddrHigh = 0x24,
182 TxHDescStartAddrLow = 0x28,
183 TxHDescStartAddrHigh = 0x2c,
184 FLASH = 0x30,
185 ERSR = 0x36,
186 ChipCmd = 0x37,
187 TxPoll = 0x38,
188 IntrMask = 0x3c,
189 IntrStatus = 0x3e,
190
191 TxConfig = 0x40,
192 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
193 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
194
195 RxConfig = 0x44,
196 #define RX128_INT_EN (1 << 15) /* 8111c and later */
197 #define RX_MULTI_EN (1 << 14) /* 8111c only */
198 #define RXCFG_FIFO_SHIFT 13
199 /* No threshold before first PCI xfer */
200 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
201 #define RX_EARLY_OFF (1 << 11)
202 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */
203 #define RXCFG_DMA_SHIFT 8
204 /* Unlimited maximum PCI burst. */
205 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
206
207 Cfg9346 = 0x50,
208 Config0 = 0x51,
209 Config1 = 0x52,
210 Config2 = 0x53,
211 #define PME_SIGNAL (1 << 5) /* 8168c and later */
212
213 Config3 = 0x54,
214 Config4 = 0x55,
215 Config5 = 0x56,
216 PHYAR = 0x60,
217 PHYstatus = 0x6c,
218 RxMaxSize = 0xda,
219 CPlusCmd = 0xe0,
220 IntrMitigate = 0xe2,
221
222 #define RTL_COALESCE_TX_USECS GENMASK(15, 12)
223 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
224 #define RTL_COALESCE_RX_USECS GENMASK(7, 4)
225 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
226
227 #define RTL_COALESCE_T_MAX 0x0fU
228 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
229
230 RxDescAddrLow = 0xe4,
231 RxDescAddrHigh = 0xe8,
232 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
233
234 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
235
236 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
237
238 #define TxPacketMax (8064 >> 7)
239 #define EarlySize 0x27
240
241 FuncEvent = 0xf0,
242 FuncEventMask = 0xf4,
243 FuncPresetState = 0xf8,
244 IBCR0 = 0xf8,
245 IBCR2 = 0xf9,
246 IBIMR0 = 0xfa,
247 IBISR0 = 0xfb,
248 FuncForceEvent = 0xfc,
249 };
250
251 enum rtl8168_8101_registers {
252 CSIDR = 0x64,
253 CSIAR = 0x68,
254 #define CSIAR_FLAG 0x80000000
255 #define CSIAR_WRITE_CMD 0x80000000
256 #define CSIAR_BYTE_ENABLE 0x0000f000
257 #define CSIAR_ADDR_MASK 0x00000fff
258 PMCH = 0x6f,
259 #define D3COLD_NO_PLL_DOWN BIT(7)
260 #define D3HOT_NO_PLL_DOWN BIT(6)
261 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
262 EPHYAR = 0x80,
263 #define EPHYAR_FLAG 0x80000000
264 #define EPHYAR_WRITE_CMD 0x80000000
265 #define EPHYAR_REG_MASK 0x1f
266 #define EPHYAR_REG_SHIFT 16
267 #define EPHYAR_DATA_MASK 0xffff
268 DLLPR = 0xd0,
269 #define PFM_EN (1 << 6)
270 #define TX_10M_PS_EN (1 << 7)
271 DBG_REG = 0xd1,
272 #define FIX_NAK_1 (1 << 4)
273 #define FIX_NAK_2 (1 << 3)
274 TWSI = 0xd2,
275 MCU = 0xd3,
276 #define NOW_IS_OOB (1 << 7)
277 #define TX_EMPTY (1 << 5)
278 #define RX_EMPTY (1 << 4)
279 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
280 #define EN_NDP (1 << 3)
281 #define EN_OOB_RESET (1 << 2)
282 #define LINK_LIST_RDY (1 << 1)
283 EFUSEAR = 0xdc,
284 #define EFUSEAR_FLAG 0x80000000
285 #define EFUSEAR_WRITE_CMD 0x80000000
286 #define EFUSEAR_READ_CMD 0x00000000
287 #define EFUSEAR_REG_MASK 0x03ff
288 #define EFUSEAR_REG_SHIFT 8
289 #define EFUSEAR_DATA_MASK 0xff
290 MISC_1 = 0xf2,
291 #define PFM_D3COLD_EN (1 << 6)
292 };
293
294 enum rtl8168_registers {
295 LED_CTRL = 0x18,
296 LED_FREQ = 0x1a,
297 EEE_LED = 0x1b,
298 ERIDR = 0x70,
299 ERIAR = 0x74,
300 #define ERIAR_FLAG 0x80000000
301 #define ERIAR_WRITE_CMD 0x80000000
302 #define ERIAR_READ_CMD 0x00000000
303 #define ERIAR_ADDR_BYTE_ALIGN 4
304 #define ERIAR_TYPE_SHIFT 16
305 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
306 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
307 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
308 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
309 #define ERIAR_MASK_SHIFT 12
310 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
311 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
312 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
313 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
314 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
315 EPHY_RXER_NUM = 0x7c,
316 OCPDR = 0xb0, /* OCP GPHY access */
317 #define OCPDR_WRITE_CMD 0x80000000
318 #define OCPDR_READ_CMD 0x00000000
319 #define OCPDR_REG_MASK 0x7f
320 #define OCPDR_GPHY_REG_SHIFT 16
321 #define OCPDR_DATA_MASK 0xffff
322 OCPAR = 0xb4,
323 #define OCPAR_FLAG 0x80000000
324 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
325 #define OCPAR_GPHY_READ_CMD 0x0000f060
326 GPHY_OCP = 0xb8,
327 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
328 MISC = 0xf0, /* 8168e only. */
329 #define TXPLA_RST (1 << 29)
330 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
331 #define PWM_EN (1 << 22)
332 #define RXDV_GATED_EN (1 << 19)
333 #define EARLY_TALLY_EN (1 << 16)
334 };
335
336 enum rtl8125_registers {
337 LEDSEL0 = 0x18,
338 INT_CFG0_8125 = 0x34,
339 #define INT_CFG0_ENABLE_8125 BIT(0)
340 #define INT_CFG0_CLKREQEN BIT(3)
341 IntrMask_8125 = 0x38,
342 IntrStatus_8125 = 0x3c,
343 INT_CFG1_8125 = 0x7a,
344 LEDSEL2 = 0x84,
345 LEDSEL1 = 0x86,
346 TxPoll_8125 = 0x90,
347 LEDSEL3 = 0x96,
348 MAC0_BKP = 0x19e0,
349 EEE_TXIDLE_TIMER_8125 = 0x6048,
350 };
351
352 #define LEDSEL_MASK_8125 0x23f
353
354 #define RX_VLAN_INNER_8125 BIT(22)
355 #define RX_VLAN_OUTER_8125 BIT(23)
356 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
357
358 #define RX_FETCH_DFLT_8125 (8 << 27)
359
360 enum rtl_register_content {
361 /* InterruptStatusBits */
362 SYSErr = 0x8000,
363 PCSTimeout = 0x4000,
364 SWInt = 0x0100,
365 TxDescUnavail = 0x0080,
366 RxFIFOOver = 0x0040,
367 LinkChg = 0x0020,
368 RxOverflow = 0x0010,
369 TxErr = 0x0008,
370 TxOK = 0x0004,
371 RxErr = 0x0002,
372 RxOK = 0x0001,
373
374 /* RxStatusDesc */
375 RxRWT = (1 << 22),
376 RxRES = (1 << 21),
377 RxRUNT = (1 << 20),
378 RxCRC = (1 << 19),
379
380 /* ChipCmdBits */
381 StopReq = 0x80,
382 CmdReset = 0x10,
383 CmdRxEnb = 0x08,
384 CmdTxEnb = 0x04,
385 RxBufEmpty = 0x01,
386
387 /* TXPoll register p.5 */
388 HPQ = 0x80, /* Poll cmd on the high prio queue */
389 NPQ = 0x40, /* Poll cmd on the low prio queue */
390 FSWInt = 0x01, /* Forced software interrupt */
391
392 /* Cfg9346Bits */
393 Cfg9346_Lock = 0x00,
394 Cfg9346_Unlock = 0xc0,
395
396 /* rx_mode_bits */
397 AcceptErr = 0x20,
398 AcceptRunt = 0x10,
399 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
400 AcceptBroadcast = 0x08,
401 AcceptMulticast = 0x04,
402 AcceptMyPhys = 0x02,
403 AcceptAllPhys = 0x01,
404 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
405 #define RX_CONFIG_ACCEPT_MASK 0x3f
406
407 /* TxConfigBits */
408 TxInterFrameGapShift = 24,
409 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
410
411 /* Config1 register p.24 */
412 LEDS1 = (1 << 7),
413 LEDS0 = (1 << 6),
414 Speed_down = (1 << 4),
415 MEMMAP = (1 << 3),
416 IOMAP = (1 << 2),
417 VPD = (1 << 1),
418 PMEnable = (1 << 0), /* Power Management Enable */
419
420 /* Config2 register p. 25 */
421 ClkReqEn = (1 << 7), /* Clock Request Enable */
422 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
423 PCI_Clock_66MHz = 0x01,
424 PCI_Clock_33MHz = 0x00,
425
426 /* Config3 register p.25 */
427 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
428 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
429 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
430 Rdy_to_L23 = (1 << 1), /* L23 Enable */
431 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
432
433 /* Config4 register */
434 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
435
436 /* Config5 register p.27 */
437 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
438 MWF = (1 << 5), /* Accept Multicast wakeup frame */
439 UWF = (1 << 4), /* Accept Unicast wakeup frame */
440 Spi_en = (1 << 3),
441 LanWake = (1 << 1), /* LanWake enable/disable */
442 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
443 ASPM_en = (1 << 0), /* ASPM enable */
444
445 /* CPlusCmd p.31 */
446 EnableBist = (1 << 15), // 8168 8101
447 Mac_dbgo_oe = (1 << 14), // 8168 8101
448 EnAnaPLL = (1 << 14), // 8169
449 Normal_mode = (1 << 13), // unused
450 Force_half_dup = (1 << 12), // 8168 8101
451 Force_rxflow_en = (1 << 11), // 8168 8101
452 Force_txflow_en = (1 << 10), // 8168 8101
453 Cxpl_dbg_sel = (1 << 9), // 8168 8101
454 ASF = (1 << 8), // 8168 8101
455 PktCntrDisable = (1 << 7), // 8168 8101
456 Mac_dbgo_sel = 0x001c, // 8168
457 RxVlan = (1 << 6),
458 RxChkSum = (1 << 5),
459 PCIDAC = (1 << 4),
460 PCIMulRW = (1 << 3),
461 #define INTT_MASK GENMASK(1, 0)
462 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
463
464 /* rtl8169_PHYstatus */
465 TBI_Enable = 0x80,
466 TxFlowCtrl = 0x40,
467 RxFlowCtrl = 0x20,
468 _1000bpsF = 0x10,
469 _100bps = 0x08,
470 _10bps = 0x04,
471 LinkStatus = 0x02,
472 FullDup = 0x01,
473
474 /* ResetCounterCommand */
475 CounterReset = 0x1,
476
477 /* DumpCounterCommand */
478 CounterDump = 0x8,
479
480 /* magic enable v2 */
481 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
482 };
483
484 enum rtl_desc_bit {
485 /* First doubleword. */
486 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
487 RingEnd = (1 << 30), /* End of descriptor ring */
488 FirstFrag = (1 << 29), /* First segment of a packet */
489 LastFrag = (1 << 28), /* Final segment of a packet */
490 };
491
492 /* Generic case. */
493 enum rtl_tx_desc_bit {
494 /* First doubleword. */
495 TD_LSO = (1 << 27), /* Large Send Offload */
496 #define TD_MSS_MAX 0x07ffu /* MSS value */
497
498 /* Second doubleword. */
499 TxVlanTag = (1 << 17), /* Add VLAN tag */
500 };
501
502 /* 8169, 8168b and 810x except 8102e. */
503 enum rtl_tx_desc_bit_0 {
504 /* First doubleword. */
505 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
506 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
507 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
508 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
509 };
510
511 /* 8102e, 8168c and beyond. */
512 enum rtl_tx_desc_bit_1 {
513 /* First doubleword. */
514 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
515 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
516 #define GTTCPHO_SHIFT 18
517 #define GTTCPHO_MAX 0x7f
518
519 /* Second doubleword. */
520 #define TCPHO_SHIFT 18
521 #define TCPHO_MAX 0x3ff
522 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
523 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
524 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
525 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
526 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
527 };
528
529 enum rtl_rx_desc_bit {
530 /* Rx private */
531 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
532 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
533
534 #define RxProtoUDP (PID1)
535 #define RxProtoTCP (PID0)
536 #define RxProtoIP (PID1 | PID0)
537 #define RxProtoMask RxProtoIP
538
539 IPFail = (1 << 16), /* IP checksum failed */
540 UDPFail = (1 << 15), /* UDP/IP checksum failed */
541 TCPFail = (1 << 14), /* TCP/IP checksum failed */
542
543 #define RxCSFailMask (IPFail | UDPFail | TCPFail)
544
545 RxVlanTag = (1 << 16), /* VLAN tag available */
546 };
547
548 #define RTL_GSO_MAX_SIZE_V1 32000
549 #define RTL_GSO_MAX_SEGS_V1 24
550 #define RTL_GSO_MAX_SIZE_V2 64000
551 #define RTL_GSO_MAX_SEGS_V2 64
552
553 struct TxDesc {
554 __le32 opts1;
555 __le32 opts2;
556 __le64 addr;
557 };
558
559 struct RxDesc {
560 __le32 opts1;
561 __le32 opts2;
562 __le64 addr;
563 };
564
565 struct ring_info {
566 struct sk_buff *skb;
567 u32 len;
568 };
569
570 struct rtl8169_counters {
571 __le64 tx_packets;
572 __le64 rx_packets;
573 __le64 tx_errors;
574 __le32 rx_errors;
575 __le16 rx_missed;
576 __le16 align_errors;
577 __le32 tx_one_collision;
578 __le32 tx_multi_collision;
579 __le64 rx_unicast;
580 __le64 rx_broadcast;
581 __le32 rx_multicast;
582 __le16 tx_aborted;
583 __le16 tx_underrun;
584 /* new since RTL8125 */
585 __le64 tx_octets;
586 __le64 rx_octets;
587 __le64 rx_multicast64;
588 __le64 tx_unicast64;
589 __le64 tx_broadcast64;
590 __le64 tx_multicast64;
591 __le32 tx_pause_on;
592 __le32 tx_pause_off;
593 __le32 tx_pause_all;
594 __le32 tx_deferred;
595 __le32 tx_late_collision;
596 __le32 tx_all_collision;
597 __le32 tx_aborted32;
598 __le32 align_errors32;
599 __le32 rx_frame_too_long;
600 __le32 rx_runt;
601 __le32 rx_pause_on;
602 __le32 rx_pause_off;
603 __le32 rx_pause_all;
604 __le32 rx_unknown_opcode;
605 __le32 rx_mac_error;
606 __le32 tx_underrun32;
607 __le32 rx_mac_missed;
608 __le32 rx_tcam_dropped;
609 __le32 tdu;
610 __le32 rdu;
611 };
612
613 struct rtl8169_tc_offsets {
614 bool inited;
615 __le64 tx_errors;
616 __le32 tx_multi_collision;
617 __le16 tx_aborted;
618 __le16 rx_missed;
619 };
620
621 enum rtl_flag {
622 RTL_FLAG_TASK_ENABLED = 0,
623 RTL_FLAG_TASK_RESET_PENDING,
624 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE,
625 RTL_FLAG_TASK_TX_TIMEOUT,
626 RTL_FLAG_MAX
627 };
628
629 enum rtl_dash_type {
630 RTL_DASH_NONE,
631 RTL_DASH_DP,
632 RTL_DASH_EP,
633 };
634
635 struct rtl8169_private {
636 void __iomem *mmio_addr; /* memory map physical address */
637 struct pci_dev *pci_dev;
638 struct net_device *dev;
639 struct phy_device *phydev;
640 struct napi_struct napi;
641 enum mac_version mac_version;
642 enum rtl_dash_type dash_type;
643 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
644 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
645 u32 dirty_tx;
646 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
647 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
648 dma_addr_t TxPhyAddr;
649 dma_addr_t RxPhyAddr;
650 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
651 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
652 u16 cp_cmd;
653 u16 tx_lpi_timer;
654 u32 irq_mask;
655 int irq;
656 struct clk *clk;
657
658 struct {
659 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
660 struct work_struct work;
661 } wk;
662
663 raw_spinlock_t config25_lock;
664 raw_spinlock_t mac_ocp_lock;
665 struct mutex led_lock; /* serialize LED ctrl RMW access */
666
667 raw_spinlock_t cfg9346_usage_lock;
668 int cfg9346_usage_count;
669
670 unsigned supports_gmii:1;
671 unsigned aspm_manageable:1;
672 unsigned dash_enabled:1;
673 dma_addr_t counters_phys_addr;
674 struct rtl8169_counters *counters;
675 struct rtl8169_tc_offsets tc_offset;
676 u32 saved_wolopts;
677
678 const char *fw_name;
679 struct rtl_fw *rtl_fw;
680
681 struct r8169_led_classdev *leds;
682
683 u32 ocp_base;
684 };
685
686 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
687
688 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
689 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
690 MODULE_SOFTDEP("pre: realtek");
691 MODULE_LICENSE("GPL");
692 MODULE_FIRMWARE(FIRMWARE_8168D_1);
693 MODULE_FIRMWARE(FIRMWARE_8168D_2);
694 MODULE_FIRMWARE(FIRMWARE_8168E_1);
695 MODULE_FIRMWARE(FIRMWARE_8168E_2);
696 MODULE_FIRMWARE(FIRMWARE_8168E_3);
697 MODULE_FIRMWARE(FIRMWARE_8105E_1);
698 MODULE_FIRMWARE(FIRMWARE_8168F_1);
699 MODULE_FIRMWARE(FIRMWARE_8168F_2);
700 MODULE_FIRMWARE(FIRMWARE_8402_1);
701 MODULE_FIRMWARE(FIRMWARE_8411_1);
702 MODULE_FIRMWARE(FIRMWARE_8411_2);
703 MODULE_FIRMWARE(FIRMWARE_8106E_1);
704 MODULE_FIRMWARE(FIRMWARE_8106E_2);
705 MODULE_FIRMWARE(FIRMWARE_8168G_2);
706 MODULE_FIRMWARE(FIRMWARE_8168G_3);
707 MODULE_FIRMWARE(FIRMWARE_8168H_2);
708 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
709 MODULE_FIRMWARE(FIRMWARE_8107E_2);
710 MODULE_FIRMWARE(FIRMWARE_8125A_3);
711 MODULE_FIRMWARE(FIRMWARE_8125B_2);
712 MODULE_FIRMWARE(FIRMWARE_8125D_1);
713 MODULE_FIRMWARE(FIRMWARE_8126A_2);
714 MODULE_FIRMWARE(FIRMWARE_8126A_3);
715
tp_to_dev(struct rtl8169_private * tp)716 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
717 {
718 return &tp->pci_dev->dev;
719 }
720
rtl_lock_config_regs(struct rtl8169_private * tp)721 static void rtl_lock_config_regs(struct rtl8169_private *tp)
722 {
723 unsigned long flags;
724
725 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
726 if (!--tp->cfg9346_usage_count)
727 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
728 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
729 }
730
rtl_unlock_config_regs(struct rtl8169_private * tp)731 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
732 {
733 unsigned long flags;
734
735 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);
736 if (!tp->cfg9346_usage_count++)
737 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
738 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);
739 }
740
rtl_pci_commit(struct rtl8169_private * tp)741 static void rtl_pci_commit(struct rtl8169_private *tp)
742 {
743 /* Read an arbitrary register to commit a preceding PCI write */
744 RTL_R8(tp, ChipCmd);
745 }
746
rtl_mod_config2(struct rtl8169_private * tp,u8 clear,u8 set)747 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
748 {
749 unsigned long flags;
750 u8 val;
751
752 raw_spin_lock_irqsave(&tp->config25_lock, flags);
753 val = RTL_R8(tp, Config2);
754 RTL_W8(tp, Config2, (val & ~clear) | set);
755 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
756 }
757
rtl_mod_config5(struct rtl8169_private * tp,u8 clear,u8 set)758 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
759 {
760 unsigned long flags;
761 u8 val;
762
763 raw_spin_lock_irqsave(&tp->config25_lock, flags);
764 val = RTL_R8(tp, Config5);
765 RTL_W8(tp, Config5, (val & ~clear) | set);
766 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
767 }
768
rtl_is_8125(struct rtl8169_private * tp)769 static bool rtl_is_8125(struct rtl8169_private *tp)
770 {
771 return tp->mac_version >= RTL_GIGA_MAC_VER_61;
772 }
773
rtl_is_8168evl_up(struct rtl8169_private * tp)774 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
775 {
776 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
777 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
778 tp->mac_version <= RTL_GIGA_MAC_VER_53;
779 }
780
rtl_supports_eee(struct rtl8169_private * tp)781 static bool rtl_supports_eee(struct rtl8169_private *tp)
782 {
783 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
784 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
785 tp->mac_version != RTL_GIGA_MAC_VER_39;
786 }
787
rtl_read_mac_from_reg(struct rtl8169_private * tp,u8 * mac,int reg)788 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
789 {
790 int i;
791
792 for (i = 0; i < ETH_ALEN; i++)
793 mac[i] = RTL_R8(tp, reg + i);
794 }
795
796 struct rtl_cond {
797 bool (*check)(struct rtl8169_private *);
798 const char *msg;
799 };
800
rtl_loop_wait(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long usecs,int n,bool high)801 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
802 unsigned long usecs, int n, bool high)
803 {
804 int i;
805
806 for (i = 0; i < n; i++) {
807 if (c->check(tp) == high)
808 return true;
809 fsleep(usecs);
810 }
811
812 if (net_ratelimit())
813 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
814 c->msg, !high, n, usecs);
815 return false;
816 }
817
rtl_loop_wait_high(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long d,int n)818 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
819 const struct rtl_cond *c,
820 unsigned long d, int n)
821 {
822 return rtl_loop_wait(tp, c, d, n, true);
823 }
824
rtl_loop_wait_low(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long d,int n)825 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
826 const struct rtl_cond *c,
827 unsigned long d, int n)
828 {
829 return rtl_loop_wait(tp, c, d, n, false);
830 }
831
832 #define DECLARE_RTL_COND(name) \
833 static bool name ## _check(struct rtl8169_private *); \
834 \
835 static const struct rtl_cond name = { \
836 .check = name ## _check, \
837 .msg = #name \
838 }; \
839 \
840 static bool name ## _check(struct rtl8169_private *tp)
841
rtl8168_led_mod_ctrl(struct rtl8169_private * tp,u16 mask,u16 val)842 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val)
843 {
844 struct device *dev = tp_to_dev(tp);
845 int ret;
846
847 ret = pm_runtime_resume_and_get(dev);
848 if (ret < 0)
849 return ret;
850
851 mutex_lock(&tp->led_lock);
852 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val);
853 mutex_unlock(&tp->led_lock);
854
855 pm_runtime_put_sync(dev);
856
857 return 0;
858 }
859
rtl8168_get_led_mode(struct rtl8169_private * tp)860 int rtl8168_get_led_mode(struct rtl8169_private *tp)
861 {
862 struct device *dev = tp_to_dev(tp);
863 int ret;
864
865 ret = pm_runtime_resume_and_get(dev);
866 if (ret < 0)
867 return ret;
868
869 ret = RTL_R16(tp, LED_CTRL);
870
871 pm_runtime_put_sync(dev);
872
873 return ret;
874 }
875
rtl8125_get_led_reg(int index)876 static int rtl8125_get_led_reg(int index)
877 {
878 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 };
879
880 return led_regs[index];
881 }
882
rtl8125_set_led_mode(struct rtl8169_private * tp,int index,u16 mode)883 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode)
884 {
885 int reg = rtl8125_get_led_reg(index);
886 struct device *dev = tp_to_dev(tp);
887 int ret;
888 u16 val;
889
890 ret = pm_runtime_resume_and_get(dev);
891 if (ret < 0)
892 return ret;
893
894 mutex_lock(&tp->led_lock);
895 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125;
896 RTL_W16(tp, reg, val | mode);
897 mutex_unlock(&tp->led_lock);
898
899 pm_runtime_put_sync(dev);
900
901 return 0;
902 }
903
rtl8125_get_led_mode(struct rtl8169_private * tp,int index)904 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index)
905 {
906 int reg = rtl8125_get_led_reg(index);
907 struct device *dev = tp_to_dev(tp);
908 int ret;
909
910 ret = pm_runtime_resume_and_get(dev);
911 if (ret < 0)
912 return ret;
913
914 ret = RTL_R16(tp, reg);
915
916 pm_runtime_put_sync(dev);
917
918 return ret;
919 }
920
r8169_get_led_name(struct rtl8169_private * tp,int idx,char * buf,int buf_len)921 void r8169_get_led_name(struct rtl8169_private *tp, int idx,
922 char *buf, int buf_len)
923 {
924 struct pci_dev *pdev = tp->pci_dev;
925 char pdom[8], pfun[8];
926 int domain;
927
928 domain = pci_domain_nr(pdev->bus);
929 if (domain)
930 snprintf(pdom, sizeof(pdom), "P%d", domain);
931 else
932 pdom[0] = '\0';
933
934 if (pdev->multifunction)
935 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn));
936 else
937 pfun[0] = '\0';
938
939 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number,
940 PCI_SLOT(pdev->devfn), pfun, idx);
941 }
942
r8168fp_adjust_ocp_cmd(struct rtl8169_private * tp,u32 * cmd,int type)943 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
944 {
945 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
946 if (type == ERIAR_OOB &&
947 (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
948 tp->mac_version == RTL_GIGA_MAC_VER_53))
949 *cmd |= 0xf70 << 18;
950 }
951
DECLARE_RTL_COND(rtl_eriar_cond)952 DECLARE_RTL_COND(rtl_eriar_cond)
953 {
954 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
955 }
956
_rtl_eri_write(struct rtl8169_private * tp,int addr,u32 mask,u32 val,int type)957 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
958 u32 val, int type)
959 {
960 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
961
962 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
963 return;
964
965 RTL_W32(tp, ERIDR, val);
966 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
967 RTL_W32(tp, ERIAR, cmd);
968
969 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
970 }
971
rtl_eri_write(struct rtl8169_private * tp,int addr,u32 mask,u32 val)972 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
973 u32 val)
974 {
975 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
976 }
977
_rtl_eri_read(struct rtl8169_private * tp,int addr,int type)978 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
979 {
980 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
981
982 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
983 RTL_W32(tp, ERIAR, cmd);
984
985 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
986 RTL_R32(tp, ERIDR) : ~0;
987 }
988
rtl_eri_read(struct rtl8169_private * tp,int addr)989 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
990 {
991 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
992 }
993
rtl_w0w1_eri(struct rtl8169_private * tp,int addr,u32 p,u32 m)994 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
995 {
996 u32 val = rtl_eri_read(tp, addr);
997
998 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
999 }
1000
rtl_eri_set_bits(struct rtl8169_private * tp,int addr,u32 p)1001 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1002 {
1003 rtl_w0w1_eri(tp, addr, p, 0);
1004 }
1005
rtl_eri_clear_bits(struct rtl8169_private * tp,int addr,u32 m)1006 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1007 {
1008 rtl_w0w1_eri(tp, addr, 0, m);
1009 }
1010
rtl_ocp_reg_failure(u32 reg)1011 static bool rtl_ocp_reg_failure(u32 reg)
1012 {
1013 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
1014 }
1015
DECLARE_RTL_COND(rtl_ocp_gphy_cond)1016 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1017 {
1018 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
1019 }
1020
r8168_phy_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)1021 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1022 {
1023 if (rtl_ocp_reg_failure(reg))
1024 return;
1025
1026 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1027
1028 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1029 }
1030
r8168_phy_ocp_read(struct rtl8169_private * tp,u32 reg)1031 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1032 {
1033 if (rtl_ocp_reg_failure(reg))
1034 return 0;
1035
1036 RTL_W32(tp, GPHY_OCP, reg << 15);
1037
1038 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1039 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
1040 }
1041
__r8168_mac_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)1042 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1043 {
1044 if (rtl_ocp_reg_failure(reg))
1045 return;
1046
1047 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
1048 }
1049
r8168_mac_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)1050 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1051 {
1052 unsigned long flags;
1053
1054 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1055 __r8168_mac_ocp_write(tp, reg, data);
1056 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1057 }
1058
__r8168_mac_ocp_read(struct rtl8169_private * tp,u32 reg)1059 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1060 {
1061 if (rtl_ocp_reg_failure(reg))
1062 return 0;
1063
1064 RTL_W32(tp, OCPDR, reg << 15);
1065
1066 return RTL_R32(tp, OCPDR);
1067 }
1068
r8168_mac_ocp_read(struct rtl8169_private * tp,u32 reg)1069 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1070 {
1071 unsigned long flags;
1072 u16 val;
1073
1074 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1075 val = __r8168_mac_ocp_read(tp, reg);
1076 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1077
1078 return val;
1079 }
1080
r8168_mac_ocp_modify(struct rtl8169_private * tp,u32 reg,u16 mask,u16 set)1081 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
1082 u16 set)
1083 {
1084 unsigned long flags;
1085 u16 data;
1086
1087 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1088 data = __r8168_mac_ocp_read(tp, reg);
1089 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
1090 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1091 }
1092
1093 /* Work around a hw issue with RTL8168g PHY, the quirk disables
1094 * PHY MCU interrupts before PHY power-down.
1095 */
rtl8168g_phy_suspend_quirk(struct rtl8169_private * tp,int value)1096 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
1097 {
1098 switch (tp->mac_version) {
1099 case RTL_GIGA_MAC_VER_40:
1100 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
1101 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
1102 else
1103 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
1104 break;
1105 default:
1106 break;
1107 }
1108 };
1109
r8168g_mdio_write(struct rtl8169_private * tp,int reg,int value)1110 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1111 {
1112 if (reg == 0x1f) {
1113 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1114 return;
1115 }
1116
1117 if (tp->ocp_base != OCP_STD_PHY_BASE)
1118 reg -= 0x10;
1119
1120 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
1121 rtl8168g_phy_suspend_quirk(tp, value);
1122
1123 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1124 }
1125
r8168g_mdio_read(struct rtl8169_private * tp,int reg)1126 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1127 {
1128 if (reg == 0x1f)
1129 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
1130
1131 if (tp->ocp_base != OCP_STD_PHY_BASE)
1132 reg -= 0x10;
1133
1134 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1135 }
1136
mac_mcu_write(struct rtl8169_private * tp,int reg,int value)1137 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1138 {
1139 if (reg == 0x1f) {
1140 tp->ocp_base = value << 4;
1141 return;
1142 }
1143
1144 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1145 }
1146
mac_mcu_read(struct rtl8169_private * tp,int reg)1147 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1148 {
1149 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1150 }
1151
DECLARE_RTL_COND(rtl_phyar_cond)1152 DECLARE_RTL_COND(rtl_phyar_cond)
1153 {
1154 return RTL_R32(tp, PHYAR) & 0x80000000;
1155 }
1156
r8169_mdio_write(struct rtl8169_private * tp,int reg,int value)1157 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1158 {
1159 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1160
1161 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1162 /*
1163 * According to hardware specs a 20us delay is required after write
1164 * complete indication, but before sending next command.
1165 */
1166 udelay(20);
1167 }
1168
r8169_mdio_read(struct rtl8169_private * tp,int reg)1169 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1170 {
1171 int value;
1172
1173 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1174
1175 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1176 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1177
1178 /*
1179 * According to hardware specs a 20us delay is required after read
1180 * complete indication, but before sending next command.
1181 */
1182 udelay(20);
1183
1184 return value;
1185 }
1186
DECLARE_RTL_COND(rtl_ocpar_cond)1187 DECLARE_RTL_COND(rtl_ocpar_cond)
1188 {
1189 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1190 }
1191
1192 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1193
r8168dp_2_mdio_start(struct rtl8169_private * tp)1194 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1195 {
1196 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1197 }
1198
r8168dp_2_mdio_stop(struct rtl8169_private * tp)1199 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1200 {
1201 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1202 }
1203
r8168dp_2_mdio_write(struct rtl8169_private * tp,int reg,int value)1204 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1205 {
1206 r8168dp_2_mdio_start(tp);
1207
1208 r8169_mdio_write(tp, reg, value);
1209
1210 r8168dp_2_mdio_stop(tp);
1211 }
1212
r8168dp_2_mdio_read(struct rtl8169_private * tp,int reg)1213 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1214 {
1215 int value;
1216
1217 /* Work around issue with chip reporting wrong PHY ID */
1218 if (reg == MII_PHYSID2)
1219 return 0xc912;
1220
1221 r8168dp_2_mdio_start(tp);
1222
1223 value = r8169_mdio_read(tp, reg);
1224
1225 r8168dp_2_mdio_stop(tp);
1226
1227 return value;
1228 }
1229
rtl_writephy(struct rtl8169_private * tp,int location,int val)1230 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1231 {
1232 switch (tp->mac_version) {
1233 case RTL_GIGA_MAC_VER_28:
1234 case RTL_GIGA_MAC_VER_31:
1235 r8168dp_2_mdio_write(tp, location, val);
1236 break;
1237 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:
1238 r8168g_mdio_write(tp, location, val);
1239 break;
1240 default:
1241 r8169_mdio_write(tp, location, val);
1242 break;
1243 }
1244 }
1245
rtl_readphy(struct rtl8169_private * tp,int location)1246 static int rtl_readphy(struct rtl8169_private *tp, int location)
1247 {
1248 switch (tp->mac_version) {
1249 case RTL_GIGA_MAC_VER_28:
1250 case RTL_GIGA_MAC_VER_31:
1251 return r8168dp_2_mdio_read(tp, location);
1252 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:
1253 return r8168g_mdio_read(tp, location);
1254 default:
1255 return r8169_mdio_read(tp, location);
1256 }
1257 }
1258
DECLARE_RTL_COND(rtl_ephyar_cond)1259 DECLARE_RTL_COND(rtl_ephyar_cond)
1260 {
1261 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1262 }
1263
rtl_ephy_write(struct rtl8169_private * tp,int reg_addr,int value)1264 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1265 {
1266 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1267 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1268
1269 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1270
1271 udelay(10);
1272 }
1273
rtl_ephy_read(struct rtl8169_private * tp,int reg_addr)1274 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1275 {
1276 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1277
1278 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1279 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1280 }
1281
r8168dp_ocp_read(struct rtl8169_private * tp,u16 reg)1282 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1283 {
1284 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1285 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1286 RTL_R32(tp, OCPDR) : ~0;
1287 }
1288
r8168ep_ocp_read(struct rtl8169_private * tp,u16 reg)1289 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1290 {
1291 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1292 }
1293
r8168dp_ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1294 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1295 u32 data)
1296 {
1297 RTL_W32(tp, OCPDR, data);
1298 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1299 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1300 }
1301
r8168ep_ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1302 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1303 u32 data)
1304 {
1305 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1306 data, ERIAR_OOB);
1307 }
1308
r8168dp_oob_notify(struct rtl8169_private * tp,u8 cmd)1309 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1310 {
1311 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1312
1313 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1314 }
1315
1316 #define OOB_CMD_RESET 0x00
1317 #define OOB_CMD_DRIVER_START 0x05
1318 #define OOB_CMD_DRIVER_STOP 0x06
1319
rtl8168_get_ocp_reg(struct rtl8169_private * tp)1320 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1321 {
1322 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1323 }
1324
DECLARE_RTL_COND(rtl_dp_ocp_read_cond)1325 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1326 {
1327 u16 reg;
1328
1329 reg = rtl8168_get_ocp_reg(tp);
1330
1331 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1332 }
1333
DECLARE_RTL_COND(rtl_ep_ocp_read_cond)1334 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1335 {
1336 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1337 }
1338
DECLARE_RTL_COND(rtl_ocp_tx_cond)1339 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1340 {
1341 return RTL_R8(tp, IBISR0) & 0x20;
1342 }
1343
rtl8168ep_stop_cmac(struct rtl8169_private * tp)1344 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1345 {
1346 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1347 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1348 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1349 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1350 }
1351
rtl_dash_loop_wait(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long usecs,int n,bool high)1352 static void rtl_dash_loop_wait(struct rtl8169_private *tp,
1353 const struct rtl_cond *c,
1354 unsigned long usecs, int n, bool high)
1355 {
1356 if (!tp->dash_enabled)
1357 return;
1358 rtl_loop_wait(tp, c, usecs, n, high);
1359 }
1360
rtl_dash_loop_wait_high(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long d,int n)1361 static void rtl_dash_loop_wait_high(struct rtl8169_private *tp,
1362 const struct rtl_cond *c,
1363 unsigned long d, int n)
1364 {
1365 rtl_dash_loop_wait(tp, c, d, n, true);
1366 }
1367
rtl_dash_loop_wait_low(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long d,int n)1368 static void rtl_dash_loop_wait_low(struct rtl8169_private *tp,
1369 const struct rtl_cond *c,
1370 unsigned long d, int n)
1371 {
1372 rtl_dash_loop_wait(tp, c, d, n, false);
1373 }
1374
rtl8168dp_driver_start(struct rtl8169_private * tp)1375 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1376 {
1377 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1378 rtl_dash_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1379 }
1380
rtl8168ep_driver_start(struct rtl8169_private * tp)1381 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1382 {
1383 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1384 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1385 rtl_dash_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30);
1386 }
1387
rtl8168_driver_start(struct rtl8169_private * tp)1388 static void rtl8168_driver_start(struct rtl8169_private *tp)
1389 {
1390 if (tp->dash_type == RTL_DASH_DP)
1391 rtl8168dp_driver_start(tp);
1392 else
1393 rtl8168ep_driver_start(tp);
1394 }
1395
rtl8168dp_driver_stop(struct rtl8169_private * tp)1396 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1397 {
1398 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1399 rtl_dash_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1400 }
1401
rtl8168ep_driver_stop(struct rtl8169_private * tp)1402 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1403 {
1404 rtl8168ep_stop_cmac(tp);
1405 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1406 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1407 rtl_dash_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1408 }
1409
rtl8168_driver_stop(struct rtl8169_private * tp)1410 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1411 {
1412 if (tp->dash_type == RTL_DASH_DP)
1413 rtl8168dp_driver_stop(tp);
1414 else
1415 rtl8168ep_driver_stop(tp);
1416 }
1417
r8168dp_check_dash(struct rtl8169_private * tp)1418 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1419 {
1420 u16 reg = rtl8168_get_ocp_reg(tp);
1421
1422 return r8168dp_ocp_read(tp, reg) & BIT(15);
1423 }
1424
r8168ep_check_dash(struct rtl8169_private * tp)1425 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1426 {
1427 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1428 }
1429
rtl_dash_is_enabled(struct rtl8169_private * tp)1430 static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1431 {
1432 switch (tp->dash_type) {
1433 case RTL_DASH_DP:
1434 return r8168dp_check_dash(tp);
1435 case RTL_DASH_EP:
1436 return r8168ep_check_dash(tp);
1437 default:
1438 return false;
1439 }
1440 }
1441
rtl_get_dash_type(struct rtl8169_private * tp)1442 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
1443 {
1444 switch (tp->mac_version) {
1445 case RTL_GIGA_MAC_VER_28:
1446 case RTL_GIGA_MAC_VER_31:
1447 return RTL_DASH_DP;
1448 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1449 return RTL_DASH_EP;
1450 default:
1451 return RTL_DASH_NONE;
1452 }
1453 }
1454
rtl_set_d3_pll_down(struct rtl8169_private * tp,bool enable)1455 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1456 {
1457 switch (tp->mac_version) {
1458 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1459 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1460 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1461 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66:
1462 if (enable)
1463 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1464 else
1465 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1466 break;
1467 default:
1468 break;
1469 }
1470 }
1471
rtl_reset_packet_filter(struct rtl8169_private * tp)1472 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1473 {
1474 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1475 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1476 }
1477
DECLARE_RTL_COND(rtl_efusear_cond)1478 DECLARE_RTL_COND(rtl_efusear_cond)
1479 {
1480 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1481 }
1482
rtl8168d_efuse_read(struct rtl8169_private * tp,int reg_addr)1483 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1484 {
1485 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1486
1487 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1488 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1489 }
1490
rtl_get_events(struct rtl8169_private * tp)1491 static u32 rtl_get_events(struct rtl8169_private *tp)
1492 {
1493 if (rtl_is_8125(tp))
1494 return RTL_R32(tp, IntrStatus_8125);
1495 else
1496 return RTL_R16(tp, IntrStatus);
1497 }
1498
rtl_ack_events(struct rtl8169_private * tp,u32 bits)1499 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1500 {
1501 if (rtl_is_8125(tp))
1502 RTL_W32(tp, IntrStatus_8125, bits);
1503 else
1504 RTL_W16(tp, IntrStatus, bits);
1505 }
1506
rtl_irq_disable(struct rtl8169_private * tp)1507 static void rtl_irq_disable(struct rtl8169_private *tp)
1508 {
1509 if (rtl_is_8125(tp))
1510 RTL_W32(tp, IntrMask_8125, 0);
1511 else
1512 RTL_W16(tp, IntrMask, 0);
1513 }
1514
rtl_irq_enable(struct rtl8169_private * tp)1515 static void rtl_irq_enable(struct rtl8169_private *tp)
1516 {
1517 if (rtl_is_8125(tp))
1518 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1519 else
1520 RTL_W16(tp, IntrMask, tp->irq_mask);
1521 }
1522
rtl8169_irq_mask_and_ack(struct rtl8169_private * tp)1523 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1524 {
1525 rtl_irq_disable(tp);
1526 rtl_ack_events(tp, 0xffffffff);
1527 rtl_pci_commit(tp);
1528 }
1529
rtl_link_chg_patch(struct rtl8169_private * tp)1530 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1531 {
1532 struct phy_device *phydev = tp->phydev;
1533
1534 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1535 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1536 if (phydev->speed == SPEED_1000) {
1537 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1538 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1539 } else if (phydev->speed == SPEED_100) {
1540 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1541 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1542 } else {
1543 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1544 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1545 }
1546 rtl_reset_packet_filter(tp);
1547 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1548 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1549 if (phydev->speed == SPEED_1000) {
1550 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1551 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1552 } else {
1553 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1554 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1555 }
1556 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1557 if (phydev->speed == SPEED_10) {
1558 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1559 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1560 } else {
1561 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1562 }
1563 }
1564 }
1565
1566 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1567
rtl8169_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1568 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1569 {
1570 struct rtl8169_private *tp = netdev_priv(dev);
1571
1572 wol->supported = WAKE_ANY;
1573 wol->wolopts = tp->saved_wolopts;
1574 }
1575
__rtl8169_set_wol(struct rtl8169_private * tp,u32 wolopts)1576 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1577 {
1578 static const struct {
1579 u32 opt;
1580 u16 reg;
1581 u8 mask;
1582 } cfg[] = {
1583 { WAKE_PHY, Config3, LinkUp },
1584 { WAKE_UCAST, Config5, UWF },
1585 { WAKE_BCAST, Config5, BWF },
1586 { WAKE_MCAST, Config5, MWF },
1587 { WAKE_ANY, Config5, LanWake },
1588 { WAKE_MAGIC, Config3, MagicPacket }
1589 };
1590 unsigned int i, tmp = ARRAY_SIZE(cfg);
1591 unsigned long flags;
1592 u8 options;
1593
1594 rtl_unlock_config_regs(tp);
1595
1596 if (rtl_is_8168evl_up(tp)) {
1597 tmp--;
1598 if (wolopts & WAKE_MAGIC)
1599 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1600 else
1601 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1602 } else if (rtl_is_8125(tp)) {
1603 tmp--;
1604 if (wolopts & WAKE_MAGIC)
1605 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1606 else
1607 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1608 }
1609
1610 raw_spin_lock_irqsave(&tp->config25_lock, flags);
1611 for (i = 0; i < tmp; i++) {
1612 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1613 if (wolopts & cfg[i].opt)
1614 options |= cfg[i].mask;
1615 RTL_W8(tp, cfg[i].reg, options);
1616 }
1617 raw_spin_unlock_irqrestore(&tp->config25_lock, flags);
1618
1619 switch (tp->mac_version) {
1620 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1621 options = RTL_R8(tp, Config1) & ~PMEnable;
1622 if (wolopts)
1623 options |= PMEnable;
1624 RTL_W8(tp, Config1, options);
1625 break;
1626 case RTL_GIGA_MAC_VER_34:
1627 case RTL_GIGA_MAC_VER_37:
1628 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66:
1629 if (wolopts)
1630 rtl_mod_config2(tp, 0, PME_SIGNAL);
1631 else
1632 rtl_mod_config2(tp, PME_SIGNAL, 0);
1633 break;
1634 default:
1635 break;
1636 }
1637
1638 rtl_lock_config_regs(tp);
1639
1640 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1641
1642 if (!tp->dash_enabled) {
1643 rtl_set_d3_pll_down(tp, !wolopts);
1644 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0;
1645 }
1646 }
1647
rtl8169_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1648 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1649 {
1650 struct rtl8169_private *tp = netdev_priv(dev);
1651
1652 if (wol->wolopts & ~WAKE_ANY)
1653 return -EINVAL;
1654
1655 tp->saved_wolopts = wol->wolopts;
1656 __rtl8169_set_wol(tp, tp->saved_wolopts);
1657
1658 return 0;
1659 }
1660
rtl8169_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1661 static void rtl8169_get_drvinfo(struct net_device *dev,
1662 struct ethtool_drvinfo *info)
1663 {
1664 struct rtl8169_private *tp = netdev_priv(dev);
1665 struct rtl_fw *rtl_fw = tp->rtl_fw;
1666
1667 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1668 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1669 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1670 if (rtl_fw)
1671 strscpy(info->fw_version, rtl_fw->version,
1672 sizeof(info->fw_version));
1673 }
1674
rtl8169_get_regs_len(struct net_device * dev)1675 static int rtl8169_get_regs_len(struct net_device *dev)
1676 {
1677 return R8169_REGS_SIZE;
1678 }
1679
rtl8169_fix_features(struct net_device * dev,netdev_features_t features)1680 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1681 netdev_features_t features)
1682 {
1683 struct rtl8169_private *tp = netdev_priv(dev);
1684
1685 if (dev->mtu > TD_MSS_MAX)
1686 features &= ~NETIF_F_ALL_TSO;
1687
1688 if (dev->mtu > ETH_DATA_LEN &&
1689 tp->mac_version > RTL_GIGA_MAC_VER_06)
1690 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1691
1692 return features;
1693 }
1694
rtl_set_rx_config_features(struct rtl8169_private * tp,netdev_features_t features)1695 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1696 netdev_features_t features)
1697 {
1698 u32 rx_config = RTL_R32(tp, RxConfig);
1699
1700 if (features & NETIF_F_RXALL)
1701 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1702 else
1703 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1704
1705 if (rtl_is_8125(tp)) {
1706 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1707 rx_config |= RX_VLAN_8125;
1708 else
1709 rx_config &= ~RX_VLAN_8125;
1710 }
1711
1712 RTL_W32(tp, RxConfig, rx_config);
1713 }
1714
rtl8169_set_features(struct net_device * dev,netdev_features_t features)1715 static int rtl8169_set_features(struct net_device *dev,
1716 netdev_features_t features)
1717 {
1718 struct rtl8169_private *tp = netdev_priv(dev);
1719
1720 rtl_set_rx_config_features(tp, features);
1721
1722 if (features & NETIF_F_RXCSUM)
1723 tp->cp_cmd |= RxChkSum;
1724 else
1725 tp->cp_cmd &= ~RxChkSum;
1726
1727 if (!rtl_is_8125(tp)) {
1728 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1729 tp->cp_cmd |= RxVlan;
1730 else
1731 tp->cp_cmd &= ~RxVlan;
1732 }
1733
1734 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1735 rtl_pci_commit(tp);
1736
1737 return 0;
1738 }
1739
rtl8169_tx_vlan_tag(struct sk_buff * skb)1740 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1741 {
1742 return (skb_vlan_tag_present(skb)) ?
1743 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1744 }
1745
rtl8169_rx_vlan_tag(struct RxDesc * desc,struct sk_buff * skb)1746 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1747 {
1748 u32 opts2 = le32_to_cpu(desc->opts2);
1749
1750 if (opts2 & RxVlanTag)
1751 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1752 }
1753
rtl8169_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)1754 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1755 void *p)
1756 {
1757 struct rtl8169_private *tp = netdev_priv(dev);
1758 u32 __iomem *data = tp->mmio_addr;
1759 u32 *dw = p;
1760 int i;
1761
1762 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1763 memcpy_fromio(dw++, data++, 4);
1764 }
1765
1766 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1767 "tx_packets",
1768 "rx_packets",
1769 "tx_errors",
1770 "rx_errors",
1771 "rx_missed",
1772 "align_errors",
1773 "tx_single_collisions",
1774 "tx_multi_collisions",
1775 "unicast",
1776 "broadcast",
1777 "multicast",
1778 "tx_aborted",
1779 "tx_underrun",
1780 };
1781
rtl8169_get_sset_count(struct net_device * dev,int sset)1782 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1783 {
1784 switch (sset) {
1785 case ETH_SS_STATS:
1786 return ARRAY_SIZE(rtl8169_gstrings);
1787 default:
1788 return -EOPNOTSUPP;
1789 }
1790 }
1791
DECLARE_RTL_COND(rtl_counters_cond)1792 DECLARE_RTL_COND(rtl_counters_cond)
1793 {
1794 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1795 }
1796
rtl8169_do_counters(struct rtl8169_private * tp,u32 counter_cmd)1797 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1798 {
1799 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1800
1801 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1802 rtl_pci_commit(tp);
1803 RTL_W32(tp, CounterAddrLow, cmd);
1804 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1805
1806 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1807 }
1808
rtl8169_update_counters(struct rtl8169_private * tp)1809 static void rtl8169_update_counters(struct rtl8169_private *tp)
1810 {
1811 u8 val = RTL_R8(tp, ChipCmd);
1812
1813 /*
1814 * Some chips are unable to dump tally counters when the receiver
1815 * is disabled. If 0xff chip may be in a PCI power-save state.
1816 */
1817 if (val & CmdRxEnb && val != 0xff)
1818 rtl8169_do_counters(tp, CounterDump);
1819 }
1820
rtl8169_init_counter_offsets(struct rtl8169_private * tp)1821 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1822 {
1823 struct rtl8169_counters *counters = tp->counters;
1824
1825 /*
1826 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1827 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1828 * reset by a power cycle, while the counter values collected by the
1829 * driver are reset at every driver unload/load cycle.
1830 *
1831 * To make sure the HW values returned by @get_stats64 match the SW
1832 * values, we collect the initial values at first open(*) and use them
1833 * as offsets to normalize the values returned by @get_stats64.
1834 *
1835 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1836 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1837 * set at open time by rtl_hw_start.
1838 */
1839
1840 if (tp->tc_offset.inited)
1841 return;
1842
1843 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1844 rtl8169_do_counters(tp, CounterReset);
1845 } else {
1846 rtl8169_update_counters(tp);
1847 tp->tc_offset.tx_errors = counters->tx_errors;
1848 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1849 tp->tc_offset.tx_aborted = counters->tx_aborted;
1850 tp->tc_offset.rx_missed = counters->rx_missed;
1851 }
1852
1853 tp->tc_offset.inited = true;
1854 }
1855
rtl8169_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)1856 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1857 struct ethtool_stats *stats, u64 *data)
1858 {
1859 struct rtl8169_private *tp = netdev_priv(dev);
1860 struct rtl8169_counters *counters;
1861
1862 counters = tp->counters;
1863 rtl8169_update_counters(tp);
1864
1865 data[0] = le64_to_cpu(counters->tx_packets);
1866 data[1] = le64_to_cpu(counters->rx_packets);
1867 data[2] = le64_to_cpu(counters->tx_errors);
1868 data[3] = le32_to_cpu(counters->rx_errors);
1869 data[4] = le16_to_cpu(counters->rx_missed);
1870 data[5] = le16_to_cpu(counters->align_errors);
1871 data[6] = le32_to_cpu(counters->tx_one_collision);
1872 data[7] = le32_to_cpu(counters->tx_multi_collision);
1873 data[8] = le64_to_cpu(counters->rx_unicast);
1874 data[9] = le64_to_cpu(counters->rx_broadcast);
1875 data[10] = le32_to_cpu(counters->rx_multicast);
1876 data[11] = le16_to_cpu(counters->tx_aborted);
1877 data[12] = le16_to_cpu(counters->tx_underrun);
1878 }
1879
rtl8169_get_strings(struct net_device * dev,u32 stringset,u8 * data)1880 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1881 {
1882 switch(stringset) {
1883 case ETH_SS_STATS:
1884 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1885 break;
1886 }
1887 }
1888
1889 /*
1890 * Interrupt coalescing
1891 *
1892 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1893 * > 8169, 8168 and 810x line of chipsets
1894 *
1895 * 8169, 8168, and 8136(810x) serial chipsets support it.
1896 *
1897 * > 2 - the Tx timer unit at gigabit speed
1898 *
1899 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1900 * (0xe0) bit 1 and bit 0.
1901 *
1902 * For 8169
1903 * bit[1:0] \ speed 1000M 100M 10M
1904 * 0 0 320ns 2.56us 40.96us
1905 * 0 1 2.56us 20.48us 327.7us
1906 * 1 0 5.12us 40.96us 655.4us
1907 * 1 1 10.24us 81.92us 1.31ms
1908 *
1909 * For the other
1910 * bit[1:0] \ speed 1000M 100M 10M
1911 * 0 0 5us 2.56us 40.96us
1912 * 0 1 40us 20.48us 327.7us
1913 * 1 0 80us 40.96us 655.4us
1914 * 1 1 160us 81.92us 1.31ms
1915 */
1916
1917 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1918 struct rtl_coalesce_info {
1919 u32 speed;
1920 u32 scale_nsecs[4];
1921 };
1922
1923 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1924 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1925
1926 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1927 { SPEED_1000, COALESCE_DELAY(320) },
1928 { SPEED_100, COALESCE_DELAY(2560) },
1929 { SPEED_10, COALESCE_DELAY(40960) },
1930 { 0 },
1931 };
1932
1933 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1934 { SPEED_1000, COALESCE_DELAY(5000) },
1935 { SPEED_100, COALESCE_DELAY(2560) },
1936 { SPEED_10, COALESCE_DELAY(40960) },
1937 { 0 },
1938 };
1939 #undef COALESCE_DELAY
1940
1941 /* get rx/tx scale vector corresponding to current speed */
1942 static const struct rtl_coalesce_info *
rtl_coalesce_info(struct rtl8169_private * tp)1943 rtl_coalesce_info(struct rtl8169_private *tp)
1944 {
1945 const struct rtl_coalesce_info *ci;
1946
1947 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1948 ci = rtl_coalesce_info_8169;
1949 else
1950 ci = rtl_coalesce_info_8168_8136;
1951
1952 /* if speed is unknown assume highest one */
1953 if (tp->phydev->speed == SPEED_UNKNOWN)
1954 return ci;
1955
1956 for (; ci->speed; ci++) {
1957 if (tp->phydev->speed == ci->speed)
1958 return ci;
1959 }
1960
1961 return ERR_PTR(-ELNRNG);
1962 }
1963
rtl_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)1964 static int rtl_get_coalesce(struct net_device *dev,
1965 struct ethtool_coalesce *ec,
1966 struct kernel_ethtool_coalesce *kernel_coal,
1967 struct netlink_ext_ack *extack)
1968 {
1969 struct rtl8169_private *tp = netdev_priv(dev);
1970 const struct rtl_coalesce_info *ci;
1971 u32 scale, c_us, c_fr;
1972 u16 intrmit;
1973
1974 if (rtl_is_8125(tp))
1975 return -EOPNOTSUPP;
1976
1977 memset(ec, 0, sizeof(*ec));
1978
1979 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1980 ci = rtl_coalesce_info(tp);
1981 if (IS_ERR(ci))
1982 return PTR_ERR(ci);
1983
1984 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1985
1986 intrmit = RTL_R16(tp, IntrMitigate);
1987
1988 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1989 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1990
1991 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1992 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1993 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1994
1995 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1996 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1997
1998 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1999 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
2000
2001 return 0;
2002 }
2003
2004 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
rtl_coalesce_choose_scale(struct rtl8169_private * tp,u32 usec,u16 * cp01)2005 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
2006 u16 *cp01)
2007 {
2008 const struct rtl_coalesce_info *ci;
2009 u16 i;
2010
2011 ci = rtl_coalesce_info(tp);
2012 if (IS_ERR(ci))
2013 return PTR_ERR(ci);
2014
2015 for (i = 0; i < 4; i++) {
2016 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
2017 *cp01 = i;
2018 return ci->scale_nsecs[i];
2019 }
2020 }
2021
2022 return -ERANGE;
2023 }
2024
rtl_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)2025 static int rtl_set_coalesce(struct net_device *dev,
2026 struct ethtool_coalesce *ec,
2027 struct kernel_ethtool_coalesce *kernel_coal,
2028 struct netlink_ext_ack *extack)
2029 {
2030 struct rtl8169_private *tp = netdev_priv(dev);
2031 u32 tx_fr = ec->tx_max_coalesced_frames;
2032 u32 rx_fr = ec->rx_max_coalesced_frames;
2033 u32 coal_usec_max, units;
2034 u16 w = 0, cp01 = 0;
2035 int scale;
2036
2037 if (rtl_is_8125(tp))
2038 return -EOPNOTSUPP;
2039
2040 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
2041 return -ERANGE;
2042
2043 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
2044 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
2045 if (scale < 0)
2046 return scale;
2047
2048 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
2049 * not only when usecs=0 because of e.g. the following scenario:
2050 *
2051 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2052 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2053 * - then user does `ethtool -C eth0 rx-usecs 100`
2054 *
2055 * Since ethtool sends to kernel whole ethtool_coalesce settings,
2056 * if we want to ignore rx_frames then it has to be set to 0.
2057 */
2058 if (rx_fr == 1)
2059 rx_fr = 0;
2060 if (tx_fr == 1)
2061 tx_fr = 0;
2062
2063 /* HW requires time limit to be set if frame limit is set */
2064 if ((tx_fr && !ec->tx_coalesce_usecs) ||
2065 (rx_fr && !ec->rx_coalesce_usecs))
2066 return -EINVAL;
2067
2068 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
2069 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
2070
2071 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
2072 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
2073 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
2074 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
2075
2076 RTL_W16(tp, IntrMitigate, w);
2077
2078 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
2079 if (rtl_is_8168evl_up(tp)) {
2080 if (!rx_fr && !tx_fr)
2081 /* disable packet counter */
2082 tp->cp_cmd |= PktCntrDisable;
2083 else
2084 tp->cp_cmd &= ~PktCntrDisable;
2085 }
2086
2087 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2088 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2089 rtl_pci_commit(tp);
2090
2091 return 0;
2092 }
2093
rtl_set_eee_txidle_timer(struct rtl8169_private * tp)2094 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp)
2095 {
2096 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20;
2097
2098 switch (tp->mac_version) {
2099 case RTL_GIGA_MAC_VER_46:
2100 case RTL_GIGA_MAC_VER_48:
2101 tp->tx_lpi_timer = timer_val;
2102 r8168_mac_ocp_write(tp, 0xe048, timer_val);
2103 break;
2104 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
2105 tp->tx_lpi_timer = timer_val;
2106 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
2107 break;
2108 default:
2109 break;
2110 }
2111 }
2112
r8169_get_tx_lpi_timer_us(struct rtl8169_private * tp)2113 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp)
2114 {
2115 unsigned int speed = tp->phydev->speed;
2116 unsigned int timer = tp->tx_lpi_timer;
2117
2118 if (!timer || speed == SPEED_UNKNOWN)
2119 return 0;
2120
2121 /* tx_lpi_timer value is in bytes */
2122 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed);
2123 }
2124
rtl8169_get_eee(struct net_device * dev,struct ethtool_keee * data)2125 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data)
2126 {
2127 struct rtl8169_private *tp = netdev_priv(dev);
2128 int ret;
2129
2130 if (!rtl_supports_eee(tp))
2131 return -EOPNOTSUPP;
2132
2133 ret = phy_ethtool_get_eee(tp->phydev, data);
2134 if (ret)
2135 return ret;
2136
2137 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp);
2138
2139 return 0;
2140 }
2141
rtl8169_set_eee(struct net_device * dev,struct ethtool_keee * data)2142 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data)
2143 {
2144 struct rtl8169_private *tp = netdev_priv(dev);
2145
2146 if (!rtl_supports_eee(tp))
2147 return -EOPNOTSUPP;
2148
2149 return phy_ethtool_set_eee(tp->phydev, data);
2150 }
2151
rtl8169_get_ringparam(struct net_device * dev,struct ethtool_ringparam * data,struct kernel_ethtool_ringparam * kernel_data,struct netlink_ext_ack * extack)2152 static void rtl8169_get_ringparam(struct net_device *dev,
2153 struct ethtool_ringparam *data,
2154 struct kernel_ethtool_ringparam *kernel_data,
2155 struct netlink_ext_ack *extack)
2156 {
2157 data->rx_max_pending = NUM_RX_DESC;
2158 data->rx_pending = NUM_RX_DESC;
2159 data->tx_max_pending = NUM_TX_DESC;
2160 data->tx_pending = NUM_TX_DESC;
2161 }
2162
rtl8169_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * data)2163 static void rtl8169_get_pauseparam(struct net_device *dev,
2164 struct ethtool_pauseparam *data)
2165 {
2166 struct rtl8169_private *tp = netdev_priv(dev);
2167 bool tx_pause, rx_pause;
2168
2169 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
2170
2171 data->autoneg = tp->phydev->autoneg;
2172 data->tx_pause = tx_pause ? 1 : 0;
2173 data->rx_pause = rx_pause ? 1 : 0;
2174 }
2175
rtl8169_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * data)2176 static int rtl8169_set_pauseparam(struct net_device *dev,
2177 struct ethtool_pauseparam *data)
2178 {
2179 struct rtl8169_private *tp = netdev_priv(dev);
2180
2181 if (dev->mtu > ETH_DATA_LEN)
2182 return -EOPNOTSUPP;
2183
2184 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
2185
2186 return 0;
2187 }
2188
2189 static const struct ethtool_ops rtl8169_ethtool_ops = {
2190 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2191 ETHTOOL_COALESCE_MAX_FRAMES,
2192 .get_drvinfo = rtl8169_get_drvinfo,
2193 .get_regs_len = rtl8169_get_regs_len,
2194 .get_link = ethtool_op_get_link,
2195 .get_coalesce = rtl_get_coalesce,
2196 .set_coalesce = rtl_set_coalesce,
2197 .get_regs = rtl8169_get_regs,
2198 .get_wol = rtl8169_get_wol,
2199 .set_wol = rtl8169_set_wol,
2200 .get_strings = rtl8169_get_strings,
2201 .get_sset_count = rtl8169_get_sset_count,
2202 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2203 .get_ts_info = ethtool_op_get_ts_info,
2204 .nway_reset = phy_ethtool_nway_reset,
2205 .get_eee = rtl8169_get_eee,
2206 .set_eee = rtl8169_set_eee,
2207 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2208 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2209 .get_ringparam = rtl8169_get_ringparam,
2210 .get_pauseparam = rtl8169_get_pauseparam,
2211 .set_pauseparam = rtl8169_set_pauseparam,
2212 };
2213
rtl8169_get_mac_version(u16 xid,bool gmii)2214 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
2215 {
2216 /*
2217 * The driver currently handles the 8168Bf and the 8168Be identically
2218 * but they can be identified more specifically through the test below
2219 * if needed:
2220 *
2221 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2222 *
2223 * Same thing for the 8101Eb and the 8101Ec:
2224 *
2225 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2226 */
2227 static const struct rtl_mac_info {
2228 u16 mask;
2229 u16 val;
2230 enum mac_version ver;
2231 } mac_info[] = {
2232 /* 8126A family. */
2233 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 },
2234 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 },
2235
2236 /* 8125D family. */
2237 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 },
2238
2239 /* 8125B family. */
2240 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2241
2242 /* 8125A family. */
2243 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 },
2244 /* It seems only XID 609 made it to the mass market.
2245 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2246 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2247 */
2248
2249 /* RTL8117 */
2250 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2251 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2252
2253 /* 8168EP family. */
2254 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2255 /* It seems this chip version never made it to
2256 * the wild. Let's disable detection.
2257 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2258 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2259 */
2260
2261 /* 8168H family. */
2262 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2263 /* It seems this chip version never made it to
2264 * the wild. Let's disable detection.
2265 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2266 */
2267 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */
2268 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 },
2269
2270 /* 8168G family. */
2271 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2272 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2273 /* It seems this chip version never made it to
2274 * the wild. Let's disable detection.
2275 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2276 */
2277 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2278
2279 /* 8168F family. */
2280 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2281 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2282 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2283
2284 /* 8168E family. */
2285 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2286 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2287 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2288
2289 /* 8168D family. */
2290 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2291 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2292
2293 /* 8168DP family. */
2294 /* It seems this early RTL8168dp version never made it to
2295 * the wild. Support has been removed.
2296 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2297 */
2298 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2299 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2300
2301 /* 8168C family. */
2302 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2303 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2304 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2305 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2306 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2307 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2308 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2309
2310 /* 8168B family. */
2311 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2312 /* This one is very old and rare, let's see if anybody complains.
2313 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2314 */
2315
2316 /* 8101 family. */
2317 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2318 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2319 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2320 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2321 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2322 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2323 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2324 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2325 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2326 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2327 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2328 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 },
2329
2330 /* 8110 family. */
2331 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2332 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2333 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2334 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2335 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2336
2337 /* Catch-all */
2338 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2339 };
2340 const struct rtl_mac_info *p = mac_info;
2341 enum mac_version ver;
2342
2343 while ((xid & p->mask) != p->val)
2344 p++;
2345 ver = p->ver;
2346
2347 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2348 if (ver == RTL_GIGA_MAC_VER_42)
2349 ver = RTL_GIGA_MAC_VER_43;
2350 else if (ver == RTL_GIGA_MAC_VER_46)
2351 ver = RTL_GIGA_MAC_VER_48;
2352 }
2353
2354 return ver;
2355 }
2356
rtl_release_firmware(struct rtl8169_private * tp)2357 static void rtl_release_firmware(struct rtl8169_private *tp)
2358 {
2359 if (tp->rtl_fw) {
2360 rtl_fw_release_firmware(tp->rtl_fw);
2361 kfree(tp->rtl_fw);
2362 tp->rtl_fw = NULL;
2363 }
2364 }
2365
r8169_apply_firmware(struct rtl8169_private * tp)2366 void r8169_apply_firmware(struct rtl8169_private *tp)
2367 {
2368 int val;
2369
2370 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2371 if (tp->rtl_fw) {
2372 rtl_fw_write_firmware(tp, tp->rtl_fw);
2373 /* At least one firmware doesn't reset tp->ocp_base. */
2374 tp->ocp_base = OCP_STD_PHY_BASE;
2375
2376 /* PHY soft reset may still be in progress */
2377 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2378 !(val & BMCR_RESET),
2379 50000, 600000, true);
2380 }
2381 }
2382
rtl8168_config_eee_mac(struct rtl8169_private * tp)2383 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2384 {
2385 /* Adjust EEE LED frequency */
2386 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2387 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2388
2389 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2390 }
2391
rtl8125a_config_eee_mac(struct rtl8169_private * tp)2392 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2393 {
2394 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2395 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2396 }
2397
rtl8125b_config_eee_mac(struct rtl8169_private * tp)2398 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2399 {
2400 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2401 }
2402
rtl_rar_exgmac_set(struct rtl8169_private * tp,const u8 * addr)2403 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2404 {
2405 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2406 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2407 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2408 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2409 }
2410
rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private * tp)2411 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2412 {
2413 u16 data1, data2, ioffset;
2414
2415 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2416 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2417 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2418
2419 ioffset = (data2 >> 1) & 0x7ff8;
2420 ioffset |= data2 & 0x0007;
2421 if (data1 & BIT(7))
2422 ioffset |= BIT(15);
2423
2424 return ioffset;
2425 }
2426
rtl_schedule_task(struct rtl8169_private * tp,enum rtl_flag flag)2427 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2428 {
2429 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
2430 return;
2431
2432 set_bit(flag, tp->wk.flags);
2433 schedule_work(&tp->wk.work);
2434 }
2435
rtl8169_init_phy(struct rtl8169_private * tp)2436 static void rtl8169_init_phy(struct rtl8169_private *tp)
2437 {
2438 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2439
2440 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2441 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2442 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2443 /* set undocumented MAC Reg C+CR Offset 0x82h */
2444 RTL_W8(tp, 0x82, 0x01);
2445 }
2446
2447 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2448 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2449 tp->pci_dev->subsystem_device == 0xe000)
2450 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2451
2452 /* We may have called phy_speed_down before */
2453 phy_speed_up(tp->phydev);
2454
2455 genphy_soft_reset(tp->phydev);
2456 }
2457
rtl_rar_set(struct rtl8169_private * tp,const u8 * addr)2458 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2459 {
2460 rtl_unlock_config_regs(tp);
2461
2462 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2463 rtl_pci_commit(tp);
2464
2465 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2466 rtl_pci_commit(tp);
2467
2468 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2469 rtl_rar_exgmac_set(tp, addr);
2470
2471 rtl_lock_config_regs(tp);
2472 }
2473
rtl_set_mac_address(struct net_device * dev,void * p)2474 static int rtl_set_mac_address(struct net_device *dev, void *p)
2475 {
2476 struct rtl8169_private *tp = netdev_priv(dev);
2477 int ret;
2478
2479 ret = eth_mac_addr(dev, p);
2480 if (ret)
2481 return ret;
2482
2483 rtl_rar_set(tp, dev->dev_addr);
2484
2485 return 0;
2486 }
2487
rtl_init_rxcfg(struct rtl8169_private * tp)2488 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2489 {
2490 switch (tp->mac_version) {
2491 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2492 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2493 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2494 break;
2495 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2496 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2497 case RTL_GIGA_MAC_VER_38:
2498 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2499 break;
2500 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2501 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2502 break;
2503 case RTL_GIGA_MAC_VER_61:
2504 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2505 break;
2506 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66:
2507 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2508 RX_PAUSE_SLOT_ON);
2509 break;
2510 default:
2511 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2512 break;
2513 }
2514 }
2515
rtl8169_init_ring_indexes(struct rtl8169_private * tp)2516 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2517 {
2518 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2519 }
2520
r8168c_hw_jumbo_enable(struct rtl8169_private * tp)2521 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2522 {
2523 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2524 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2525 }
2526
r8168c_hw_jumbo_disable(struct rtl8169_private * tp)2527 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2528 {
2529 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2530 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2531 }
2532
r8168dp_hw_jumbo_enable(struct rtl8169_private * tp)2533 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2534 {
2535 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2536 }
2537
r8168dp_hw_jumbo_disable(struct rtl8169_private * tp)2538 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2539 {
2540 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2541 }
2542
r8168e_hw_jumbo_enable(struct rtl8169_private * tp)2543 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2544 {
2545 RTL_W8(tp, MaxTxPacketSize, 0x24);
2546 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2547 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2548 }
2549
r8168e_hw_jumbo_disable(struct rtl8169_private * tp)2550 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2551 {
2552 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2553 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2554 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2555 }
2556
r8168b_1_hw_jumbo_enable(struct rtl8169_private * tp)2557 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2558 {
2559 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2560 }
2561
r8168b_1_hw_jumbo_disable(struct rtl8169_private * tp)2562 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2563 {
2564 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2565 }
2566
rtl_jumbo_config(struct rtl8169_private * tp)2567 static void rtl_jumbo_config(struct rtl8169_private *tp)
2568 {
2569 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2570 int readrq = 4096;
2571
2572 rtl_unlock_config_regs(tp);
2573 switch (tp->mac_version) {
2574 case RTL_GIGA_MAC_VER_17:
2575 if (jumbo) {
2576 readrq = 512;
2577 r8168b_1_hw_jumbo_enable(tp);
2578 } else {
2579 r8168b_1_hw_jumbo_disable(tp);
2580 }
2581 break;
2582 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2583 if (jumbo) {
2584 readrq = 512;
2585 r8168c_hw_jumbo_enable(tp);
2586 } else {
2587 r8168c_hw_jumbo_disable(tp);
2588 }
2589 break;
2590 case RTL_GIGA_MAC_VER_28:
2591 if (jumbo)
2592 r8168dp_hw_jumbo_enable(tp);
2593 else
2594 r8168dp_hw_jumbo_disable(tp);
2595 break;
2596 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2597 if (jumbo)
2598 r8168e_hw_jumbo_enable(tp);
2599 else
2600 r8168e_hw_jumbo_disable(tp);
2601 break;
2602 default:
2603 break;
2604 }
2605 rtl_lock_config_regs(tp);
2606
2607 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2608 pcie_set_readrq(tp->pci_dev, readrq);
2609
2610 /* Chip doesn't support pause in jumbo mode */
2611 if (jumbo) {
2612 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2613 tp->phydev->advertising);
2614 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2615 tp->phydev->advertising);
2616 phy_start_aneg(tp->phydev);
2617 }
2618 }
2619
DECLARE_RTL_COND(rtl_chipcmd_cond)2620 DECLARE_RTL_COND(rtl_chipcmd_cond)
2621 {
2622 return RTL_R8(tp, ChipCmd) & CmdReset;
2623 }
2624
rtl_hw_reset(struct rtl8169_private * tp)2625 static void rtl_hw_reset(struct rtl8169_private *tp)
2626 {
2627 RTL_W8(tp, ChipCmd, CmdReset);
2628
2629 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2630 }
2631
rtl_request_firmware(struct rtl8169_private * tp)2632 static void rtl_request_firmware(struct rtl8169_private *tp)
2633 {
2634 struct rtl_fw *rtl_fw;
2635
2636 /* firmware loaded already or no firmware available */
2637 if (tp->rtl_fw || !tp->fw_name)
2638 return;
2639
2640 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2641 if (!rtl_fw)
2642 return;
2643
2644 rtl_fw->phy_write = rtl_writephy;
2645 rtl_fw->phy_read = rtl_readphy;
2646 rtl_fw->mac_mcu_write = mac_mcu_write;
2647 rtl_fw->mac_mcu_read = mac_mcu_read;
2648 rtl_fw->fw_name = tp->fw_name;
2649 rtl_fw->dev = tp_to_dev(tp);
2650
2651 if (rtl_fw_request_firmware(rtl_fw))
2652 kfree(rtl_fw);
2653 else
2654 tp->rtl_fw = rtl_fw;
2655 }
2656
rtl_rx_close(struct rtl8169_private * tp)2657 static void rtl_rx_close(struct rtl8169_private *tp)
2658 {
2659 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2660 }
2661
DECLARE_RTL_COND(rtl_npq_cond)2662 DECLARE_RTL_COND(rtl_npq_cond)
2663 {
2664 return RTL_R8(tp, TxPoll) & NPQ;
2665 }
2666
DECLARE_RTL_COND(rtl_txcfg_empty_cond)2667 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2668 {
2669 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2670 }
2671
DECLARE_RTL_COND(rtl_rxtx_empty_cond)2672 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2673 {
2674 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2675 }
2676
DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)2677 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2678 {
2679 /* IntrMitigate has new functionality on RTL8125 */
2680 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2681 }
2682
rtl_wait_txrx_fifo_empty(struct rtl8169_private * tp)2683 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2684 {
2685 switch (tp->mac_version) {
2686 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2687 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2688 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2689 break;
2690 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2691 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2692 break;
2693 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66:
2694 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2695 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2696 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2697 break;
2698 default:
2699 break;
2700 }
2701 }
2702
rtl_disable_rxdvgate(struct rtl8169_private * tp)2703 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2704 {
2705 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2706 }
2707
rtl_enable_rxdvgate(struct rtl8169_private * tp)2708 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2709 {
2710 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2711 fsleep(2000);
2712 rtl_wait_txrx_fifo_empty(tp);
2713 }
2714
rtl_wol_enable_rx(struct rtl8169_private * tp)2715 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2716 {
2717 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2718 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2719 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2720
2721 if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2722 rtl_disable_rxdvgate(tp);
2723 }
2724
rtl_prepare_power_down(struct rtl8169_private * tp)2725 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2726 {
2727 if (tp->dash_enabled)
2728 return;
2729
2730 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2731 tp->mac_version == RTL_GIGA_MAC_VER_33)
2732 rtl_ephy_write(tp, 0x19, 0xff64);
2733
2734 if (device_may_wakeup(tp_to_dev(tp))) {
2735 phy_speed_down(tp->phydev, false);
2736 rtl_wol_enable_rx(tp);
2737 }
2738 }
2739
rtl_set_tx_config_registers(struct rtl8169_private * tp)2740 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2741 {
2742 u32 val = TX_DMA_BURST << TxDMAShift |
2743 InterFrameGap << TxInterFrameGapShift;
2744
2745 if (rtl_is_8168evl_up(tp))
2746 val |= TXCFG_AUTO_FIFO;
2747
2748 RTL_W32(tp, TxConfig, val);
2749 }
2750
rtl_set_rx_max_size(struct rtl8169_private * tp)2751 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2752 {
2753 /* Low hurts. Let's disable the filtering. */
2754 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2755 }
2756
rtl_set_rx_tx_desc_registers(struct rtl8169_private * tp)2757 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2758 {
2759 /*
2760 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2761 * register to be written before TxDescAddrLow to work.
2762 * Switching from MMIO to I/O access fixes the issue as well.
2763 */
2764 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2765 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2766 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2767 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2768 }
2769
rtl8169_set_magic_reg(struct rtl8169_private * tp)2770 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2771 {
2772 u32 val;
2773
2774 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2775 val = 0x000fff00;
2776 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2777 val = 0x00ffff00;
2778 else
2779 return;
2780
2781 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2782 val |= 0xff;
2783
2784 RTL_W32(tp, 0x7c, val);
2785 }
2786
rtl_set_rx_mode(struct net_device * dev)2787 static void rtl_set_rx_mode(struct net_device *dev)
2788 {
2789 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2790 /* Multicast hash filter */
2791 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2792 struct rtl8169_private *tp = netdev_priv(dev);
2793 u32 tmp;
2794
2795 if (dev->flags & IFF_PROMISC) {
2796 rx_mode |= AcceptAllPhys;
2797 } else if (!(dev->flags & IFF_MULTICAST)) {
2798 rx_mode &= ~AcceptMulticast;
2799 } else if (dev->flags & IFF_ALLMULTI ||
2800 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2801 /* accept all multicasts */
2802 } else if (netdev_mc_empty(dev)) {
2803 rx_mode &= ~AcceptMulticast;
2804 } else {
2805 struct netdev_hw_addr *ha;
2806
2807 mc_filter[1] = mc_filter[0] = 0;
2808 netdev_for_each_mc_addr(ha, dev) {
2809 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2810 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2811 }
2812
2813 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2814 tmp = mc_filter[0];
2815 mc_filter[0] = swab32(mc_filter[1]);
2816 mc_filter[1] = swab32(tmp);
2817 }
2818 }
2819
2820 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2821 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2822
2823 tmp = RTL_R32(tp, RxConfig);
2824 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2825 }
2826
DECLARE_RTL_COND(rtl_csiar_cond)2827 DECLARE_RTL_COND(rtl_csiar_cond)
2828 {
2829 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2830 }
2831
rtl_csi_write(struct rtl8169_private * tp,int addr,int value)2832 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2833 {
2834 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2835
2836 RTL_W32(tp, CSIDR, value);
2837 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2838 CSIAR_BYTE_ENABLE | func << 16);
2839
2840 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2841 }
2842
rtl_csi_read(struct rtl8169_private * tp,int addr)2843 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2844 {
2845 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2846
2847 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2848 CSIAR_BYTE_ENABLE);
2849
2850 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2851 RTL_R32(tp, CSIDR) : ~0;
2852 }
2853
rtl_disable_zrxdc_timeout(struct rtl8169_private * tp)2854 static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp)
2855 {
2856 struct pci_dev *pdev = tp->pci_dev;
2857 u32 csi;
2858 int rc;
2859 u8 val;
2860
2861 #define RTL_GEN3_RELATED_OFF 0x0890
2862 #define RTL_GEN3_ZRXDC_NONCOMPL 0x1
2863 if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) {
2864 rc = pci_read_config_byte(pdev, RTL_GEN3_RELATED_OFF, &val);
2865 if (rc == PCIBIOS_SUCCESSFUL) {
2866 val &= ~RTL_GEN3_ZRXDC_NONCOMPL;
2867 rc = pci_write_config_byte(pdev, RTL_GEN3_RELATED_OFF,
2868 val);
2869 if (rc == PCIBIOS_SUCCESSFUL)
2870 return;
2871 }
2872 }
2873
2874 netdev_notice_once(tp->dev,
2875 "No native access to PCI extended config space, falling back to CSI\n");
2876 csi = rtl_csi_read(tp, RTL_GEN3_RELATED_OFF);
2877 rtl_csi_write(tp, RTL_GEN3_RELATED_OFF, csi & ~RTL_GEN3_ZRXDC_NONCOMPL);
2878 }
2879
rtl_set_aspm_entry_latency(struct rtl8169_private * tp,u8 val)2880 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2881 {
2882 struct pci_dev *pdev = tp->pci_dev;
2883 u32 csi;
2884
2885 /* According to Realtek the value at config space address 0x070f
2886 * controls the L0s/L1 entrance latency. We try standard ECAM access
2887 * first and if it fails fall back to CSI.
2888 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2889 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2890 */
2891 if (pdev->cfg_size > 0x070f &&
2892 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2893 return;
2894
2895 netdev_notice_once(tp->dev,
2896 "No native access to PCI extended config space, falling back to CSI\n");
2897 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2898 rtl_csi_write(tp, 0x070c, csi | val << 24);
2899 }
2900
rtl_set_def_aspm_entry_latency(struct rtl8169_private * tp)2901 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2902 {
2903 /* L0 7us, L1 16us */
2904 rtl_set_aspm_entry_latency(tp, 0x27);
2905 }
2906
2907 struct ephy_info {
2908 unsigned int offset;
2909 u16 mask;
2910 u16 bits;
2911 };
2912
__rtl_ephy_init(struct rtl8169_private * tp,const struct ephy_info * e,int len)2913 static void __rtl_ephy_init(struct rtl8169_private *tp,
2914 const struct ephy_info *e, int len)
2915 {
2916 u16 w;
2917
2918 while (len-- > 0) {
2919 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2920 rtl_ephy_write(tp, e->offset, w);
2921 e++;
2922 }
2923 }
2924
2925 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2926
rtl_disable_clock_request(struct rtl8169_private * tp)2927 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2928 {
2929 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2930 PCI_EXP_LNKCTL_CLKREQ_EN);
2931 }
2932
rtl_enable_clock_request(struct rtl8169_private * tp)2933 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2934 {
2935 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2936 PCI_EXP_LNKCTL_CLKREQ_EN);
2937 }
2938
rtl_pcie_state_l2l3_disable(struct rtl8169_private * tp)2939 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2940 {
2941 /* work around an issue when PCI reset occurs during L2/L3 state */
2942 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2943 }
2944
rtl_enable_exit_l1(struct rtl8169_private * tp)2945 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2946 {
2947 /* Bits control which events trigger ASPM L1 exit:
2948 * Bit 12: rxdv
2949 * Bit 11: ltr_msg
2950 * Bit 10: txdma_poll
2951 * Bit 9: xadm
2952 * Bit 8: pktavi
2953 * Bit 7: txpla
2954 */
2955 switch (tp->mac_version) {
2956 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2957 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2958 break;
2959 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2960 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2961 break;
2962 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:
2963 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2964 break;
2965 default:
2966 break;
2967 }
2968 }
2969
rtl_disable_exit_l1(struct rtl8169_private * tp)2970 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2971 {
2972 switch (tp->mac_version) {
2973 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2974 rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2975 break;
2976 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:
2977 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2978 break;
2979 default:
2980 break;
2981 }
2982 }
2983
rtl_hw_aspm_clkreq_enable(struct rtl8169_private * tp,bool enable)2984 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2985 {
2986 u8 val8;
2987
2988 if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2989 return;
2990
2991 /* Don't enable ASPM in the chip if OS can't control ASPM */
2992 if (enable && tp->aspm_manageable) {
2993 /* On these chip versions ASPM can even harm
2994 * bus communication of other PCI devices.
2995 */
2996 if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2997 tp->mac_version == RTL_GIGA_MAC_VER_43)
2998 return;
2999
3000 rtl_mod_config5(tp, 0, ASPM_en);
3001 switch (tp->mac_version) {
3002 case RTL_GIGA_MAC_VER_65:
3003 case RTL_GIGA_MAC_VER_66:
3004 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;
3005 RTL_W8(tp, INT_CFG0_8125, val8);
3006 break;
3007 default:
3008 rtl_mod_config2(tp, 0, ClkReqEn);
3009 break;
3010 }
3011
3012 switch (tp->mac_version) {
3013 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
3014 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
3015 /* reset ephy tx/rx disable timer */
3016 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
3017 /* chip can trigger L1.2 */
3018 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
3019 break;
3020 default:
3021 break;
3022 }
3023 } else {
3024 switch (tp->mac_version) {
3025 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
3026 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
3027 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
3028 break;
3029 default:
3030 break;
3031 }
3032
3033 switch (tp->mac_version) {
3034 case RTL_GIGA_MAC_VER_65:
3035 case RTL_GIGA_MAC_VER_66:
3036 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;
3037 RTL_W8(tp, INT_CFG0_8125, val8);
3038 break;
3039 default:
3040 rtl_mod_config2(tp, ClkReqEn, 0);
3041 break;
3042 }
3043 rtl_mod_config5(tp, ASPM_en, 0);
3044 }
3045 }
3046
rtl_set_fifo_size(struct rtl8169_private * tp,u16 rx_stat,u16 tx_stat,u16 rx_dyn,u16 tx_dyn)3047 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
3048 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
3049 {
3050 /* Usage of dynamic vs. static FIFO is controlled by bit
3051 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
3052 */
3053 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
3054 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
3055 }
3056
rtl8168g_set_pause_thresholds(struct rtl8169_private * tp,u8 low,u8 high)3057 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
3058 u8 low, u8 high)
3059 {
3060 /* FIFO thresholds for pause flow control */
3061 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
3062 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
3063 }
3064
rtl_hw_start_8168b(struct rtl8169_private * tp)3065 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
3066 {
3067 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3068 }
3069
__rtl_hw_start_8168cp(struct rtl8169_private * tp)3070 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
3071 {
3072 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
3073
3074 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3075
3076 rtl_disable_clock_request(tp);
3077 }
3078
rtl_hw_start_8168cp_1(struct rtl8169_private * tp)3079 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
3080 {
3081 static const struct ephy_info e_info_8168cp[] = {
3082 { 0x01, 0, 0x0001 },
3083 { 0x02, 0x0800, 0x1000 },
3084 { 0x03, 0, 0x0042 },
3085 { 0x06, 0x0080, 0x0000 },
3086 { 0x07, 0, 0x2000 }
3087 };
3088
3089 rtl_set_def_aspm_entry_latency(tp);
3090
3091 rtl_ephy_init(tp, e_info_8168cp);
3092
3093 __rtl_hw_start_8168cp(tp);
3094 }
3095
rtl_hw_start_8168cp_2(struct rtl8169_private * tp)3096 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
3097 {
3098 rtl_set_def_aspm_entry_latency(tp);
3099
3100 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3101 }
3102
rtl_hw_start_8168cp_3(struct rtl8169_private * tp)3103 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
3104 {
3105 rtl_set_def_aspm_entry_latency(tp);
3106
3107 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3108
3109 /* Magic. */
3110 RTL_W8(tp, DBG_REG, 0x20);
3111 }
3112
rtl_hw_start_8168c_1(struct rtl8169_private * tp)3113 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
3114 {
3115 static const struct ephy_info e_info_8168c_1[] = {
3116 { 0x02, 0x0800, 0x1000 },
3117 { 0x03, 0, 0x0002 },
3118 { 0x06, 0x0080, 0x0000 }
3119 };
3120
3121 rtl_set_def_aspm_entry_latency(tp);
3122
3123 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3124
3125 rtl_ephy_init(tp, e_info_8168c_1);
3126
3127 __rtl_hw_start_8168cp(tp);
3128 }
3129
rtl_hw_start_8168c_2(struct rtl8169_private * tp)3130 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
3131 {
3132 static const struct ephy_info e_info_8168c_2[] = {
3133 { 0x01, 0, 0x0001 },
3134 { 0x03, 0x0400, 0x0020 }
3135 };
3136
3137 rtl_set_def_aspm_entry_latency(tp);
3138
3139 rtl_ephy_init(tp, e_info_8168c_2);
3140
3141 __rtl_hw_start_8168cp(tp);
3142 }
3143
rtl_hw_start_8168c_4(struct rtl8169_private * tp)3144 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
3145 {
3146 rtl_set_def_aspm_entry_latency(tp);
3147
3148 __rtl_hw_start_8168cp(tp);
3149 }
3150
rtl_hw_start_8168d(struct rtl8169_private * tp)3151 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
3152 {
3153 rtl_set_def_aspm_entry_latency(tp);
3154
3155 rtl_disable_clock_request(tp);
3156 }
3157
rtl_hw_start_8168d_4(struct rtl8169_private * tp)3158 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
3159 {
3160 static const struct ephy_info e_info_8168d_4[] = {
3161 { 0x0b, 0x0000, 0x0048 },
3162 { 0x19, 0x0020, 0x0050 },
3163 { 0x0c, 0x0100, 0x0020 },
3164 { 0x10, 0x0004, 0x0000 },
3165 };
3166
3167 rtl_set_def_aspm_entry_latency(tp);
3168
3169 rtl_ephy_init(tp, e_info_8168d_4);
3170
3171 rtl_enable_clock_request(tp);
3172 }
3173
rtl_hw_start_8168e_1(struct rtl8169_private * tp)3174 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
3175 {
3176 static const struct ephy_info e_info_8168e_1[] = {
3177 { 0x00, 0x0200, 0x0100 },
3178 { 0x00, 0x0000, 0x0004 },
3179 { 0x06, 0x0002, 0x0001 },
3180 { 0x06, 0x0000, 0x0030 },
3181 { 0x07, 0x0000, 0x2000 },
3182 { 0x00, 0x0000, 0x0020 },
3183 { 0x03, 0x5800, 0x2000 },
3184 { 0x03, 0x0000, 0x0001 },
3185 { 0x01, 0x0800, 0x1000 },
3186 { 0x07, 0x0000, 0x4000 },
3187 { 0x1e, 0x0000, 0x2000 },
3188 { 0x19, 0xffff, 0xfe6c },
3189 { 0x0a, 0x0000, 0x0040 }
3190 };
3191
3192 rtl_set_def_aspm_entry_latency(tp);
3193
3194 rtl_ephy_init(tp, e_info_8168e_1);
3195
3196 rtl_disable_clock_request(tp);
3197
3198 /* Reset tx FIFO pointer */
3199 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
3200 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
3201
3202 rtl_mod_config5(tp, Spi_en, 0);
3203 }
3204
rtl_hw_start_8168e_2(struct rtl8169_private * tp)3205 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
3206 {
3207 static const struct ephy_info e_info_8168e_2[] = {
3208 { 0x09, 0x0000, 0x0080 },
3209 { 0x19, 0x0000, 0x0224 },
3210 { 0x00, 0x0000, 0x0004 },
3211 { 0x0c, 0x3df0, 0x0200 },
3212 };
3213
3214 rtl_set_def_aspm_entry_latency(tp);
3215
3216 rtl_ephy_init(tp, e_info_8168e_2);
3217
3218 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3219 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3220 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3221 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
3222 rtl_reset_packet_filter(tp);
3223 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3224 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3225 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
3226
3227 rtl_disable_clock_request(tp);
3228
3229 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3230
3231 rtl8168_config_eee_mac(tp);
3232
3233 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3234 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3235 rtl_mod_config5(tp, Spi_en, 0);
3236 }
3237
rtl_hw_start_8168f(struct rtl8169_private * tp)3238 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
3239 {
3240 rtl_set_def_aspm_entry_latency(tp);
3241
3242 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3243 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3244 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3245 rtl_reset_packet_filter(tp);
3246 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3247 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
3248 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3249 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
3250
3251 rtl_disable_clock_request(tp);
3252
3253 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3254 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3255 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3256 rtl_mod_config5(tp, Spi_en, 0);
3257
3258 rtl8168_config_eee_mac(tp);
3259 }
3260
rtl_hw_start_8168f_1(struct rtl8169_private * tp)3261 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3262 {
3263 static const struct ephy_info e_info_8168f_1[] = {
3264 { 0x06, 0x00c0, 0x0020 },
3265 { 0x08, 0x0001, 0x0002 },
3266 { 0x09, 0x0000, 0x0080 },
3267 { 0x19, 0x0000, 0x0224 },
3268 { 0x00, 0x0000, 0x0008 },
3269 { 0x0c, 0x3df0, 0x0200 },
3270 };
3271
3272 rtl_hw_start_8168f(tp);
3273
3274 rtl_ephy_init(tp, e_info_8168f_1);
3275 }
3276
rtl_hw_start_8411(struct rtl8169_private * tp)3277 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3278 {
3279 static const struct ephy_info e_info_8168f_1[] = {
3280 { 0x06, 0x00c0, 0x0020 },
3281 { 0x0f, 0xffff, 0x5200 },
3282 { 0x19, 0x0000, 0x0224 },
3283 { 0x00, 0x0000, 0x0008 },
3284 { 0x0c, 0x3df0, 0x0200 },
3285 };
3286
3287 rtl_hw_start_8168f(tp);
3288 rtl_pcie_state_l2l3_disable(tp);
3289
3290 rtl_ephy_init(tp, e_info_8168f_1);
3291 }
3292
rtl_hw_start_8168g(struct rtl8169_private * tp)3293 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3294 {
3295 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3296 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3297
3298 rtl_set_def_aspm_entry_latency(tp);
3299
3300 rtl_reset_packet_filter(tp);
3301 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3302
3303 rtl_disable_rxdvgate(tp);
3304
3305 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3306 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3307
3308 rtl8168_config_eee_mac(tp);
3309
3310 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3311 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3312
3313 rtl_pcie_state_l2l3_disable(tp);
3314 }
3315
rtl_hw_start_8168g_1(struct rtl8169_private * tp)3316 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3317 {
3318 static const struct ephy_info e_info_8168g_1[] = {
3319 { 0x00, 0x0008, 0x0000 },
3320 { 0x0c, 0x3ff0, 0x0820 },
3321 { 0x1e, 0x0000, 0x0001 },
3322 { 0x19, 0x8000, 0x0000 }
3323 };
3324
3325 rtl_hw_start_8168g(tp);
3326 rtl_ephy_init(tp, e_info_8168g_1);
3327 }
3328
rtl_hw_start_8168g_2(struct rtl8169_private * tp)3329 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3330 {
3331 static const struct ephy_info e_info_8168g_2[] = {
3332 { 0x00, 0x0008, 0x0000 },
3333 { 0x0c, 0x3ff0, 0x0820 },
3334 { 0x19, 0xffff, 0x7c00 },
3335 { 0x1e, 0xffff, 0x20eb },
3336 { 0x0d, 0xffff, 0x1666 },
3337 { 0x00, 0xffff, 0x10a3 },
3338 { 0x06, 0xffff, 0xf050 },
3339 { 0x04, 0x0000, 0x0010 },
3340 { 0x1d, 0x4000, 0x0000 },
3341 };
3342
3343 rtl_hw_start_8168g(tp);
3344 rtl_ephy_init(tp, e_info_8168g_2);
3345 }
3346
rtl8411b_fix_phy_down(struct rtl8169_private * tp)3347 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp)
3348 {
3349 static const u16 fix_data[] = {
3350 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065,
3351 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00,
3352 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009,
3353 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006,
3354 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2,
3355 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400,
3356 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519,
3357 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4,
3358 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508,
3359 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434,
3360 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007,
3361 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00,
3362 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1,
3363 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132
3364 };
3365 unsigned long flags;
3366 int i;
3367
3368 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
3369 for (i = 0; i < ARRAY_SIZE(fix_data); i++)
3370 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]);
3371 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
3372 }
3373
rtl_hw_start_8411_2(struct rtl8169_private * tp)3374 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3375 {
3376 static const struct ephy_info e_info_8411_2[] = {
3377 { 0x00, 0x0008, 0x0000 },
3378 { 0x0c, 0x37d0, 0x0820 },
3379 { 0x1e, 0x0000, 0x0001 },
3380 { 0x19, 0x8021, 0x0000 },
3381 { 0x1e, 0x0000, 0x2000 },
3382 { 0x0d, 0x0100, 0x0200 },
3383 { 0x00, 0x0000, 0x0080 },
3384 { 0x06, 0x0000, 0x0010 },
3385 { 0x04, 0x0000, 0x0010 },
3386 { 0x1d, 0x0000, 0x4000 },
3387 };
3388
3389 rtl_hw_start_8168g(tp);
3390
3391 rtl_ephy_init(tp, e_info_8411_2);
3392
3393 /* The following Realtek-provided magic fixes an issue with the RX unit
3394 * getting confused after the PHY having been powered-down.
3395 */
3396 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3397 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3398 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3399 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3400 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3401 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3402 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3403 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3404 mdelay(3);
3405 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3406
3407 rtl8411b_fix_phy_down(tp);
3408
3409 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3410
3411 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3412 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3413 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3414 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3415 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3416 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3417 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3418 }
3419
rtl_hw_start_8168h_1(struct rtl8169_private * tp)3420 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3421 {
3422 static const struct ephy_info e_info_8168h_1[] = {
3423 { 0x1e, 0x0800, 0x0001 },
3424 { 0x1d, 0x0000, 0x0800 },
3425 { 0x05, 0xffff, 0x2089 },
3426 { 0x06, 0xffff, 0x5881 },
3427 { 0x04, 0xffff, 0x854a },
3428 { 0x01, 0xffff, 0x068b }
3429 };
3430 int rg_saw_cnt;
3431
3432 rtl_ephy_init(tp, e_info_8168h_1);
3433
3434 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3435 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3436
3437 rtl_set_def_aspm_entry_latency(tp);
3438
3439 rtl_reset_packet_filter(tp);
3440
3441 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3442
3443 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3444
3445 rtl_disable_rxdvgate(tp);
3446
3447 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3448 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3449
3450 rtl8168_config_eee_mac(tp);
3451
3452 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3453 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3454
3455 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3456
3457 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3458
3459 rtl_pcie_state_l2l3_disable(tp);
3460
3461 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3462 if (rg_saw_cnt > 0) {
3463 u16 sw_cnt_1ms_ini;
3464
3465 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3466 sw_cnt_1ms_ini &= 0x0fff;
3467 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3468 }
3469
3470 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3471 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3472 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3473 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3474
3475 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3476 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3477 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3478 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3479 }
3480
rtl_hw_start_8168ep(struct rtl8169_private * tp)3481 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3482 {
3483 rtl8168ep_stop_cmac(tp);
3484
3485 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3486 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3487
3488 rtl_set_def_aspm_entry_latency(tp);
3489
3490 rtl_reset_packet_filter(tp);
3491
3492 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3493
3494 rtl_disable_rxdvgate(tp);
3495
3496 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3497 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3498
3499 rtl8168_config_eee_mac(tp);
3500
3501 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3502
3503 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3504
3505 rtl_pcie_state_l2l3_disable(tp);
3506 }
3507
rtl_hw_start_8168ep_3(struct rtl8169_private * tp)3508 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3509 {
3510 static const struct ephy_info e_info_8168ep_3[] = {
3511 { 0x00, 0x0000, 0x0080 },
3512 { 0x0d, 0x0100, 0x0200 },
3513 { 0x19, 0x8021, 0x0000 },
3514 { 0x1e, 0x0000, 0x2000 },
3515 };
3516
3517 rtl_ephy_init(tp, e_info_8168ep_3);
3518
3519 rtl_hw_start_8168ep(tp);
3520
3521 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3522 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3523
3524 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3525 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3526 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3527 }
3528
rtl_hw_start_8117(struct rtl8169_private * tp)3529 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3530 {
3531 static const struct ephy_info e_info_8117[] = {
3532 { 0x19, 0x0040, 0x1100 },
3533 { 0x59, 0x0040, 0x1100 },
3534 };
3535 int rg_saw_cnt;
3536
3537 rtl8168ep_stop_cmac(tp);
3538 rtl_ephy_init(tp, e_info_8117);
3539
3540 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3541 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3542
3543 rtl_set_def_aspm_entry_latency(tp);
3544
3545 rtl_reset_packet_filter(tp);
3546
3547 rtl_eri_set_bits(tp, 0xd4, 0x0010);
3548
3549 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3550
3551 rtl_disable_rxdvgate(tp);
3552
3553 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3554 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3555
3556 rtl8168_config_eee_mac(tp);
3557
3558 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3559 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3560
3561 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3562
3563 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3564
3565 rtl_pcie_state_l2l3_disable(tp);
3566
3567 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3568 if (rg_saw_cnt > 0) {
3569 u16 sw_cnt_1ms_ini;
3570
3571 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3572 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3573 }
3574
3575 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3576 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3577 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3578 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3579
3580 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3581 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3582 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3583 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3584
3585 /* firmware is for MAC only */
3586 r8169_apply_firmware(tp);
3587 }
3588
rtl_hw_start_8102e_1(struct rtl8169_private * tp)3589 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3590 {
3591 static const struct ephy_info e_info_8102e_1[] = {
3592 { 0x01, 0, 0x6e65 },
3593 { 0x02, 0, 0x091f },
3594 { 0x03, 0, 0xc2f9 },
3595 { 0x06, 0, 0xafb5 },
3596 { 0x07, 0, 0x0e00 },
3597 { 0x19, 0, 0xec80 },
3598 { 0x01, 0, 0x2e65 },
3599 { 0x01, 0, 0x6e65 }
3600 };
3601 u8 cfg1;
3602
3603 rtl_set_def_aspm_entry_latency(tp);
3604
3605 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3606
3607 RTL_W8(tp, Config1,
3608 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3609 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3610
3611 cfg1 = RTL_R8(tp, Config1);
3612 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3613 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3614
3615 rtl_ephy_init(tp, e_info_8102e_1);
3616 }
3617
rtl_hw_start_8102e_2(struct rtl8169_private * tp)3618 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3619 {
3620 rtl_set_def_aspm_entry_latency(tp);
3621
3622 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3623 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3624 }
3625
rtl_hw_start_8102e_3(struct rtl8169_private * tp)3626 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3627 {
3628 rtl_hw_start_8102e_2(tp);
3629
3630 rtl_ephy_write(tp, 0x03, 0xc2f9);
3631 }
3632
rtl_hw_start_8401(struct rtl8169_private * tp)3633 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3634 {
3635 static const struct ephy_info e_info_8401[] = {
3636 { 0x01, 0xffff, 0x6fe5 },
3637 { 0x03, 0xffff, 0x0599 },
3638 { 0x06, 0xffff, 0xaf25 },
3639 { 0x07, 0xffff, 0x8e68 },
3640 };
3641
3642 rtl_ephy_init(tp, e_info_8401);
3643 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3644 }
3645
rtl_hw_start_8105e_1(struct rtl8169_private * tp)3646 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3647 {
3648 static const struct ephy_info e_info_8105e_1[] = {
3649 { 0x07, 0, 0x4000 },
3650 { 0x19, 0, 0x0200 },
3651 { 0x19, 0, 0x0020 },
3652 { 0x1e, 0, 0x2000 },
3653 { 0x03, 0, 0x0001 },
3654 { 0x19, 0, 0x0100 },
3655 { 0x19, 0, 0x0004 },
3656 { 0x0a, 0, 0x0020 }
3657 };
3658
3659 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3660 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3661
3662 /* Disable Early Tally Counter */
3663 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3664
3665 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3666 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3667
3668 rtl_ephy_init(tp, e_info_8105e_1);
3669
3670 rtl_pcie_state_l2l3_disable(tp);
3671 }
3672
rtl_hw_start_8105e_2(struct rtl8169_private * tp)3673 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3674 {
3675 rtl_hw_start_8105e_1(tp);
3676 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3677 }
3678
rtl_hw_start_8402(struct rtl8169_private * tp)3679 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3680 {
3681 static const struct ephy_info e_info_8402[] = {
3682 { 0x19, 0xffff, 0xff64 },
3683 { 0x1e, 0, 0x4000 }
3684 };
3685
3686 rtl_set_def_aspm_entry_latency(tp);
3687
3688 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3689 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3690
3691 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3692
3693 rtl_ephy_init(tp, e_info_8402);
3694
3695 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3696 rtl_reset_packet_filter(tp);
3697 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3698 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3699 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3700
3701 /* disable EEE */
3702 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3703
3704 rtl_pcie_state_l2l3_disable(tp);
3705 }
3706
rtl_hw_start_8106(struct rtl8169_private * tp)3707 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3708 {
3709 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3710 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3711
3712 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3713 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3714 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3715
3716 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3717 rtl_set_aspm_entry_latency(tp, 0x2f);
3718
3719 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3720
3721 /* disable EEE */
3722 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3723
3724 rtl_pcie_state_l2l3_disable(tp);
3725 }
3726
DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)3727 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3728 {
3729 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3730 }
3731
rtl_hw_start_8125_common(struct rtl8169_private * tp)3732 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3733 {
3734 rtl_pcie_state_l2l3_disable(tp);
3735
3736 RTL_W16(tp, 0x382, 0x221b);
3737 RTL_W8(tp, 0x4500, 0);
3738 RTL_W16(tp, 0x4800, 0);
3739
3740 /* disable UPS */
3741 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3742
3743 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3744
3745 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3746 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3747
3748 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3749 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3750 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3751
3752 /* disable new tx descriptor format */
3753 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3754
3755 if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||
3756 tp->mac_version == RTL_GIGA_MAC_VER_66)
3757 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);
3758
3759 if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||
3760 tp->mac_version == RTL_GIGA_MAC_VER_66)
3761 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3762 else if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3763 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3764 else
3765 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300);
3766
3767 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3768 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3769 else
3770 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3771
3772 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3773 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3774 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3775 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3776 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3777 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3778 if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||
3779 tp->mac_version == RTL_GIGA_MAC_VER_66)
3780 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000);
3781 else
3782 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3783 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3784 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3785 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3786
3787 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3788 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3789 udelay(1);
3790 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3791 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3792
3793 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3794
3795 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3796
3797 if (tp->mac_version == RTL_GIGA_MAC_VER_61)
3798 rtl8125a_config_eee_mac(tp);
3799 else
3800 rtl8125b_config_eee_mac(tp);
3801
3802 rtl_disable_rxdvgate(tp);
3803 }
3804
rtl_hw_start_8125a_2(struct rtl8169_private * tp)3805 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3806 {
3807 static const struct ephy_info e_info_8125a_2[] = {
3808 { 0x04, 0xffff, 0xd000 },
3809 { 0x0a, 0xffff, 0x8653 },
3810 { 0x23, 0xffff, 0xab66 },
3811 { 0x20, 0xffff, 0x9455 },
3812 { 0x21, 0xffff, 0x99ff },
3813 { 0x29, 0xffff, 0xfe04 },
3814
3815 { 0x44, 0xffff, 0xd000 },
3816 { 0x4a, 0xffff, 0x8653 },
3817 { 0x63, 0xffff, 0xab66 },
3818 { 0x60, 0xffff, 0x9455 },
3819 { 0x61, 0xffff, 0x99ff },
3820 { 0x69, 0xffff, 0xfe04 },
3821 };
3822
3823 rtl_set_def_aspm_entry_latency(tp);
3824 rtl_ephy_init(tp, e_info_8125a_2);
3825 rtl_hw_start_8125_common(tp);
3826 }
3827
rtl_hw_start_8125b(struct rtl8169_private * tp)3828 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3829 {
3830 static const struct ephy_info e_info_8125b[] = {
3831 { 0x0b, 0xffff, 0xa908 },
3832 { 0x1e, 0xffff, 0x20eb },
3833 { 0x4b, 0xffff, 0xa908 },
3834 { 0x5e, 0xffff, 0x20eb },
3835 { 0x22, 0x0030, 0x0020 },
3836 { 0x62, 0x0030, 0x0020 },
3837 };
3838
3839 rtl_set_def_aspm_entry_latency(tp);
3840 rtl_ephy_init(tp, e_info_8125b);
3841 rtl_hw_start_8125_common(tp);
3842 }
3843
rtl_hw_start_8125d(struct rtl8169_private * tp)3844 static void rtl_hw_start_8125d(struct rtl8169_private *tp)
3845 {
3846 rtl_set_def_aspm_entry_latency(tp);
3847 rtl_hw_start_8125_common(tp);
3848 }
3849
rtl_hw_start_8126a(struct rtl8169_private * tp)3850 static void rtl_hw_start_8126a(struct rtl8169_private *tp)
3851 {
3852 rtl_disable_zrxdc_timeout(tp);
3853 rtl_set_def_aspm_entry_latency(tp);
3854 rtl_hw_start_8125_common(tp);
3855 }
3856
rtl_hw_config(struct rtl8169_private * tp)3857 static void rtl_hw_config(struct rtl8169_private *tp)
3858 {
3859 static const rtl_generic_fct hw_configs[] = {
3860 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3861 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3862 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3863 [RTL_GIGA_MAC_VER_10] = NULL,
3864 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3865 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3866 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3867 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3868 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3869 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3870 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3871 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3872 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3873 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3874 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3875 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3876 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3877 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3878 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3879 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3880 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3881 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3882 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3883 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3884 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3885 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3886 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3887 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3888 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3889 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3890 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3891 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3892 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3893 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3894 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3895 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3896 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3897 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3898 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3899 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d,
3900 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a,
3901 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a,
3902 };
3903
3904 if (hw_configs[tp->mac_version])
3905 hw_configs[tp->mac_version](tp);
3906 }
3907
rtl_hw_start_8125(struct rtl8169_private * tp)3908 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3909 {
3910 int i;
3911
3912 RTL_W8(tp, INT_CFG0_8125, 0x00);
3913
3914 /* disable interrupt coalescing */
3915 switch (tp->mac_version) {
3916 case RTL_GIGA_MAC_VER_61:
3917 case RTL_GIGA_MAC_VER_64:
3918 for (i = 0xa00; i < 0xb00; i += 4)
3919 RTL_W32(tp, i, 0);
3920 break;
3921 case RTL_GIGA_MAC_VER_63:
3922 case RTL_GIGA_MAC_VER_65:
3923 case RTL_GIGA_MAC_VER_66:
3924 for (i = 0xa00; i < 0xa80; i += 4)
3925 RTL_W32(tp, i, 0);
3926 RTL_W16(tp, INT_CFG1_8125, 0x0000);
3927 break;
3928 default:
3929 break;
3930 }
3931
3932 rtl_hw_config(tp);
3933 }
3934
rtl_hw_start_8168(struct rtl8169_private * tp)3935 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3936 {
3937 if (rtl_is_8168evl_up(tp))
3938 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3939 else
3940 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3941
3942 rtl_hw_config(tp);
3943
3944 /* disable interrupt coalescing */
3945 RTL_W16(tp, IntrMitigate, 0x0000);
3946 }
3947
rtl_hw_start_8169(struct rtl8169_private * tp)3948 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3949 {
3950 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3951
3952 tp->cp_cmd |= PCIMulRW;
3953
3954 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3955 tp->mac_version == RTL_GIGA_MAC_VER_03)
3956 tp->cp_cmd |= EnAnaPLL;
3957
3958 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3959
3960 rtl8169_set_magic_reg(tp);
3961
3962 /* disable interrupt coalescing */
3963 RTL_W16(tp, IntrMitigate, 0x0000);
3964 }
3965
rtl_hw_start(struct rtl8169_private * tp)3966 static void rtl_hw_start(struct rtl8169_private *tp)
3967 {
3968 rtl_unlock_config_regs(tp);
3969 /* disable aspm and clock request before ephy access */
3970 rtl_hw_aspm_clkreq_enable(tp, false);
3971 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3972
3973 rtl_set_eee_txidle_timer(tp);
3974
3975 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3976 rtl_hw_start_8169(tp);
3977 else if (rtl_is_8125(tp))
3978 rtl_hw_start_8125(tp);
3979 else
3980 rtl_hw_start_8168(tp);
3981
3982 rtl_enable_exit_l1(tp);
3983 rtl_hw_aspm_clkreq_enable(tp, true);
3984 rtl_set_rx_max_size(tp);
3985 rtl_set_rx_tx_desc_registers(tp);
3986 rtl_lock_config_regs(tp);
3987
3988 rtl_jumbo_config(tp);
3989
3990 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3991 rtl_pci_commit(tp);
3992
3993 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3994 rtl_init_rxcfg(tp);
3995 rtl_set_tx_config_registers(tp);
3996 rtl_set_rx_config_features(tp, tp->dev->features);
3997 rtl_set_rx_mode(tp->dev);
3998 rtl_irq_enable(tp);
3999 }
4000
rtl8169_change_mtu(struct net_device * dev,int new_mtu)4001 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4002 {
4003 struct rtl8169_private *tp = netdev_priv(dev);
4004
4005 WRITE_ONCE(dev->mtu, new_mtu);
4006 netdev_update_features(dev);
4007 rtl_jumbo_config(tp);
4008 rtl_set_eee_txidle_timer(tp);
4009
4010 return 0;
4011 }
4012
rtl8169_mark_to_asic(struct RxDesc * desc)4013 static void rtl8169_mark_to_asic(struct RxDesc *desc)
4014 {
4015 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4016
4017 desc->opts2 = 0;
4018 /* Force memory writes to complete before releasing descriptor */
4019 dma_wmb();
4020 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
4021 }
4022
rtl8169_alloc_rx_data(struct rtl8169_private * tp,struct RxDesc * desc)4023 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4024 struct RxDesc *desc)
4025 {
4026 struct device *d = tp_to_dev(tp);
4027 int node = dev_to_node(d);
4028 dma_addr_t mapping;
4029 struct page *data;
4030
4031 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
4032 if (!data)
4033 return NULL;
4034
4035 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
4036 if (unlikely(dma_mapping_error(d, mapping))) {
4037 netdev_err(tp->dev, "Failed to map RX DMA!\n");
4038 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
4039 return NULL;
4040 }
4041
4042 desc->addr = cpu_to_le64(mapping);
4043 rtl8169_mark_to_asic(desc);
4044
4045 return data;
4046 }
4047
rtl8169_rx_clear(struct rtl8169_private * tp)4048 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4049 {
4050 int i;
4051
4052 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
4053 dma_unmap_page(tp_to_dev(tp),
4054 le64_to_cpu(tp->RxDescArray[i].addr),
4055 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
4056 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
4057 tp->Rx_databuff[i] = NULL;
4058 tp->RxDescArray[i].addr = 0;
4059 tp->RxDescArray[i].opts1 = 0;
4060 }
4061 }
4062
rtl8169_rx_fill(struct rtl8169_private * tp)4063 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4064 {
4065 int i;
4066
4067 for (i = 0; i < NUM_RX_DESC; i++) {
4068 struct page *data;
4069
4070 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4071 if (!data) {
4072 rtl8169_rx_clear(tp);
4073 return -ENOMEM;
4074 }
4075 tp->Rx_databuff[i] = data;
4076 }
4077
4078 /* mark as last descriptor in the ring */
4079 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
4080
4081 return 0;
4082 }
4083
rtl8169_init_ring(struct rtl8169_private * tp)4084 static int rtl8169_init_ring(struct rtl8169_private *tp)
4085 {
4086 rtl8169_init_ring_indexes(tp);
4087
4088 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
4089 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
4090
4091 return rtl8169_rx_fill(tp);
4092 }
4093
rtl8169_unmap_tx_skb(struct rtl8169_private * tp,unsigned int entry)4094 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
4095 {
4096 struct ring_info *tx_skb = tp->tx_skb + entry;
4097 struct TxDesc *desc = tp->TxDescArray + entry;
4098
4099 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
4100 DMA_TO_DEVICE);
4101 memset(desc, 0, sizeof(*desc));
4102 memset(tx_skb, 0, sizeof(*tx_skb));
4103 }
4104
rtl8169_tx_clear_range(struct rtl8169_private * tp,u32 start,unsigned int n)4105 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4106 unsigned int n)
4107 {
4108 unsigned int i;
4109
4110 for (i = 0; i < n; i++) {
4111 unsigned int entry = (start + i) % NUM_TX_DESC;
4112 struct ring_info *tx_skb = tp->tx_skb + entry;
4113 unsigned int len = tx_skb->len;
4114
4115 if (len) {
4116 struct sk_buff *skb = tx_skb->skb;
4117
4118 rtl8169_unmap_tx_skb(tp, entry);
4119 if (skb)
4120 dev_consume_skb_any(skb);
4121 }
4122 }
4123 }
4124
rtl8169_tx_clear(struct rtl8169_private * tp)4125 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4126 {
4127 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4128 netdev_reset_queue(tp->dev);
4129 }
4130
rtl8169_cleanup(struct rtl8169_private * tp)4131 static void rtl8169_cleanup(struct rtl8169_private *tp)
4132 {
4133 napi_disable(&tp->napi);
4134
4135 /* Give a racing hard_start_xmit a few cycles to complete. */
4136 synchronize_net();
4137
4138 /* Disable interrupts */
4139 rtl8169_irq_mask_and_ack(tp);
4140
4141 rtl_rx_close(tp);
4142
4143 switch (tp->mac_version) {
4144 case RTL_GIGA_MAC_VER_28:
4145 case RTL_GIGA_MAC_VER_31:
4146 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
4147 break;
4148 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4149 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4150 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4151 break;
4152 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:
4153 rtl_enable_rxdvgate(tp);
4154 fsleep(2000);
4155 break;
4156 default:
4157 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4158 fsleep(100);
4159 break;
4160 }
4161
4162 rtl_hw_reset(tp);
4163
4164 rtl8169_tx_clear(tp);
4165 rtl8169_init_ring_indexes(tp);
4166 }
4167
rtl_reset_work(struct rtl8169_private * tp)4168 static void rtl_reset_work(struct rtl8169_private *tp)
4169 {
4170 int i;
4171
4172 netif_stop_queue(tp->dev);
4173
4174 rtl8169_cleanup(tp);
4175
4176 for (i = 0; i < NUM_RX_DESC; i++)
4177 rtl8169_mark_to_asic(tp->RxDescArray + i);
4178
4179 napi_enable(&tp->napi);
4180 rtl_hw_start(tp);
4181 }
4182
rtl8169_tx_timeout(struct net_device * dev,unsigned int txqueue)4183 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4184 {
4185 struct rtl8169_private *tp = netdev_priv(dev);
4186
4187 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
4188 }
4189
rtl8169_tx_map(struct rtl8169_private * tp,const u32 * opts,u32 len,void * addr,unsigned int entry,bool desc_own)4190 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4191 void *addr, unsigned int entry, bool desc_own)
4192 {
4193 struct TxDesc *txd = tp->TxDescArray + entry;
4194 struct device *d = tp_to_dev(tp);
4195 dma_addr_t mapping;
4196 u32 opts1;
4197 int ret;
4198
4199 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4200 ret = dma_mapping_error(d, mapping);
4201 if (unlikely(ret)) {
4202 if (net_ratelimit())
4203 netdev_err(tp->dev, "Failed to map TX data!\n");
4204 return ret;
4205 }
4206
4207 txd->addr = cpu_to_le64(mapping);
4208 txd->opts2 = cpu_to_le32(opts[1]);
4209
4210 opts1 = opts[0] | len;
4211 if (entry == NUM_TX_DESC - 1)
4212 opts1 |= RingEnd;
4213 if (desc_own)
4214 opts1 |= DescOwn;
4215 txd->opts1 = cpu_to_le32(opts1);
4216
4217 tp->tx_skb[entry].len = len;
4218
4219 return 0;
4220 }
4221
rtl8169_xmit_frags(struct rtl8169_private * tp,struct sk_buff * skb,const u32 * opts,unsigned int entry)4222 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4223 const u32 *opts, unsigned int entry)
4224 {
4225 struct skb_shared_info *info = skb_shinfo(skb);
4226 unsigned int cur_frag;
4227
4228 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4229 const skb_frag_t *frag = info->frags + cur_frag;
4230 void *addr = skb_frag_address(frag);
4231 u32 len = skb_frag_size(frag);
4232
4233 entry = (entry + 1) % NUM_TX_DESC;
4234
4235 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4236 goto err_out;
4237 }
4238
4239 return 0;
4240
4241 err_out:
4242 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4243 return -EIO;
4244 }
4245
rtl_skb_is_udp(struct sk_buff * skb)4246 static bool rtl_skb_is_udp(struct sk_buff *skb)
4247 {
4248 int no = skb_network_offset(skb);
4249 struct ipv6hdr *i6h, _i6h;
4250 struct iphdr *ih, _ih;
4251
4252 switch (vlan_get_protocol(skb)) {
4253 case htons(ETH_P_IP):
4254 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4255 return ih && ih->protocol == IPPROTO_UDP;
4256 case htons(ETH_P_IPV6):
4257 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4258 return i6h && i6h->nexthdr == IPPROTO_UDP;
4259 default:
4260 return false;
4261 }
4262 }
4263
4264 #define RTL_MIN_PATCH_LEN 47
4265
4266 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
rtl8125_quirk_udp_padto(struct rtl8169_private * tp,struct sk_buff * skb)4267 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4268 struct sk_buff *skb)
4269 {
4270 unsigned int padto = 0, len = skb->len;
4271
4272 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) &&
4273 skb_transport_header_was_set(skb)) {
4274 unsigned int trans_data_len = skb_tail_pointer(skb) -
4275 skb_transport_header(skb);
4276
4277 if (trans_data_len >= offsetof(struct udphdr, len) &&
4278 trans_data_len < RTL_MIN_PATCH_LEN) {
4279 u16 dest = ntohs(udp_hdr(skb)->dest);
4280
4281 /* dest is a standard PTP port */
4282 if (dest == 319 || dest == 320)
4283 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4284 }
4285
4286 if (trans_data_len < sizeof(struct udphdr))
4287 padto = max_t(unsigned int, padto,
4288 len + sizeof(struct udphdr) - trans_data_len);
4289 }
4290
4291 return padto;
4292 }
4293
rtl_quirk_packet_padto(struct rtl8169_private * tp,struct sk_buff * skb)4294 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4295 struct sk_buff *skb)
4296 {
4297 unsigned int padto = 0;
4298
4299 switch (tp->mac_version) {
4300 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
4301 padto = rtl8125_quirk_udp_padto(tp, skb);
4302 break;
4303 default:
4304 break;
4305 }
4306
4307 switch (tp->mac_version) {
4308 case RTL_GIGA_MAC_VER_34:
4309 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
4310 padto = max_t(unsigned int, padto, ETH_ZLEN);
4311 break;
4312 default:
4313 break;
4314 }
4315
4316 return padto;
4317 }
4318
rtl8169_tso_csum_v1(struct sk_buff * skb,u32 * opts)4319 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4320 {
4321 u32 mss = skb_shinfo(skb)->gso_size;
4322
4323 if (mss) {
4324 opts[0] |= TD_LSO;
4325 opts[0] |= mss << TD0_MSS_SHIFT;
4326 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4327 const struct iphdr *ip = ip_hdr(skb);
4328
4329 if (ip->protocol == IPPROTO_TCP)
4330 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4331 else if (ip->protocol == IPPROTO_UDP)
4332 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4333 else
4334 WARN_ON_ONCE(1);
4335 }
4336 }
4337
rtl8169_tso_csum_v2(struct rtl8169_private * tp,struct sk_buff * skb,u32 * opts)4338 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4339 struct sk_buff *skb, u32 *opts)
4340 {
4341 struct skb_shared_info *shinfo = skb_shinfo(skb);
4342 u32 mss = shinfo->gso_size;
4343
4344 if (mss) {
4345 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4346 opts[0] |= TD1_GTSENV4;
4347 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4348 if (skb_cow_head(skb, 0))
4349 return false;
4350
4351 tcp_v6_gso_csum_prep(skb);
4352 opts[0] |= TD1_GTSENV6;
4353 } else {
4354 WARN_ON_ONCE(1);
4355 }
4356
4357 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4358 opts[1] |= mss << TD1_MSS_SHIFT;
4359 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4360 u8 ip_protocol;
4361
4362 switch (vlan_get_protocol(skb)) {
4363 case htons(ETH_P_IP):
4364 opts[1] |= TD1_IPv4_CS;
4365 ip_protocol = ip_hdr(skb)->protocol;
4366 break;
4367
4368 case htons(ETH_P_IPV6):
4369 opts[1] |= TD1_IPv6_CS;
4370 ip_protocol = ipv6_hdr(skb)->nexthdr;
4371 break;
4372
4373 default:
4374 ip_protocol = IPPROTO_RAW;
4375 break;
4376 }
4377
4378 if (ip_protocol == IPPROTO_TCP)
4379 opts[1] |= TD1_TCP_CS;
4380 else if (ip_protocol == IPPROTO_UDP)
4381 opts[1] |= TD1_UDP_CS;
4382 else
4383 WARN_ON_ONCE(1);
4384
4385 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4386 } else {
4387 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4388
4389 /* skb_padto would free the skb on error */
4390 return !__skb_put_padto(skb, padto, false);
4391 }
4392
4393 return true;
4394 }
4395
rtl_tx_slots_avail(struct rtl8169_private * tp)4396 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4397 {
4398 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4399 }
4400
4401 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
rtl_chip_supports_csum_v2(struct rtl8169_private * tp)4402 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4403 {
4404 switch (tp->mac_version) {
4405 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4406 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4407 return false;
4408 default:
4409 return true;
4410 }
4411 }
4412
rtl8169_doorbell(struct rtl8169_private * tp)4413 static void rtl8169_doorbell(struct rtl8169_private *tp)
4414 {
4415 if (rtl_is_8125(tp))
4416 RTL_W16(tp, TxPoll_8125, BIT(0));
4417 else
4418 RTL_W8(tp, TxPoll, NPQ);
4419 }
4420
rtl8169_start_xmit(struct sk_buff * skb,struct net_device * dev)4421 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4422 struct net_device *dev)
4423 {
4424 struct rtl8169_private *tp = netdev_priv(dev);
4425 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4426 struct TxDesc *txd_first, *txd_last;
4427 bool stop_queue, door_bell;
4428 unsigned int frags;
4429 u32 opts[2];
4430
4431 if (unlikely(!rtl_tx_slots_avail(tp))) {
4432 if (net_ratelimit())
4433 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4434 netif_stop_queue(dev);
4435 return NETDEV_TX_BUSY;
4436 }
4437
4438 opts[1] = rtl8169_tx_vlan_tag(skb);
4439 opts[0] = 0;
4440
4441 if (!rtl_chip_supports_csum_v2(tp))
4442 rtl8169_tso_csum_v1(skb, opts);
4443 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4444 goto err_dma_0;
4445
4446 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4447 entry, false)))
4448 goto err_dma_0;
4449
4450 txd_first = tp->TxDescArray + entry;
4451
4452 frags = skb_shinfo(skb)->nr_frags;
4453 if (frags) {
4454 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4455 goto err_dma_1;
4456 entry = (entry + frags) % NUM_TX_DESC;
4457 }
4458
4459 txd_last = tp->TxDescArray + entry;
4460 txd_last->opts1 |= cpu_to_le32(LastFrag);
4461 tp->tx_skb[entry].skb = skb;
4462
4463 skb_tx_timestamp(skb);
4464
4465 /* Force memory writes to complete before releasing descriptor */
4466 dma_wmb();
4467
4468 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4469
4470 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4471
4472 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4473 smp_wmb();
4474
4475 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4476
4477 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4478 R8169_TX_STOP_THRS,
4479 R8169_TX_START_THRS);
4480 if (door_bell || stop_queue)
4481 rtl8169_doorbell(tp);
4482
4483 return NETDEV_TX_OK;
4484
4485 err_dma_1:
4486 rtl8169_unmap_tx_skb(tp, entry);
4487 err_dma_0:
4488 dev_kfree_skb_any(skb);
4489 dev->stats.tx_dropped++;
4490 return NETDEV_TX_OK;
4491 }
4492
rtl_last_frag_len(struct sk_buff * skb)4493 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4494 {
4495 struct skb_shared_info *info = skb_shinfo(skb);
4496 unsigned int nr_frags = info->nr_frags;
4497
4498 if (!nr_frags)
4499 return UINT_MAX;
4500
4501 return skb_frag_size(info->frags + nr_frags - 1);
4502 }
4503
4504 /* Workaround for hw issues with TSO on RTL8168evl */
rtl8168evl_fix_tso(struct sk_buff * skb,netdev_features_t features)4505 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4506 netdev_features_t features)
4507 {
4508 /* IPv4 header has options field */
4509 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4510 ip_hdrlen(skb) > sizeof(struct iphdr))
4511 features &= ~NETIF_F_ALL_TSO;
4512
4513 /* IPv4 TCP header has options field */
4514 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4515 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4516 features &= ~NETIF_F_ALL_TSO;
4517
4518 else if (rtl_last_frag_len(skb) <= 6)
4519 features &= ~NETIF_F_ALL_TSO;
4520
4521 return features;
4522 }
4523
rtl8169_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)4524 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4525 struct net_device *dev,
4526 netdev_features_t features)
4527 {
4528 struct rtl8169_private *tp = netdev_priv(dev);
4529
4530 if (skb_is_gso(skb)) {
4531 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4532 features = rtl8168evl_fix_tso(skb, features);
4533
4534 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4535 rtl_chip_supports_csum_v2(tp))
4536 features &= ~NETIF_F_ALL_TSO;
4537 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4538 /* work around hw bug on some chip versions */
4539 if (skb->len < ETH_ZLEN)
4540 features &= ~NETIF_F_CSUM_MASK;
4541
4542 if (rtl_quirk_packet_padto(tp, skb))
4543 features &= ~NETIF_F_CSUM_MASK;
4544
4545 if (skb_transport_offset(skb) > TCPHO_MAX &&
4546 rtl_chip_supports_csum_v2(tp))
4547 features &= ~NETIF_F_CSUM_MASK;
4548 }
4549
4550 return vlan_features_check(skb, features);
4551 }
4552
rtl8169_pcierr_interrupt(struct net_device * dev)4553 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4554 {
4555 struct rtl8169_private *tp = netdev_priv(dev);
4556 struct pci_dev *pdev = tp->pci_dev;
4557 int pci_status_errs;
4558 u16 pci_cmd;
4559
4560 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4561
4562 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4563
4564 if (net_ratelimit())
4565 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4566 pci_cmd, pci_status_errs);
4567
4568 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4569 }
4570
rtl_tx(struct net_device * dev,struct rtl8169_private * tp,int budget)4571 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4572 int budget)
4573 {
4574 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4575 struct sk_buff *skb;
4576
4577 dirty_tx = tp->dirty_tx;
4578
4579 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4580 unsigned int entry = dirty_tx % NUM_TX_DESC;
4581 u32 status;
4582
4583 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4584 if (status & DescOwn)
4585 break;
4586
4587 skb = tp->tx_skb[entry].skb;
4588 rtl8169_unmap_tx_skb(tp, entry);
4589
4590 if (skb) {
4591 pkts_compl++;
4592 bytes_compl += skb->len;
4593 napi_consume_skb(skb, budget);
4594 }
4595 dirty_tx++;
4596 }
4597
4598 if (tp->dirty_tx != dirty_tx) {
4599 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4600 WRITE_ONCE(tp->dirty_tx, dirty_tx);
4601
4602 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4603 rtl_tx_slots_avail(tp),
4604 R8169_TX_START_THRS);
4605 /*
4606 * 8168 hack: TxPoll requests are lost when the Tx packets are
4607 * too close. Let's kick an extra TxPoll request when a burst
4608 * of start_xmit activity is detected (if it is not detected,
4609 * it is slow enough). -- FR
4610 * If skb is NULL then we come here again once a tx irq is
4611 * triggered after the last fragment is marked transmitted.
4612 */
4613 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4614 rtl8169_doorbell(tp);
4615 }
4616 }
4617
rtl8169_fragmented_frame(u32 status)4618 static inline int rtl8169_fragmented_frame(u32 status)
4619 {
4620 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4621 }
4622
rtl8169_rx_csum(struct sk_buff * skb,u32 opts1)4623 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4624 {
4625 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4626
4627 if (status == RxProtoTCP || status == RxProtoUDP)
4628 skb->ip_summed = CHECKSUM_UNNECESSARY;
4629 else
4630 skb_checksum_none_assert(skb);
4631 }
4632
rtl_rx(struct net_device * dev,struct rtl8169_private * tp,int budget)4633 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4634 {
4635 struct device *d = tp_to_dev(tp);
4636 int count;
4637
4638 for (count = 0; count < budget; count++, tp->cur_rx++) {
4639 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4640 struct RxDesc *desc = tp->RxDescArray + entry;
4641 struct sk_buff *skb;
4642 const void *rx_buf;
4643 dma_addr_t addr;
4644 u32 status;
4645
4646 status = le32_to_cpu(READ_ONCE(desc->opts1));
4647 if (status & DescOwn)
4648 break;
4649
4650 /* This barrier is needed to keep us from reading
4651 * any other fields out of the Rx descriptor until
4652 * we know the status of DescOwn
4653 */
4654 dma_rmb();
4655
4656 if (unlikely(status & RxRES)) {
4657 if (net_ratelimit())
4658 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4659 status);
4660 dev->stats.rx_errors++;
4661 if (status & (RxRWT | RxRUNT))
4662 dev->stats.rx_length_errors++;
4663 if (status & RxCRC)
4664 dev->stats.rx_crc_errors++;
4665
4666 if (!(dev->features & NETIF_F_RXALL))
4667 goto release_descriptor;
4668 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4669 goto release_descriptor;
4670 }
4671
4672 pkt_size = status & GENMASK(13, 0);
4673 if (likely(!(dev->features & NETIF_F_RXFCS)))
4674 pkt_size -= ETH_FCS_LEN;
4675
4676 /* The driver does not support incoming fragmented frames.
4677 * They are seen as a symptom of over-mtu sized frames.
4678 */
4679 if (unlikely(rtl8169_fragmented_frame(status))) {
4680 dev->stats.rx_dropped++;
4681 dev->stats.rx_length_errors++;
4682 goto release_descriptor;
4683 }
4684
4685 skb = napi_alloc_skb(&tp->napi, pkt_size);
4686 if (unlikely(!skb)) {
4687 dev->stats.rx_dropped++;
4688 goto release_descriptor;
4689 }
4690
4691 addr = le64_to_cpu(desc->addr);
4692 rx_buf = page_address(tp->Rx_databuff[entry]);
4693
4694 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4695 prefetch(rx_buf);
4696 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4697 skb->tail += pkt_size;
4698 skb->len = pkt_size;
4699 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4700
4701 rtl8169_rx_csum(skb, status);
4702 skb->protocol = eth_type_trans(skb, dev);
4703
4704 rtl8169_rx_vlan_tag(desc, skb);
4705
4706 if (skb->pkt_type == PACKET_MULTICAST)
4707 dev->stats.multicast++;
4708
4709 napi_gro_receive(&tp->napi, skb);
4710
4711 dev_sw_netstats_rx_add(dev, pkt_size);
4712 release_descriptor:
4713 rtl8169_mark_to_asic(desc);
4714 }
4715
4716 return count;
4717 }
4718
rtl8169_interrupt(int irq,void * dev_instance)4719 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4720 {
4721 struct rtl8169_private *tp = dev_instance;
4722 u32 status = rtl_get_events(tp);
4723
4724 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4725 return IRQ_NONE;
4726
4727 /* At least RTL8168fp may unexpectedly set the SYSErr bit */
4728 if (unlikely(status & SYSErr &&
4729 tp->mac_version <= RTL_GIGA_MAC_VER_06)) {
4730 rtl8169_pcierr_interrupt(tp->dev);
4731 goto out;
4732 }
4733
4734 if (status & LinkChg)
4735 phy_mac_interrupt(tp->phydev);
4736
4737 if (unlikely(status & RxFIFOOver &&
4738 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4739 netif_stop_queue(tp->dev);
4740 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4741 }
4742
4743 rtl_irq_disable(tp);
4744 napi_schedule(&tp->napi);
4745 out:
4746 rtl_ack_events(tp, status);
4747
4748 return IRQ_HANDLED;
4749 }
4750
rtl_task(struct work_struct * work)4751 static void rtl_task(struct work_struct *work)
4752 {
4753 struct rtl8169_private *tp =
4754 container_of(work, struct rtl8169_private, wk.work);
4755 int ret;
4756
4757 rtnl_lock();
4758
4759 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4760 goto out_unlock;
4761
4762 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4763 /* if chip isn't accessible, reset bus to revive it */
4764 if (RTL_R32(tp, TxConfig) == ~0) {
4765 ret = pci_reset_bus(tp->pci_dev);
4766 if (ret < 0) {
4767 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4768 netif_device_detach(tp->dev);
4769 goto out_unlock;
4770 }
4771 }
4772
4773 /* ASPM compatibility issues are a typical reason for tx timeouts */
4774 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4775 PCIE_LINK_STATE_L0S);
4776 if (!ret)
4777 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4778 goto reset;
4779 }
4780
4781 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4782 reset:
4783 rtl_reset_work(tp);
4784 netif_wake_queue(tp->dev);
4785 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) {
4786 rtl_reset_work(tp);
4787 }
4788 out_unlock:
4789 rtnl_unlock();
4790 }
4791
rtl8169_poll(struct napi_struct * napi,int budget)4792 static int rtl8169_poll(struct napi_struct *napi, int budget)
4793 {
4794 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4795 struct net_device *dev = tp->dev;
4796 int work_done;
4797
4798 rtl_tx(dev, tp, budget);
4799
4800 work_done = rtl_rx(dev, tp, budget);
4801
4802 if (work_done < budget && napi_complete_done(napi, work_done))
4803 rtl_irq_enable(tp);
4804
4805 return work_done;
4806 }
4807
r8169_phylink_handler(struct net_device * ndev)4808 static void r8169_phylink_handler(struct net_device *ndev)
4809 {
4810 struct rtl8169_private *tp = netdev_priv(ndev);
4811 struct device *d = tp_to_dev(tp);
4812
4813 if (netif_carrier_ok(ndev)) {
4814 rtl_link_chg_patch(tp);
4815 pm_request_resume(d);
4816 netif_wake_queue(tp->dev);
4817 } else {
4818 /* In few cases rx is broken after link-down otherwise */
4819 if (rtl_is_8125(tp))
4820 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE);
4821 pm_runtime_idle(d);
4822 }
4823
4824 phy_print_status(tp->phydev);
4825 }
4826
r8169_phy_connect(struct rtl8169_private * tp)4827 static int r8169_phy_connect(struct rtl8169_private *tp)
4828 {
4829 struct phy_device *phydev = tp->phydev;
4830 phy_interface_t phy_mode;
4831 int ret;
4832
4833 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4834 PHY_INTERFACE_MODE_MII;
4835
4836 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4837 phy_mode);
4838 if (ret)
4839 return ret;
4840
4841 if (!tp->supports_gmii)
4842 phy_set_max_speed(phydev, SPEED_100);
4843
4844 phy_attached_info(phydev);
4845
4846 return 0;
4847 }
4848
rtl8169_down(struct rtl8169_private * tp)4849 static void rtl8169_down(struct rtl8169_private *tp)
4850 {
4851 /* Clear all task flags */
4852 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4853
4854 phy_stop(tp->phydev);
4855
4856 rtl8169_update_counters(tp);
4857
4858 pci_clear_master(tp->pci_dev);
4859 rtl_pci_commit(tp);
4860
4861 rtl8169_cleanup(tp);
4862 rtl_disable_exit_l1(tp);
4863 rtl_prepare_power_down(tp);
4864
4865 if (tp->dash_type != RTL_DASH_NONE)
4866 rtl8168_driver_stop(tp);
4867 }
4868
rtl8169_up(struct rtl8169_private * tp)4869 static void rtl8169_up(struct rtl8169_private *tp)
4870 {
4871 if (tp->dash_type != RTL_DASH_NONE)
4872 rtl8168_driver_start(tp);
4873
4874 pci_set_master(tp->pci_dev);
4875 phy_init_hw(tp->phydev);
4876 phy_resume(tp->phydev);
4877 rtl8169_init_phy(tp);
4878 napi_enable(&tp->napi);
4879 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4880 rtl_reset_work(tp);
4881
4882 phy_start(tp->phydev);
4883 }
4884
rtl8169_close(struct net_device * dev)4885 static int rtl8169_close(struct net_device *dev)
4886 {
4887 struct rtl8169_private *tp = netdev_priv(dev);
4888 struct pci_dev *pdev = tp->pci_dev;
4889
4890 pm_runtime_get_sync(&pdev->dev);
4891
4892 netif_stop_queue(dev);
4893 rtl8169_down(tp);
4894 rtl8169_rx_clear(tp);
4895
4896 cancel_work(&tp->wk.work);
4897
4898 free_irq(tp->irq, tp);
4899
4900 phy_disconnect(tp->phydev);
4901
4902 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4903 tp->RxPhyAddr);
4904 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4905 tp->TxPhyAddr);
4906 tp->TxDescArray = NULL;
4907 tp->RxDescArray = NULL;
4908
4909 pm_runtime_put_sync(&pdev->dev);
4910
4911 return 0;
4912 }
4913
4914 #ifdef CONFIG_NET_POLL_CONTROLLER
rtl8169_netpoll(struct net_device * dev)4915 static void rtl8169_netpoll(struct net_device *dev)
4916 {
4917 struct rtl8169_private *tp = netdev_priv(dev);
4918
4919 rtl8169_interrupt(tp->irq, tp);
4920 }
4921 #endif
4922
rtl_open(struct net_device * dev)4923 static int rtl_open(struct net_device *dev)
4924 {
4925 struct rtl8169_private *tp = netdev_priv(dev);
4926 struct pci_dev *pdev = tp->pci_dev;
4927 unsigned long irqflags;
4928 int retval = -ENOMEM;
4929
4930 pm_runtime_get_sync(&pdev->dev);
4931
4932 /*
4933 * Rx and Tx descriptors needs 256 bytes alignment.
4934 * dma_alloc_coherent provides more.
4935 */
4936 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4937 &tp->TxPhyAddr, GFP_KERNEL);
4938 if (!tp->TxDescArray)
4939 goto out;
4940
4941 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4942 &tp->RxPhyAddr, GFP_KERNEL);
4943 if (!tp->RxDescArray)
4944 goto err_free_tx_0;
4945
4946 retval = rtl8169_init_ring(tp);
4947 if (retval < 0)
4948 goto err_free_rx_1;
4949
4950 rtl_request_firmware(tp);
4951
4952 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4953 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4954 if (retval < 0)
4955 goto err_release_fw_2;
4956
4957 retval = r8169_phy_connect(tp);
4958 if (retval)
4959 goto err_free_irq;
4960
4961 rtl8169_up(tp);
4962 rtl8169_init_counter_offsets(tp);
4963 netif_start_queue(dev);
4964 out:
4965 pm_runtime_put_sync(&pdev->dev);
4966
4967 return retval;
4968
4969 err_free_irq:
4970 free_irq(tp->irq, tp);
4971 err_release_fw_2:
4972 rtl_release_firmware(tp);
4973 rtl8169_rx_clear(tp);
4974 err_free_rx_1:
4975 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4976 tp->RxPhyAddr);
4977 tp->RxDescArray = NULL;
4978 err_free_tx_0:
4979 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4980 tp->TxPhyAddr);
4981 tp->TxDescArray = NULL;
4982 goto out;
4983 }
4984
4985 static void
rtl8169_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)4986 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4987 {
4988 struct rtl8169_private *tp = netdev_priv(dev);
4989 struct pci_dev *pdev = tp->pci_dev;
4990 struct rtl8169_counters *counters = tp->counters;
4991
4992 pm_runtime_get_noresume(&pdev->dev);
4993
4994 netdev_stats_to_stats64(stats, &dev->stats);
4995 dev_fetch_sw_netstats(stats, dev->tstats);
4996
4997 /*
4998 * Fetch additional counter values missing in stats collected by driver
4999 * from tally counters.
5000 */
5001 if (pm_runtime_active(&pdev->dev))
5002 rtl8169_update_counters(tp);
5003
5004 /*
5005 * Subtract values fetched during initalization.
5006 * See rtl8169_init_counter_offsets for a description why we do that.
5007 */
5008 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
5009 le64_to_cpu(tp->tc_offset.tx_errors);
5010 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
5011 le32_to_cpu(tp->tc_offset.tx_multi_collision);
5012 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
5013 le16_to_cpu(tp->tc_offset.tx_aborted);
5014 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
5015 le16_to_cpu(tp->tc_offset.rx_missed);
5016
5017 pm_runtime_put_noidle(&pdev->dev);
5018 }
5019
rtl8169_net_suspend(struct rtl8169_private * tp)5020 static void rtl8169_net_suspend(struct rtl8169_private *tp)
5021 {
5022 netif_device_detach(tp->dev);
5023
5024 if (netif_running(tp->dev))
5025 rtl8169_down(tp);
5026 }
5027
rtl8169_runtime_resume(struct device * dev)5028 static int rtl8169_runtime_resume(struct device *dev)
5029 {
5030 struct rtl8169_private *tp = dev_get_drvdata(dev);
5031
5032 rtl_rar_set(tp, tp->dev->dev_addr);
5033 __rtl8169_set_wol(tp, tp->saved_wolopts);
5034
5035 if (tp->TxDescArray)
5036 rtl8169_up(tp);
5037
5038 netif_device_attach(tp->dev);
5039
5040 return 0;
5041 }
5042
rtl8169_suspend(struct device * device)5043 static int rtl8169_suspend(struct device *device)
5044 {
5045 struct rtl8169_private *tp = dev_get_drvdata(device);
5046
5047 rtnl_lock();
5048 rtl8169_net_suspend(tp);
5049 if (!device_may_wakeup(tp_to_dev(tp)))
5050 clk_disable_unprepare(tp->clk);
5051 rtnl_unlock();
5052
5053 return 0;
5054 }
5055
rtl8169_resume(struct device * device)5056 static int rtl8169_resume(struct device *device)
5057 {
5058 struct rtl8169_private *tp = dev_get_drvdata(device);
5059
5060 if (!device_may_wakeup(tp_to_dev(tp)))
5061 clk_prepare_enable(tp->clk);
5062
5063 /* Reportedly at least Asus X453MA truncates packets otherwise */
5064 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
5065 rtl_init_rxcfg(tp);
5066
5067 return rtl8169_runtime_resume(device);
5068 }
5069
rtl8169_runtime_suspend(struct device * device)5070 static int rtl8169_runtime_suspend(struct device *device)
5071 {
5072 struct rtl8169_private *tp = dev_get_drvdata(device);
5073
5074 if (!tp->TxDescArray) {
5075 netif_device_detach(tp->dev);
5076 return 0;
5077 }
5078
5079 rtnl_lock();
5080 __rtl8169_set_wol(tp, WAKE_PHY);
5081 rtl8169_net_suspend(tp);
5082 rtnl_unlock();
5083
5084 return 0;
5085 }
5086
rtl8169_runtime_idle(struct device * device)5087 static int rtl8169_runtime_idle(struct device *device)
5088 {
5089 struct rtl8169_private *tp = dev_get_drvdata(device);
5090
5091 if (tp->dash_enabled)
5092 return -EBUSY;
5093
5094 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
5095 pm_schedule_suspend(device, 10000);
5096
5097 return -EBUSY;
5098 }
5099
5100 static const struct dev_pm_ops rtl8169_pm_ops = {
5101 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
5102 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
5103 rtl8169_runtime_idle)
5104 };
5105
rtl_shutdown(struct pci_dev * pdev)5106 static void rtl_shutdown(struct pci_dev *pdev)
5107 {
5108 struct rtl8169_private *tp = pci_get_drvdata(pdev);
5109
5110 rtnl_lock();
5111 rtl8169_net_suspend(tp);
5112 rtnl_unlock();
5113
5114 /* Restore original MAC address */
5115 rtl_rar_set(tp, tp->dev->perm_addr);
5116
5117 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) {
5118 pci_wake_from_d3(pdev, tp->saved_wolopts);
5119 pci_set_power_state(pdev, PCI_D3hot);
5120 }
5121 }
5122
rtl_remove_one(struct pci_dev * pdev)5123 static void rtl_remove_one(struct pci_dev *pdev)
5124 {
5125 struct rtl8169_private *tp = pci_get_drvdata(pdev);
5126
5127 if (pci_dev_run_wake(pdev))
5128 pm_runtime_get_noresume(&pdev->dev);
5129
5130 cancel_work_sync(&tp->wk.work);
5131
5132 if (IS_ENABLED(CONFIG_R8169_LEDS))
5133 r8169_remove_leds(tp->leds);
5134
5135 unregister_netdev(tp->dev);
5136
5137 if (tp->dash_type != RTL_DASH_NONE)
5138 rtl8168_driver_stop(tp);
5139
5140 rtl_release_firmware(tp);
5141
5142 /* restore original MAC address */
5143 rtl_rar_set(tp, tp->dev->perm_addr);
5144 }
5145
5146 static const struct net_device_ops rtl_netdev_ops = {
5147 .ndo_open = rtl_open,
5148 .ndo_stop = rtl8169_close,
5149 .ndo_get_stats64 = rtl8169_get_stats64,
5150 .ndo_start_xmit = rtl8169_start_xmit,
5151 .ndo_features_check = rtl8169_features_check,
5152 .ndo_tx_timeout = rtl8169_tx_timeout,
5153 .ndo_validate_addr = eth_validate_addr,
5154 .ndo_change_mtu = rtl8169_change_mtu,
5155 .ndo_fix_features = rtl8169_fix_features,
5156 .ndo_set_features = rtl8169_set_features,
5157 .ndo_set_mac_address = rtl_set_mac_address,
5158 .ndo_eth_ioctl = phy_do_ioctl_running,
5159 .ndo_set_rx_mode = rtl_set_rx_mode,
5160 #ifdef CONFIG_NET_POLL_CONTROLLER
5161 .ndo_poll_controller = rtl8169_netpoll,
5162 #endif
5163
5164 };
5165
rtl_set_irq_mask(struct rtl8169_private * tp)5166 static void rtl_set_irq_mask(struct rtl8169_private *tp)
5167 {
5168 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5169
5170 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5171 tp->irq_mask |= SYSErr | RxFIFOOver;
5172 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5173 /* special workaround needed */
5174 tp->irq_mask |= RxFIFOOver;
5175 }
5176
rtl_alloc_irq(struct rtl8169_private * tp)5177 static int rtl_alloc_irq(struct rtl8169_private *tp)
5178 {
5179 unsigned int flags;
5180
5181 switch (tp->mac_version) {
5182 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5183 rtl_unlock_config_regs(tp);
5184 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5185 rtl_lock_config_regs(tp);
5186 fallthrough;
5187 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5188 flags = PCI_IRQ_INTX;
5189 break;
5190 default:
5191 flags = PCI_IRQ_ALL_TYPES;
5192 break;
5193 }
5194
5195 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5196 }
5197
rtl_read_mac_address(struct rtl8169_private * tp,u8 mac_addr[ETH_ALEN])5198 static void rtl_read_mac_address(struct rtl8169_private *tp,
5199 u8 mac_addr[ETH_ALEN])
5200 {
5201 /* Get MAC address */
5202 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5203 u32 value;
5204
5205 value = rtl_eri_read(tp, 0xe0);
5206 put_unaligned_le32(value, mac_addr);
5207 value = rtl_eri_read(tp, 0xe4);
5208 put_unaligned_le16(value, mac_addr + 4);
5209 } else if (rtl_is_8125(tp)) {
5210 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5211 }
5212 }
5213
DECLARE_RTL_COND(rtl_link_list_ready_cond)5214 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5215 {
5216 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5217 }
5218
r8168g_wait_ll_share_fifo_ready(struct rtl8169_private * tp)5219 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5220 {
5221 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5222 }
5223
r8169_mdio_read_reg(struct mii_bus * mii_bus,int phyaddr,int phyreg)5224 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5225 {
5226 struct rtl8169_private *tp = mii_bus->priv;
5227
5228 if (phyaddr > 0)
5229 return -ENODEV;
5230
5231 return rtl_readphy(tp, phyreg);
5232 }
5233
r8169_mdio_write_reg(struct mii_bus * mii_bus,int phyaddr,int phyreg,u16 val)5234 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5235 int phyreg, u16 val)
5236 {
5237 struct rtl8169_private *tp = mii_bus->priv;
5238
5239 if (phyaddr > 0)
5240 return -ENODEV;
5241
5242 rtl_writephy(tp, phyreg, val);
5243
5244 return 0;
5245 }
5246
r8169_mdio_register(struct rtl8169_private * tp)5247 static int r8169_mdio_register(struct rtl8169_private *tp)
5248 {
5249 struct pci_dev *pdev = tp->pci_dev;
5250 struct mii_bus *new_bus;
5251 int ret;
5252
5253 /* On some boards with this chip version the BIOS is buggy and misses
5254 * to reset the PHY page selector. This results in the PHY ID read
5255 * accessing registers on a different page, returning a more or
5256 * less random value. Fix this by resetting the page selector first.
5257 */
5258 if (tp->mac_version == RTL_GIGA_MAC_VER_25 ||
5259 tp->mac_version == RTL_GIGA_MAC_VER_26)
5260 r8169_mdio_write(tp, 0x1f, 0);
5261
5262 new_bus = devm_mdiobus_alloc(&pdev->dev);
5263 if (!new_bus)
5264 return -ENOMEM;
5265
5266 new_bus->name = "r8169";
5267 new_bus->priv = tp;
5268 new_bus->parent = &pdev->dev;
5269 new_bus->irq[0] = PHY_MAC_INTERRUPT;
5270 new_bus->phy_mask = GENMASK(31, 1);
5271 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5272 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5273
5274 new_bus->read = r8169_mdio_read_reg;
5275 new_bus->write = r8169_mdio_write_reg;
5276
5277 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5278 if (ret)
5279 return ret;
5280
5281 tp->phydev = mdiobus_get_phy(new_bus, 0);
5282 if (!tp->phydev) {
5283 return -ENODEV;
5284 } else if (!tp->phydev->drv) {
5285 /* Most chip versions fail with the genphy driver.
5286 * Therefore ensure that the dedicated PHY driver is loaded.
5287 */
5288 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5289 tp->phydev->phy_id);
5290 return -EUNATCH;
5291 }
5292
5293 tp->phydev->mac_managed_pm = true;
5294 if (rtl_supports_eee(tp))
5295 phy_support_eee(tp->phydev);
5296 phy_support_asym_pause(tp->phydev);
5297
5298 /* PHY will be woken up in rtl_open() */
5299 phy_suspend(tp->phydev);
5300
5301 return 0;
5302 }
5303
rtl_hw_init_8168g(struct rtl8169_private * tp)5304 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5305 {
5306 rtl_enable_rxdvgate(tp);
5307
5308 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5309 msleep(1);
5310 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5311
5312 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5313 r8168g_wait_ll_share_fifo_ready(tp);
5314
5315 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5316 r8168g_wait_ll_share_fifo_ready(tp);
5317 }
5318
rtl_hw_init_8125(struct rtl8169_private * tp)5319 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5320 {
5321 rtl_enable_rxdvgate(tp);
5322
5323 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5324 msleep(1);
5325 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5326
5327 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5328 r8168g_wait_ll_share_fifo_ready(tp);
5329
5330 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5331 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5332 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5333 r8168g_wait_ll_share_fifo_ready(tp);
5334 }
5335
rtl_hw_initialize(struct rtl8169_private * tp)5336 static void rtl_hw_initialize(struct rtl8169_private *tp)
5337 {
5338 switch (tp->mac_version) {
5339 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5340 rtl8168ep_stop_cmac(tp);
5341 fallthrough;
5342 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5343 rtl_hw_init_8168g(tp);
5344 break;
5345 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:
5346 rtl_hw_init_8125(tp);
5347 break;
5348 default:
5349 break;
5350 }
5351 }
5352
rtl_jumbo_max(struct rtl8169_private * tp)5353 static int rtl_jumbo_max(struct rtl8169_private *tp)
5354 {
5355 /* Non-GBit versions don't support jumbo frames */
5356 if (!tp->supports_gmii)
5357 return 0;
5358
5359 switch (tp->mac_version) {
5360 /* RTL8169 */
5361 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5362 return JUMBO_7K;
5363 /* RTL8168b */
5364 case RTL_GIGA_MAC_VER_11:
5365 case RTL_GIGA_MAC_VER_17:
5366 return JUMBO_4K;
5367 /* RTL8168c */
5368 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5369 return JUMBO_6K;
5370 default:
5371 return JUMBO_9K;
5372 }
5373 }
5374
rtl_init_mac_address(struct rtl8169_private * tp)5375 static void rtl_init_mac_address(struct rtl8169_private *tp)
5376 {
5377 u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5378 struct net_device *dev = tp->dev;
5379 int rc;
5380
5381 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5382 if (!rc)
5383 goto done;
5384
5385 rtl_read_mac_address(tp, mac_addr);
5386 if (is_valid_ether_addr(mac_addr))
5387 goto done;
5388
5389 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5390 if (is_valid_ether_addr(mac_addr))
5391 goto done;
5392
5393 eth_random_addr(mac_addr);
5394 dev->addr_assign_type = NET_ADDR_RANDOM;
5395 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5396 done:
5397 eth_hw_addr_set(dev, mac_addr);
5398 rtl_rar_set(tp, mac_addr);
5399 }
5400
5401 /* register is set if system vendor successfully tested ASPM 1.2 */
rtl_aspm_is_safe(struct rtl8169_private * tp)5402 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5403 {
5404 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5405 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5406 return true;
5407
5408 return false;
5409 }
5410
rtl_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)5411 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5412 {
5413 struct rtl8169_private *tp;
5414 int jumbo_max, region, rc;
5415 enum mac_version chipset;
5416 struct net_device *dev;
5417 u32 txconfig;
5418 u16 xid;
5419
5420 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5421 if (!dev)
5422 return -ENOMEM;
5423
5424 SET_NETDEV_DEV(dev, &pdev->dev);
5425 dev->netdev_ops = &rtl_netdev_ops;
5426 tp = netdev_priv(dev);
5427 tp->dev = dev;
5428 tp->pci_dev = pdev;
5429 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5430 tp->ocp_base = OCP_STD_PHY_BASE;
5431
5432 raw_spin_lock_init(&tp->cfg9346_usage_lock);
5433 raw_spin_lock_init(&tp->config25_lock);
5434 raw_spin_lock_init(&tp->mac_ocp_lock);
5435 mutex_init(&tp->led_lock);
5436
5437 /* Get the *optional* external "ether_clk" used on some boards */
5438 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5439 if (IS_ERR(tp->clk))
5440 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5441
5442 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5443 rc = pcim_enable_device(pdev);
5444 if (rc < 0)
5445 return dev_err_probe(&pdev->dev, rc, "enable failure\n");
5446
5447 if (pcim_set_mwi(pdev) < 0)
5448 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5449
5450 /* use first MMIO region */
5451 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5452 if (region < 0)
5453 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n");
5454
5455 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5456 if (rc < 0)
5457 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n");
5458
5459 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5460
5461 txconfig = RTL_R32(tp, TxConfig);
5462 if (txconfig == ~0U)
5463 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n");
5464
5465 xid = (txconfig >> 20) & 0xfcf;
5466
5467 /* Identify chip attached to board */
5468 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5469 if (chipset == RTL_GIGA_MAC_NONE)
5470 return dev_err_probe(&pdev->dev, -ENODEV,
5471 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5472 xid);
5473 tp->mac_version = chipset;
5474
5475 /* Disable ASPM L1 as that cause random device stop working
5476 * problems as well as full system hangs for some PCIe devices users.
5477 */
5478 if (rtl_aspm_is_safe(tp))
5479 rc = 0;
5480 else
5481 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5482 tp->aspm_manageable = !rc;
5483
5484 tp->dash_type = rtl_get_dash_type(tp);
5485 tp->dash_enabled = rtl_dash_is_enabled(tp);
5486
5487 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5488
5489 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5490 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5491 dev->features |= NETIF_F_HIGHDMA;
5492
5493 rtl_init_rxcfg(tp);
5494
5495 rtl8169_irq_mask_and_ack(tp);
5496
5497 rtl_hw_initialize(tp);
5498
5499 rtl_hw_reset(tp);
5500
5501 rc = rtl_alloc_irq(tp);
5502 if (rc < 0)
5503 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
5504
5505 tp->irq = pci_irq_vector(pdev, 0);
5506
5507 INIT_WORK(&tp->wk.work, rtl_task);
5508
5509 rtl_init_mac_address(tp);
5510
5511 dev->ethtool_ops = &rtl8169_ethtool_ops;
5512
5513 netif_napi_add(dev, &tp->napi, rtl8169_poll);
5514
5515 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5516 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5517 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5518 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5519
5520 /*
5521 * Pretend we are using VLANs; This bypasses a nasty bug where
5522 * Interrupts stop flowing on high load on 8110SCd controllers.
5523 */
5524 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5525 /* Disallow toggling */
5526 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5527
5528 if (rtl_chip_supports_csum_v2(tp))
5529 dev->hw_features |= NETIF_F_IPV6_CSUM;
5530
5531 dev->features |= dev->hw_features;
5532
5533 /* There has been a number of reports that using SG/TSO results in
5534 * tx timeouts. However for a lot of people SG/TSO works fine.
5535 * Therefore disable both features by default, but allow users to
5536 * enable them. Use at own risk!
5537 */
5538 if (rtl_chip_supports_csum_v2(tp)) {
5539 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5540 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5541 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5542 } else {
5543 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5544 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5545 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5546 }
5547
5548 dev->hw_features |= NETIF_F_RXALL;
5549 dev->hw_features |= NETIF_F_RXFCS;
5550
5551 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS;
5552
5553 netdev_sw_irq_coalesce_default_on(dev);
5554
5555 /* configure chip for default features */
5556 rtl8169_set_features(dev, dev->features);
5557
5558 if (!tp->dash_enabled) {
5559 rtl_set_d3_pll_down(tp, true);
5560 } else {
5561 rtl_set_d3_pll_down(tp, false);
5562 dev->ethtool->wol_enabled = 1;
5563 }
5564
5565 jumbo_max = rtl_jumbo_max(tp);
5566 if (jumbo_max)
5567 dev->max_mtu = jumbo_max;
5568
5569 rtl_set_irq_mask(tp);
5570
5571 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5572
5573 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5574 &tp->counters_phys_addr,
5575 GFP_KERNEL);
5576 if (!tp->counters)
5577 return -ENOMEM;
5578
5579 pci_set_drvdata(pdev, tp);
5580
5581 rc = r8169_mdio_register(tp);
5582 if (rc)
5583 return rc;
5584
5585 rc = register_netdev(dev);
5586 if (rc)
5587 return rc;
5588
5589 if (IS_ENABLED(CONFIG_R8169_LEDS)) {
5590 if (rtl_is_8125(tp))
5591 tp->leds = rtl8125_init_leds(dev);
5592 else if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5593 tp->leds = rtl8168_init_leds(dev);
5594 }
5595
5596 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5597 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5598
5599 if (jumbo_max)
5600 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5601 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5602 "ok" : "ko");
5603
5604 if (tp->dash_type != RTL_DASH_NONE) {
5605 netdev_info(dev, "DASH %s\n",
5606 tp->dash_enabled ? "enabled" : "disabled");
5607 rtl8168_driver_start(tp);
5608 }
5609
5610 if (pci_dev_run_wake(pdev))
5611 pm_runtime_put_sync(&pdev->dev);
5612
5613 return 0;
5614 }
5615
5616 static struct pci_driver rtl8169_pci_driver = {
5617 .name = KBUILD_MODNAME,
5618 .id_table = rtl8169_pci_tbl,
5619 .probe = rtl_init_one,
5620 .remove = rtl_remove_one,
5621 .shutdown = rtl_shutdown,
5622 .driver.pm = pm_ptr(&rtl8169_pm_ops),
5623 };
5624
5625 module_pci_driver(rtl8169_pci_driver);
5626