1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7
8 #include "core.h"
9
10 enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20
21 struct rtw89_c2hreg_hdr {
22 u32 w0;
23 };
24
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30 struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35 } __packed;
36
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50
51 #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
52 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
53 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
54 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
55 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
56 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
57 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
58 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
59 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
60 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
61 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
62 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
63 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
64 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
65 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
66 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
67 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
68 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
69 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
70 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
71 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
72 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
73 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
74 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
75 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
76
77 struct rtw89_h2creg_hdr {
78 u32 w0;
79 };
80
81 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
82 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
83
84 struct rtw89_h2creg_sch_tx_en {
85 u32 w0;
86 u32 w1;
87 } __packed;
88
89 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
90 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
91 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
92
93 #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
94
95 #define RTW89_H2CREG_MAX 4
96 #define RTW89_C2HREG_MAX 4
97 #define RTW89_C2HREG_HDR_LEN 2
98 #define RTW89_H2CREG_HDR_LEN 2
99 #define RTW89_C2H_TIMEOUT 1000000
100 #define RTW89_C2H_TIMEOUT_USB 4000
101
102 struct rtw89_mac_c2h_info {
103 u8 id;
104 u8 content_len;
105 union {
106 u32 c2hreg[RTW89_C2HREG_MAX];
107 struct rtw89_c2hreg_hdr hdr;
108 struct rtw89_c2hreg_phycap phycap;
109 } u;
110 };
111
112 struct rtw89_mac_h2c_info {
113 u8 id;
114 u8 content_len;
115 union {
116 u32 h2creg[RTW89_H2CREG_MAX];
117 struct rtw89_h2creg_hdr hdr;
118 struct rtw89_h2creg_sch_tx_en sch_tx_en;
119 } u;
120 };
121
122 enum rtw89_mac_h2c_type {
123 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
124 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
125 RTW89_FWCMD_H2CREG_FUNC_FWERR,
126 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
127 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
128 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
129 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP,
130 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1,
131 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2,
132 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ,
133 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL,
134 };
135
136 enum rtw89_mac_c2h_type {
137 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
138 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
139 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
140 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
141 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
142 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
143 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
144 };
145
146 enum rtw89_fw_c2h_category {
147 RTW89_C2H_CAT_TEST,
148 RTW89_C2H_CAT_MAC,
149 RTW89_C2H_CAT_OUTSRC,
150 };
151
152 enum rtw89_fw_log_level {
153 RTW89_FW_LOG_LEVEL_OFF,
154 RTW89_FW_LOG_LEVEL_CRT,
155 RTW89_FW_LOG_LEVEL_SER,
156 RTW89_FW_LOG_LEVEL_WARN,
157 RTW89_FW_LOG_LEVEL_LOUD,
158 RTW89_FW_LOG_LEVEL_TR,
159 };
160
161 enum rtw89_fw_log_path {
162 RTW89_FW_LOG_LEVEL_UART,
163 RTW89_FW_LOG_LEVEL_C2H,
164 RTW89_FW_LOG_LEVEL_SNI,
165 };
166
167 enum rtw89_fw_log_comp {
168 RTW89_FW_LOG_COMP_VER,
169 RTW89_FW_LOG_COMP_INIT,
170 RTW89_FW_LOG_COMP_TASK,
171 RTW89_FW_LOG_COMP_CNS,
172 RTW89_FW_LOG_COMP_H2C,
173 RTW89_FW_LOG_COMP_C2H,
174 RTW89_FW_LOG_COMP_TX,
175 RTW89_FW_LOG_COMP_RX,
176 RTW89_FW_LOG_COMP_IPSEC,
177 RTW89_FW_LOG_COMP_TIMER,
178 RTW89_FW_LOG_COMP_DBGPKT,
179 RTW89_FW_LOG_COMP_PS,
180 RTW89_FW_LOG_COMP_ERROR,
181 RTW89_FW_LOG_COMP_WOWLAN,
182 RTW89_FW_LOG_COMP_SECURE_BOOT,
183 RTW89_FW_LOG_COMP_BTC,
184 RTW89_FW_LOG_COMP_BB,
185 RTW89_FW_LOG_COMP_TWT,
186 RTW89_FW_LOG_COMP_RF,
187 RTW89_FW_LOG_COMP_MCC = 20,
188 RTW89_FW_LOG_COMP_SCAN = 28,
189 };
190
191 enum rtw89_pkt_offload_op {
192 RTW89_PKT_OFLD_OP_ADD,
193 RTW89_PKT_OFLD_OP_DEL,
194 RTW89_PKT_OFLD_OP_READ,
195
196 NUM_OF_RTW89_PKT_OFFLOAD_OP,
197 };
198
199 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
200 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
201
202 enum rtw89_scanofld_notify_reason {
203 RTW89_SCAN_DWELL_NOTIFY,
204 RTW89_SCAN_PRE_TX_NOTIFY,
205 RTW89_SCAN_POST_TX_NOTIFY,
206 RTW89_SCAN_ENTER_CH_NOTIFY,
207 RTW89_SCAN_LEAVE_CH_NOTIFY,
208 RTW89_SCAN_END_SCAN_NOTIFY,
209 RTW89_SCAN_REPORT_NOTIFY,
210 RTW89_SCAN_CHKPT_NOTIFY,
211 RTW89_SCAN_ENTER_OP_NOTIFY,
212 RTW89_SCAN_LEAVE_OP_NOTIFY,
213 };
214
215 enum rtw89_scanofld_status {
216 RTW89_SCAN_STATUS_NOTIFY,
217 RTW89_SCAN_STATUS_SUCCESS,
218 RTW89_SCAN_STATUS_FAIL,
219 };
220
221 enum rtw89_chan_type {
222 RTW89_CHAN_OPERATE = 0,
223 RTW89_CHAN_ACTIVE,
224 RTW89_CHAN_DFS,
225 };
226
227 enum rtw89_p2pps_action {
228 RTW89_P2P_ACT_INIT = 0,
229 RTW89_P2P_ACT_UPDATE = 1,
230 RTW89_P2P_ACT_REMOVE = 2,
231 RTW89_P2P_ACT_TERMINATE = 3,
232 };
233
234 #define RTW89_DEFAULT_CQM_HYST 4
235 #define RTW89_DEFAULT_CQM_THOLD -70
236
237 enum rtw89_bcn_fltr_offload_mode {
238 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
239 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
240 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
241 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
242
243 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
244 };
245
246 enum rtw89_bcn_fltr_type {
247 RTW89_BCN_FLTR_BEACON_LOSS,
248 RTW89_BCN_FLTR_RSSI,
249 RTW89_BCN_FLTR_NOTIFY,
250 };
251
252 enum rtw89_bcn_fltr_rssi_event {
253 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
254 RTW89_BCN_FLTR_RSSI_HIGH,
255 RTW89_BCN_FLTR_RSSI_LOW,
256 };
257
258 #define FWDL_SECTION_MAX_NUM 10
259 #define FWDL_SECTION_CHKSUM_LEN 8
260 #define FWDL_SECTION_PER_PKT_LEN 2020
261
262 struct rtw89_fw_hdr_section_info {
263 u8 redl;
264 const u8 *addr;
265 u32 len;
266 u32 dladdr;
267 u32 mssc;
268 u8 type;
269 bool ignore;
270 const u8 *key_addr;
271 u32 key_len;
272 u32 key_idx;
273 };
274
275 struct rtw89_fw_bin_info {
276 u8 section_num;
277 u32 hdr_len;
278 bool dynamic_hdr_en;
279 u32 dynamic_hdr_len;
280 bool dsp_checksum;
281 bool secure_section_exist;
282 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
283 };
284
285 struct rtw89_fw_macid_pause_grp {
286 __le32 pause_grp[4];
287 __le32 mask_grp[4];
288 } __packed;
289
290 struct rtw89_fw_macid_pause_sleep_grp {
291 struct {
292 __le32 pause_grp[4];
293 __le32 pause_mask_grp[4];
294 __le32 sleep_grp[4];
295 __le32 sleep_mask_grp[4];
296 } __packed n[4];
297 } __packed;
298
299 #define RTW89_H2C_MAX_SIZE 2048
300 #define RTW89_CHANNEL_TIME 45
301 #define RTW89_CHANNEL_TIME_6G 20
302 #define RTW89_DFS_CHAN_TIME 105
303 #define RTW89_OFF_CHAN_TIME 100
304 #define RTW89_DWELL_TIME 20
305 #define RTW89_DWELL_TIME_6G 10
306 #define RTW89_SCAN_WIDTH 0
307 #define RTW89_SCANOFLD_MAX_SSID 8
308 #define RTW89_SCANOFLD_MAX_IE_LEN 512
309 #define RTW89_SCANOFLD_PKT_NONE 0xFF
310 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
311 #define RTW89_CHAN_INVALID 0xFF
312 #define RTW89_MAC_CHINFO_SIZE 28
313 #define RTW89_SCAN_LIST_GUARD 4
314 #define RTW89_SCAN_LIST_LIMIT \
315 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
316
317 #define RTW89_BCN_LOSS_CNT 10
318
319 struct rtw89_mac_chinfo {
320 u8 period;
321 u8 dwell_time;
322 u8 central_ch;
323 u8 pri_ch;
324 u8 bw:3;
325 u8 notify_action:5;
326 u8 num_pkt:4;
327 u8 tx_pkt:1;
328 u8 pause_data:1;
329 u8 ch_band:2;
330 u8 probe_id;
331 u8 dfs_ch:1;
332 u8 tx_null:1;
333 u8 rand_seq_num:1;
334 u8 cfg_tx_pwr:1;
335 u8 rsvd0: 4;
336 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
337 u16 tx_pwr_idx;
338 u8 rsvd1;
339 struct list_head list;
340 bool is_psc;
341 };
342
343 struct rtw89_mac_chinfo_be {
344 u8 period;
345 u8 dwell_time;
346 u8 central_ch;
347 u8 pri_ch;
348 u8 bw:3;
349 u8 ch_band:2;
350 u8 dfs_ch:1;
351 u8 pause_data:1;
352 u8 tx_null:1;
353 u8 rand_seq_num:1;
354 u8 notify_action:5;
355 u8 probe_id;
356 u8 leave_crit;
357 u8 chkpt_timer;
358 u8 leave_time;
359 u8 leave_th;
360 u16 tx_pkt_ctrl;
361 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
362 u8 sw_def;
363 u16 fw_probe0_ssids;
364 u16 fw_probe0_shortssids;
365 u16 fw_probe0_bssids;
366
367 struct list_head list;
368 bool is_psc;
369 };
370
371 struct rtw89_pktofld_info {
372 struct list_head list;
373 u8 id;
374 bool wildcard_6ghz;
375
376 /* Below fields are for WiFi 6 chips 6 GHz RNR use only */
377 u8 ssid[IEEE80211_MAX_SSID_LEN];
378 u8 ssid_len;
379 u8 bssid[ETH_ALEN];
380 u16 channel_6ghz;
381 bool cancel;
382 };
383
384 struct rtw89_h2c_ra {
385 __le32 w0;
386 __le32 w1;
387 __le32 w2;
388 __le32 w3;
389 } __packed;
390
391 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
392 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
393 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
394 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
395 #define RTW89_H2C_RA_W0_DCM BIT(16)
396 #define RTW89_H2C_RA_W0_ER BIT(17)
397 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
398 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
399 #define RTW89_H2C_RA_W0_SGI BIT(21)
400 #define RTW89_H2C_RA_W0_LDPC BIT(22)
401 #define RTW89_H2C_RA_W0_STBC BIT(23)
402 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
403 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
404 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
405 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
406 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
407 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
408 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
409 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
410 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
411 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
412 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
413 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
414 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
415 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
416 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
417 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
418 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
419
420 struct rtw89_h2c_ra_v1 {
421 struct rtw89_h2c_ra v0;
422 __le32 w4;
423 __le32 w5;
424 } __packed;
425
426 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
427 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
428 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
429 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
430
RTW89_SET_FWCMD_SEC_IDX(void * cmd,u32 val)431 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
432 {
433 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
434 }
435
RTW89_SET_FWCMD_SEC_OFFSET(void * cmd,u32 val)436 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
437 {
438 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
439 }
440
RTW89_SET_FWCMD_SEC_LEN(void * cmd,u32 val)441 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
442 {
443 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
444 }
445
RTW89_SET_FWCMD_SEC_TYPE(void * cmd,u32 val)446 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
447 {
448 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
449 }
450
RTW89_SET_FWCMD_SEC_EXT_KEY(void * cmd,u32 val)451 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
452 {
453 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
454 }
455
RTW89_SET_FWCMD_SEC_SPP_MODE(void * cmd,u32 val)456 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
457 {
458 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
459 }
460
RTW89_SET_FWCMD_SEC_KEY0(void * cmd,u32 val)461 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
462 {
463 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
464 }
465
RTW89_SET_FWCMD_SEC_KEY1(void * cmd,u32 val)466 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
467 {
468 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
469 }
470
RTW89_SET_FWCMD_SEC_KEY2(void * cmd,u32 val)471 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
472 {
473 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
474 }
475
RTW89_SET_FWCMD_SEC_KEY3(void * cmd,u32 val)476 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
477 {
478 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
479 }
480
RTW89_SET_EDCA_SEL(void * cmd,u32 val)481 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
482 {
483 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
484 }
485
RTW89_SET_EDCA_BAND(void * cmd,u32 val)486 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
487 {
488 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
489 }
490
RTW89_SET_EDCA_WMM(void * cmd,u32 val)491 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
492 {
493 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
494 }
495
RTW89_SET_EDCA_AC(void * cmd,u32 val)496 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
497 {
498 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
499 }
500
RTW89_SET_EDCA_PARAM(void * cmd,u32 val)501 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
502 {
503 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
504 }
505 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
506 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
507 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
508 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
509
510 #define FWDL_SECURITY_SECTION_TYPE 9
511 #define FWDL_SECURITY_SIGLEN 512
512 #define FWDL_SECURITY_CHKSUM_LEN 8
513
514 struct rtw89_fw_dynhdr_sec {
515 __le32 w0;
516 u8 content[];
517 } __packed;
518
519 struct rtw89_fw_dynhdr_hdr {
520 __le32 hdr_len;
521 __le32 setcion_count;
522 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
523 } __packed;
524
525 struct rtw89_fw_hdr_section {
526 __le32 w0;
527 __le32 w1;
528 __le32 w2;
529 __le32 w3;
530 } __packed;
531
532 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
533 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
534 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
535 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
536 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
537 #define FWSECTION_HDR_W1_REDL BIT(29)
538 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
539
540 struct rtw89_fw_hdr {
541 __le32 w0;
542 __le32 w1;
543 __le32 w2;
544 __le32 w3;
545 __le32 w4;
546 __le32 w5;
547 __le32 w6;
548 __le32 w7;
549 struct rtw89_fw_hdr_section sections[];
550 /* struct rtw89_fw_dynhdr_hdr (optional) */
551 } __packed;
552
553 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
554 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
555 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
556 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
557 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
558 #define FW_HDR_W3_LEN GENMASK(23, 16)
559 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
560 #define FW_HDR_W4_MONTH GENMASK(7, 0)
561 #define FW_HDR_W4_DATE GENMASK(15, 8)
562 #define FW_HDR_W4_HOUR GENMASK(23, 16)
563 #define FW_HDR_W4_MIN GENMASK(31, 24)
564 #define FW_HDR_W5_YEAR GENMASK(31, 0)
565 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
566 #define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
567 #define FW_HDR_W7_DYN_HDR BIT(16)
568 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
569
570 struct rtw89_fw_hdr_section_v1 {
571 __le32 w0;
572 __le32 w1;
573 __le32 w2;
574 __le32 w3;
575 } __packed;
576
577 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
578 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
579 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
580 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
581 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
582 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
583 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
584 #define FORMATTED_MSSC 0xFF
585 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
586
587 struct rtw89_fw_hdr_v1 {
588 __le32 w0;
589 __le32 w1;
590 __le32 w2;
591 __le32 w3;
592 __le32 w4;
593 __le32 w5;
594 __le32 w6;
595 __le32 w7;
596 __le32 w8;
597 __le32 w9;
598 __le32 w10;
599 __le32 w11;
600 struct rtw89_fw_hdr_section_v1 sections[];
601 } __packed;
602
603 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
604 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
605 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
606 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
607 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
608 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
609 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
610 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
611 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
612 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
613 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
614 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
615 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
616 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
617 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
618 #define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
619 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
620
621 enum rtw89_fw_mss_pool_rmp_tbl_type {
622 MSS_POOL_RMP_TBL_BITMASK = 0x0,
623 MSS_POOL_RMP_TBL_RECORD = 0x1,
624 };
625
626 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
627
628 struct rtw89_fw_mss_pool_hdr {
629 u8 signature[8]; /* equal to mss_signature[] */
630 __le32 rmp_tbl_offset;
631 __le32 key_raw_offset;
632 u8 defen;
633 u8 rsvd[3];
634 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
635 u8 mssdev_max;
636 __le16 keypair_num;
637 __le16 msscust_max;
638 __le16 msskey_num_max;
639 __le32 rsvd3;
640 u8 rmp_tbl[];
641 } __packed;
642
643 union rtw89_fw_section_mssc_content {
644 struct {
645 u8 pad[0x20];
646 u8 bit_in_chip_list;
647 u8 ver;
648 } __packed blacklist;
649 struct {
650 u8 pad[58];
651 __le32 v;
652 } __packed sb_sel_ver;
653 struct {
654 u8 pad[60];
655 __le16 v;
656 } __packed key_sign_len;
657 } __packed;
658
659 struct rtw89_fw_blacklist {
660 u8 ver;
661 u8 list[32];
662 };
663
664 extern const struct rtw89_fw_blacklist rtw89_fw_blacklist_default;
665
SET_CTRL_INFO_MACID(void * table,u32 val)666 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
667 {
668 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
669 }
670
SET_CTRL_INFO_OPERATION(void * table,u32 val)671 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
672 {
673 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
674 }
675 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
SET_CMC_TBL_DATARATE(void * table,u32 val)676 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
677 {
678 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
679 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
680 GENMASK(8, 0));
681 }
682 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
SET_CMC_TBL_FORCE_TXOP(void * table,u32 val)683 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
684 {
685 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
686 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
687 BIT(9));
688 }
689 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
SET_CMC_TBL_DATA_BW(void * table,u32 val)690 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
691 {
692 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
693 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
694 GENMASK(11, 10));
695 }
696 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_DATA_GI_LTF(void * table,u32 val)697 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
698 {
699 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
700 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
701 GENMASK(14, 12));
702 }
703 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
SET_CMC_TBL_DARF_TC_INDEX(void * table,u32 val)704 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
705 {
706 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
707 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
708 BIT(15));
709 }
710 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
SET_CMC_TBL_ARFR_CTRL(void * table,u32 val)711 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
712 {
713 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
714 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
715 GENMASK(19, 16));
716 }
717 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
SET_CMC_TBL_ACQ_RPT_EN(void * table,u32 val)718 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
719 {
720 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
721 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
722 BIT(20));
723 }
724 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
SET_CMC_TBL_MGQ_RPT_EN(void * table,u32 val)725 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
726 {
727 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
728 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
729 BIT(21));
730 }
731 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
SET_CMC_TBL_ULQ_RPT_EN(void * table,u32 val)732 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
733 {
734 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
735 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
736 BIT(22));
737 }
738 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
SET_CMC_TBL_TWTQ_RPT_EN(void * table,u32 val)739 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
740 {
741 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
742 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
743 BIT(23));
744 }
745 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
SET_CMC_TBL_DISRTSFB(void * table,u32 val)746 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
747 {
748 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
749 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
750 BIT(25));
751 }
752 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
SET_CMC_TBL_DISDATAFB(void * table,u32 val)753 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
754 {
755 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
756 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
757 BIT(26));
758 }
759 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
SET_CMC_TBL_TRYRATE(void * table,u32 val)760 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
761 {
762 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
763 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
764 BIT(27));
765 }
766 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
SET_CMC_TBL_AMPDU_DENSITY(void * table,u32 val)767 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
768 {
769 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
770 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
771 GENMASK(31, 28));
772 }
773 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void * table,u32 val)774 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
775 {
776 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
777 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
778 GENMASK(8, 0));
779 }
780 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
SET_CMC_TBL_AMPDU_TIME_SEL(void * table,u32 val)781 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
782 {
783 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
784 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
785 BIT(9));
786 }
787 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
SET_CMC_TBL_AMPDU_LEN_SEL(void * table,u32 val)788 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
789 {
790 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
791 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
792 BIT(10));
793 }
794 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void * table,u32 val)795 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
796 {
797 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
798 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
799 BIT(11));
800 }
801 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
SET_CMC_TBL_RTS_TXCNT_LMT(void * table,u32 val)802 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
803 {
804 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
805 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
806 GENMASK(15, 12));
807 }
808 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
SET_CMC_TBL_RTSRATE(void * table,u32 val)809 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
810 {
811 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
812 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
813 GENMASK(24, 16));
814 }
815 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
SET_CMC_TBL_VCS_STBC(void * table,u32 val)816 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
817 {
818 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
819 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
820 BIT(27));
821 }
822 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void * table,u32 val)823 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
824 {
825 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
826 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
827 GENMASK(31, 28));
828 }
829 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
SET_CMC_TBL_DATA_TX_CNT_LMT(void * table,u32 val)830 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
831 {
832 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
833 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
834 GENMASK(5, 0));
835 }
836 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void * table,u32 val)837 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
838 {
839 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
840 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
841 BIT(6));
842 }
843 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
SET_CMC_TBL_MAX_AGG_NUM_SEL(void * table,u32 val)844 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
845 {
846 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
847 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
848 BIT(7));
849 }
850 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
SET_CMC_TBL_RTS_EN(void * table,u32 val)851 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
852 {
853 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
854 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
855 BIT(8));
856 }
857 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
SET_CMC_TBL_CTS2SELF_EN(void * table,u32 val)858 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
859 {
860 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
861 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
862 BIT(9));
863 }
864 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
SET_CMC_TBL_CCA_RTS(void * table,u32 val)865 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
866 {
867 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
868 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
869 GENMASK(11, 10));
870 }
871 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
SET_CMC_TBL_HW_RTS_EN(void * table,u32 val)872 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
873 {
874 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
875 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
876 BIT(12));
877 }
878 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
SET_CMC_TBL_RTS_DROP_DATA_MODE(void * table,u32 val)879 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
880 {
881 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
882 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
883 GENMASK(14, 13));
884 }
885 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
SET_CMC_TBL_AMPDU_MAX_LEN(void * table,u32 val)886 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
887 {
888 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
889 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
890 GENMASK(26, 16));
891 }
892 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
SET_CMC_TBL_UL_MU_DIS(void * table,u32 val)893 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
894 {
895 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
896 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
897 BIT(27));
898 }
899 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
SET_CMC_TBL_AMPDU_MAX_TIME(void * table,u32 val)900 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
901 {
902 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
903 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
904 GENMASK(31, 28));
905 }
906 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
SET_CMC_TBL_MAX_AGG_NUM(void * table,u32 val)907 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
908 {
909 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
910 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
911 GENMASK(7, 0));
912 }
913 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
SET_CMC_TBL_BA_BMAP(void * table,u32 val)914 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
915 {
916 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
917 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
918 GENMASK(9, 8));
919 }
920 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VO_LFTIME_SEL(void * table,u32 val)921 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
922 {
923 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
924 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
925 GENMASK(18, 16));
926 }
927 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VI_LFTIME_SEL(void * table,u32 val)928 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
929 {
930 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
931 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
932 GENMASK(21, 19));
933 }
934 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BE_LFTIME_SEL(void * table,u32 val)935 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
936 {
937 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
938 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
939 GENMASK(24, 22));
940 }
941 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BK_LFTIME_SEL(void * table,u32 val)942 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
943 {
944 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
945 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
946 GENMASK(27, 25));
947 }
948 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
SET_CMC_TBL_SECTYPE(void * table,u32 val)949 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
950 {
951 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
952 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
953 GENMASK(31, 28));
954 }
955 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
SET_CMC_TBL_MULTI_PORT_ID(void * table,u32 val)956 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
957 {
958 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
959 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
960 GENMASK(2, 0));
961 }
962 #define SET_CMC_TBL_MASK_BMC BIT(0)
SET_CMC_TBL_BMC(void * table,u32 val)963 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
964 {
965 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
966 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
967 BIT(3));
968 }
969 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
SET_CMC_TBL_MBSSID(void * table,u32 val)970 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
971 {
972 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
973 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
974 GENMASK(7, 4));
975 }
976 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
SET_CMC_TBL_NAVUSEHDR(void * table,u32 val)977 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
978 {
979 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
980 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
981 BIT(8));
982 }
983 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
SET_CMC_TBL_TXPWR_MODE(void * table,u32 val)984 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
985 {
986 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
987 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
988 GENMASK(11, 9));
989 }
990 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
SET_CMC_TBL_DATA_DCM(void * table,u32 val)991 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
992 {
993 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
994 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
995 BIT(12));
996 }
997 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
SET_CMC_TBL_DATA_ER(void * table,u32 val)998 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
999 {
1000 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
1001 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
1002 BIT(13));
1003 }
1004 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
SET_CMC_TBL_DATA_LDPC(void * table,u32 val)1005 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
1006 {
1007 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
1008 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
1009 BIT(14));
1010 }
1011 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
SET_CMC_TBL_DATA_STBC(void * table,u32 val)1012 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
1013 {
1014 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1015 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
1016 BIT(15));
1017 }
1018 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
SET_CMC_TBL_A_CTRL_BQR(void * table,u32 val)1019 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
1020 {
1021 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1022 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
1023 BIT(16));
1024 }
1025 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
SET_CMC_TBL_A_CTRL_UPH(void * table,u32 val)1026 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
1027 {
1028 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1029 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
1030 BIT(17));
1031 }
1032 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
SET_CMC_TBL_A_CTRL_BSR(void * table,u32 val)1033 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
1034 {
1035 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1036 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
1037 BIT(18));
1038 }
1039 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
SET_CMC_TBL_A_CTRL_CAS(void * table,u32 val)1040 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
1041 {
1042 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1043 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1044 BIT(19));
1045 }
1046 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
SET_CMC_TBL_DATA_BW_ER(void * table,u32 val)1047 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1048 {
1049 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1050 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1051 BIT(20));
1052 }
1053 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
SET_CMC_TBL_LSIG_TXOP_EN(void * table,u32 val)1054 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1055 {
1056 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1057 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1058 BIT(21));
1059 }
1060 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
SET_CMC_TBL_CTRL_CNT_VLD(void * table,u32 val)1061 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1062 {
1063 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1064 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1065 BIT(27));
1066 }
1067 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
SET_CMC_TBL_CTRL_CNT(void * table,u32 val)1068 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1069 {
1070 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
1071 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1072 GENMASK(31, 28));
1073 }
1074 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
SET_CMC_TBL_RESP_REF_RATE(void * table,u32 val)1075 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1076 {
1077 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
1078 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1079 GENMASK(8, 0));
1080 }
1081 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
SET_CMC_TBL_ALL_ACK_SUPPORT(void * table,u32 val)1082 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1083 {
1084 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1085 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1086 BIT(12));
1087 }
1088 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void * table,u32 val)1089 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1090 {
1091 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1092 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1093 BIT(13));
1094 }
1095 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
SET_CMC_TBL_NTX_PATH_EN(void * table,u32 val)1096 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1097 {
1098 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1099 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1100 GENMASK(19, 16));
1101 }
1102 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_A(void * table,u32 val)1103 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1104 {
1105 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1106 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1107 GENMASK(21, 20));
1108 }
1109 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_B(void * table,u32 val)1110 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1111 {
1112 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1113 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1114 GENMASK(23, 22));
1115 }
1116 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_C(void * table,u32 val)1117 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1118 {
1119 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1120 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1121 GENMASK(25, 24));
1122 }
1123 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_D(void * table,u32 val)1124 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1125 {
1126 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1127 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1128 GENMASK(27, 26));
1129 }
1130 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
SET_CMC_TBL_ANTSEL_A(void * table,u32 val)1131 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1132 {
1133 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1134 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1135 BIT(28));
1136 }
1137 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
SET_CMC_TBL_ANTSEL_B(void * table,u32 val)1138 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1139 {
1140 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1141 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1142 BIT(29));
1143 }
1144 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
SET_CMC_TBL_ANTSEL_C(void * table,u32 val)1145 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1146 {
1147 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1148 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1149 BIT(30));
1150 }
1151 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
SET_CMC_TBL_ANTSEL_D(void * table,u32 val)1152 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1153 {
1154 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1155 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1156 BIT(31));
1157 }
1158
1159 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void * table,u32 val)1160 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1161 {
1162 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1163 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1164 GENMASK(1, 0));
1165 }
1166
SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void * table,u32 val)1167 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1168 {
1169 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1170 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1171 GENMASK(3, 2));
1172 }
1173
SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void * table,u32 val)1174 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1175 {
1176 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1177 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1178 GENMASK(5, 4));
1179 }
1180
SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void * table,u32 val)1181 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1182 {
1183 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1184 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1185 GENMASK(7, 6));
1186 }
1187
1188 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
SET_CMC_TBL_ADDR_CAM_INDEX(void * table,u32 val)1189 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1190 {
1191 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1192 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1193 GENMASK(7, 0));
1194 }
1195 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
SET_CMC_TBL_PAID(void * table,u32 val)1196 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1197 {
1198 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1199 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1200 GENMASK(16, 8));
1201 }
1202 #define SET_CMC_TBL_MASK_ULDL BIT(0)
SET_CMC_TBL_ULDL(void * table,u32 val)1203 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1204 {
1205 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1206 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1207 BIT(17));
1208 }
1209 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
SET_CMC_TBL_DOPPLER_CTRL(void * table,u32 val)1210 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1211 {
1212 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1213 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1214 GENMASK(19, 18));
1215 }
SET_CMC_TBL_NOMINAL_PKT_PADDING(void * table,u32 val)1216 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1217 {
1218 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1219 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1220 GENMASK(21, 20));
1221 }
1222
SET_CMC_TBL_NOMINAL_PKT_PADDING40(void * table,u32 val)1223 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1224 {
1225 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1226 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1227 GENMASK(23, 22));
1228 }
1229 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
SET_CMC_TBL_TXPWR_TOLERENCE(void * table,u32 val)1230 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1231 {
1232 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1233 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1234 GENMASK(27, 24));
1235 }
1236
SET_CMC_TBL_NOMINAL_PKT_PADDING80(void * table,u32 val)1237 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1238 {
1239 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1240 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1241 GENMASK(31, 30));
1242 }
1243 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
SET_CMC_TBL_NC(void * table,u32 val)1244 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1245 {
1246 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1247 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1248 GENMASK(2, 0));
1249 }
1250 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
SET_CMC_TBL_NR(void * table,u32 val)1251 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1252 {
1253 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1254 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1255 GENMASK(5, 3));
1256 }
1257 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
SET_CMC_TBL_NG(void * table,u32 val)1258 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1259 {
1260 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1261 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1262 GENMASK(7, 6));
1263 }
1264 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
SET_CMC_TBL_CB(void * table,u32 val)1265 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1266 {
1267 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1268 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1269 GENMASK(9, 8));
1270 }
1271 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
SET_CMC_TBL_CS(void * table,u32 val)1272 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1273 {
1274 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1275 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1276 GENMASK(11, 10));
1277 }
1278 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
SET_CMC_TBL_CSI_TXBF_EN(void * table,u32 val)1279 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1280 {
1281 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1282 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1283 BIT(12));
1284 }
1285 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
SET_CMC_TBL_CSI_STBC_EN(void * table,u32 val)1286 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1287 {
1288 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1289 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1290 BIT(13));
1291 }
1292 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
SET_CMC_TBL_CSI_LDPC_EN(void * table,u32 val)1293 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1294 {
1295 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1296 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1297 BIT(14));
1298 }
1299 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
SET_CMC_TBL_CSI_PARA_EN(void * table,u32 val)1300 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1301 {
1302 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1303 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1304 BIT(15));
1305 }
1306 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
SET_CMC_TBL_CSI_FIX_RATE(void * table,u32 val)1307 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1308 {
1309 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1310 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1311 GENMASK(24, 16));
1312 }
1313 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_CSI_GI_LTF(void * table,u32 val)1314 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1315 {
1316 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1317 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1318 GENMASK(27, 25));
1319 }
1320
SET_CMC_TBL_NOMINAL_PKT_PADDING160(void * table,u32 val)1321 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1322 {
1323 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1324 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1325 GENMASK(29, 28));
1326 }
1327
1328 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
SET_CMC_TBL_CSI_BW(void * table,u32 val)1329 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1330 {
1331 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1332 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1333 GENMASK(31, 30));
1334 }
1335
1336 struct rtw89_h2c_cctlinfo_ud_g7 {
1337 __le32 c0;
1338 __le32 w0;
1339 __le32 w1;
1340 __le32 w2;
1341 __le32 w3;
1342 __le32 w4;
1343 __le32 w5;
1344 __le32 w6;
1345 __le32 w7;
1346 __le32 w8;
1347 __le32 w9;
1348 __le32 w10;
1349 __le32 w11;
1350 __le32 w12;
1351 __le32 w13;
1352 __le32 w14;
1353 __le32 w15;
1354 __le32 m0;
1355 __le32 m1;
1356 __le32 m2;
1357 __le32 m3;
1358 __le32 m4;
1359 __le32 m5;
1360 __le32 m6;
1361 __le32 m7;
1362 __le32 m8;
1363 __le32 m9;
1364 __le32 m10;
1365 __le32 m11;
1366 __le32 m12;
1367 __le32 m13;
1368 __le32 m14;
1369 __le32 m15;
1370 } __packed;
1371
1372 #define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1373 #define CCTLINFO_G7_C0_OP BIT(7)
1374
1375 #define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1376 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1377 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1378 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1379 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1380 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1381 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1382 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1383 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1384 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1385 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1386 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1387 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1388 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1389 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1390 #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1391 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1392 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1393 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1394 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1395 #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1396 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1397 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1398 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1399 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1400 #define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1401 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1402 #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1403 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1404 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1405 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1406 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1407 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1408 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1409 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1410 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1411 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1412 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1413 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1414 #define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1415 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1416 #define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1417 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1418 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1419 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1420 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1421 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1422 #define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1423 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1424 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1425 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1426 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1427 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1428 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1429 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1430 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1431 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1432 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1433 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1434 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1435 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1436 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1437 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1438 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1439 #define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1440 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1441 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1442 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1443 #define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1444 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1445 #define CCTLINFO_G7_W6_ULDL BIT(31)
1446 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1447 #define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1448 #define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1449 #define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1450 #define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1451 #define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1452 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1453 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1454 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1455 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1456 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1457 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1458 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1459 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1460 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1461 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1462 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1463 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1464 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1465 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1466 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1467 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1468 #define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1469 /* W9~13 are reserved */
1470 #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1471 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1472 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1473 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1474 #define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1475 #define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1476 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1477 #define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1478
1479 struct rtw89_h2c_bcn_upd {
1480 __le32 w0;
1481 __le32 w1;
1482 __le32 w2;
1483 } __packed;
1484
1485 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1486 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1487 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1488 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1489 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1490 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1491 #define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1492 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1493 #define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1494 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1495 #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1496 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1497 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1498 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1499 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1500 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1501 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1502 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1503 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1504 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1505
1506 struct rtw89_h2c_bcn_upd_be {
1507 __le32 w0;
1508 __le32 w1;
1509 __le32 w2;
1510 __le32 w3;
1511 __le32 w4;
1512 __le32 w5;
1513 __le32 w6;
1514 __le32 w7;
1515 __le32 w8;
1516 __le32 w9;
1517 __le32 w10;
1518 __le32 w11;
1519 __le32 w12;
1520 __le32 w13;
1521 __le32 w14;
1522 __le32 w15;
1523 __le32 w16;
1524 __le32 w17;
1525 __le32 w18;
1526 __le32 w19;
1527 __le32 w20;
1528 __le32 w21;
1529 __le32 w22;
1530 __le32 w23;
1531 __le32 w24;
1532 __le32 w25;
1533 __le32 w26;
1534 __le32 w27;
1535 __le32 w28;
1536 __le32 w29;
1537 } __packed;
1538
1539 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1540 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1541 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1542 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1543 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1544 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1545 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1546 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1547 #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1548 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1549 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1550 #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1551 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1552 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1553 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1554 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1555 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1556 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1557 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1558 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1559 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1560 #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1561 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1562 #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1563 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1564 #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1565 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1566 #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1567 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1568 #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1569 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1570 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1571
SET_FWROLE_MAINTAIN_MACID(void * h2c,u32 val)1572 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1573 {
1574 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1575 }
1576
SET_FWROLE_MAINTAIN_SELF_ROLE(void * h2c,u32 val)1577 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1578 {
1579 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1580 }
1581
SET_FWROLE_MAINTAIN_UPD_MODE(void * h2c,u32 val)1582 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1583 {
1584 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1585 }
1586
SET_FWROLE_MAINTAIN_WIFI_ROLE(void * h2c,u32 val)1587 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1588 {
1589 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1590 }
1591
1592 enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1593 RTW89_FW_N_AC_STA = 0,
1594 RTW89_FW_AX_STA = 1,
1595 RTW89_FW_BE_STA = 2,
1596 };
1597
1598 struct rtw89_h2c_join {
1599 __le32 w0;
1600 } __packed;
1601
1602 struct rtw89_h2c_join_v1 {
1603 __le32 w0;
1604 __le32 w1;
1605 __le32 w2;
1606 } __packed;
1607
1608 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1609 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1610 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1611 #define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1612 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1613 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1614 #define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1615 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1616 #define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1617 #define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1618 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1619 #define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1620 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1621 #define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1622 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1623 #define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1624 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1625 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1626 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1627 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1628 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1629 #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1630 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1631 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1632
1633 struct rtw89_h2c_notify_dbcc {
1634 __le32 w0;
1635 } __packed;
1636
1637 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1638
SET_GENERAL_PKT_MACID(void * h2c,u32 val)1639 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1640 {
1641 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1642 }
1643
SET_GENERAL_PKT_PROBRSP_ID(void * h2c,u32 val)1644 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1645 {
1646 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1647 }
1648
SET_GENERAL_PKT_PSPOLL_ID(void * h2c,u32 val)1649 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1650 {
1651 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1652 }
1653
SET_GENERAL_PKT_NULL_ID(void * h2c,u32 val)1654 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1655 {
1656 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1657 }
1658
SET_GENERAL_PKT_QOS_NULL_ID(void * h2c,u32 val)1659 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1660 {
1661 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1662 }
1663
SET_GENERAL_PKT_CTS2SELF_ID(void * h2c,u32 val)1664 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1665 {
1666 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1667 }
1668
SET_LOG_CFG_LEVEL(void * h2c,u32 val)1669 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1670 {
1671 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1672 }
1673
SET_LOG_CFG_PATH(void * h2c,u32 val)1674 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1675 {
1676 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1677 }
1678
SET_LOG_CFG_COMP(void * h2c,u32 val)1679 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1680 {
1681 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1682 }
1683
SET_LOG_CFG_COMP_EXT(void * h2c,u32 val)1684 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1685 {
1686 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1687 }
1688
1689 struct rtw89_h2c_ba_cam {
1690 __le32 w0;
1691 __le32 w1;
1692 } __packed;
1693
1694 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1695 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1696 #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1697 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1698 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1699 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1700 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1701 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1702 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1703 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1704 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1705
1706 struct rtw89_h2c_ba_cam_v1 {
1707 __le32 w0;
1708 __le32 w1;
1709 } __packed;
1710
1711 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1712 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1713 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1714 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1715 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1716 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1717 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1718 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1719 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1720 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1721 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1722
1723 struct rtw89_h2c_ba_cam_init {
1724 __le32 w0;
1725 } __packed;
1726
1727 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1728 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1729 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1730
SET_LPS_PARM_MACID(void * h2c,u32 val)1731 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1732 {
1733 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1734 }
1735
SET_LPS_PARM_PSMODE(void * h2c,u32 val)1736 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1737 {
1738 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1739 }
1740
SET_LPS_PARM_RLBM(void * h2c,u32 val)1741 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1742 {
1743 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1744 }
1745
SET_LPS_PARM_SMARTPS(void * h2c,u32 val)1746 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1747 {
1748 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1749 }
1750
SET_LPS_PARM_AWAKEINTERVAL(void * h2c,u32 val)1751 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1752 {
1753 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1754 }
1755
SET_LPS_PARM_VOUAPSD(void * h2c,u32 val)1756 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1757 {
1758 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1759 }
1760
SET_LPS_PARM_VIUAPSD(void * h2c,u32 val)1761 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1762 {
1763 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1764 }
1765
SET_LPS_PARM_BEUAPSD(void * h2c,u32 val)1766 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1767 {
1768 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1769 }
1770
SET_LPS_PARM_BKUAPSD(void * h2c,u32 val)1771 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1772 {
1773 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1774 }
1775
SET_LPS_PARM_LASTRPWM(void * h2c,u32 val)1776 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1777 {
1778 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1779 }
1780
1781 struct rtw89_h2c_lps_ch_info {
1782 struct {
1783 u8 pri_ch;
1784 u8 central_ch;
1785 u8 bw;
1786 u8 band;
1787 } __packed info[2];
1788
1789 __le32 mlo_dbcc_mode_lps;
1790 } __packed;
1791
RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void * cmd,u32 val)1792 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1793 {
1794 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1795 }
1796
RTW89_SET_FWCMD_PKT_DROP_SEL(void * cmd,u32 val)1797 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1798 {
1799 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1800 }
1801
RTW89_SET_FWCMD_PKT_DROP_MACID(void * cmd,u32 val)1802 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1803 {
1804 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1805 }
1806
RTW89_SET_FWCMD_PKT_DROP_BAND(void * cmd,u32 val)1807 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1808 {
1809 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1810 }
1811
RTW89_SET_FWCMD_PKT_DROP_PORT(void * cmd,u32 val)1812 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1813 {
1814 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1815 }
1816
RTW89_SET_FWCMD_PKT_DROP_MBSSID(void * cmd,u32 val)1817 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1818 {
1819 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1820 }
1821
RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void * cmd,u32 val)1822 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1823 {
1824 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1825 }
1826
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void * cmd,u32 val)1827 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1828 {
1829 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1830 }
1831
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void * cmd,u32 val)1832 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1833 {
1834 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1835 }
1836
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void * cmd,u32 val)1837 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1838 {
1839 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1840 }
1841
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void * cmd,u32 val)1842 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1843 {
1844 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1845 }
1846
RTW89_SET_KEEP_ALIVE_ENABLE(void * h2c,u32 val)1847 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1848 {
1849 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1850 }
1851
RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void * h2c,u32 val)1852 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1853 {
1854 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1855 }
1856
RTW89_SET_KEEP_ALIVE_PERIOD(void * h2c,u32 val)1857 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1858 {
1859 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1860 }
1861
RTW89_SET_KEEP_ALIVE_MACID(void * h2c,u32 val)1862 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1863 {
1864 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1865 }
1866
RTW89_SET_DISCONNECT_DETECT_ENABLE(void * h2c,u32 val)1867 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1868 {
1869 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1870 }
1871
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void * h2c,u32 val)1872 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1873 {
1874 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1875 }
1876
RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void * h2c,u32 val)1877 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1878 {
1879 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1880 }
1881
RTW89_SET_DISCONNECT_DETECT_MAC_ID(void * h2c,u32 val)1882 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1883 {
1884 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1885 }
1886
RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void * h2c,u32 val)1887 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1888 {
1889 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1890 }
1891
RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void * h2c,u32 val)1892 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1893 {
1894 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1895 }
1896
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void * h2c,u32 val)1897 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1898 {
1899 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1900 }
1901
1902 struct rtw89_h2c_wow_global {
1903 __le32 w0;
1904 struct rtw89_wow_key_info key_info;
1905 } __packed;
1906
1907 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1908 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1909 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1910 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1911 #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
1912 #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
1913 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
1914
1915 #define RTW89_MAX_SUPPORT_NL_NUM 16
1916 struct rtw89_h2c_cfg_nlo {
1917 __le32 w0;
1918 u8 nlo_cnt;
1919 u8 rsvd[3];
1920 __le32 patterncheck;
1921 __le32 rsvd1;
1922 __le32 rsvd2;
1923 u8 ssid_len[RTW89_MAX_SUPPORT_NL_NUM];
1924 u8 chiper[RTW89_MAX_SUPPORT_NL_NUM];
1925 u8 rsvd3[24];
1926 u8 ssid[RTW89_MAX_SUPPORT_NL_NUM][IEEE80211_MAX_SSID_LEN];
1927 } __packed;
1928
1929 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
1930 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
1931 #define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
1932
RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void * h2c,u32 val)1933 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
1934 {
1935 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1936 }
1937
RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void * h2c,u32 val)1938 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
1939 {
1940 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1941 }
1942
RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void * h2c,u32 val)1943 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
1944 {
1945 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1946 }
1947
RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void * h2c,u32 val)1948 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
1949 {
1950 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1951 }
1952
RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void * h2c,u32 val)1953 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
1954 {
1955 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
1956 }
1957
RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void * h2c,u32 val)1958 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
1959 {
1960 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
1961 }
1962
RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void * h2c,u32 val)1963 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
1964 {
1965 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
1966 }
1967
RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void * h2c,u32 val)1968 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
1969 {
1970 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
1971 }
1972
RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void * h2c,u32 val)1973 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
1974 {
1975 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1976 }
1977
RTW89_SET_WOW_CAM_UPD_R_W(void * h2c,u32 val)1978 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
1979 {
1980 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1981 }
1982
RTW89_SET_WOW_CAM_UPD_IDX(void * h2c,u32 val)1983 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
1984 {
1985 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
1986 }
1987
RTW89_SET_WOW_CAM_UPD_WKFM1(void * h2c,u32 val)1988 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
1989 {
1990 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
1991 }
1992
RTW89_SET_WOW_CAM_UPD_WKFM2(void * h2c,u32 val)1993 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
1994 {
1995 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
1996 }
1997
RTW89_SET_WOW_CAM_UPD_WKFM3(void * h2c,u32 val)1998 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
1999 {
2000 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2001 }
2002
RTW89_SET_WOW_CAM_UPD_WKFM4(void * h2c,u32 val)2003 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2004 {
2005 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2006 }
2007
RTW89_SET_WOW_CAM_UPD_CRC(void * h2c,u32 val)2008 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2009 {
2010 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2011 }
2012
RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void * h2c,u32 val)2013 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2014 {
2015 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2016 }
2017
RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void * h2c,u32 val)2018 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2019 {
2020 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2021 }
2022
RTW89_SET_WOW_CAM_UPD_UC(void * h2c,u32 val)2023 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2024 {
2025 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2026 }
2027
RTW89_SET_WOW_CAM_UPD_MC(void * h2c,u32 val)2028 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2029 {
2030 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2031 }
2032
RTW89_SET_WOW_CAM_UPD_BC(void * h2c,u32 val)2033 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2034 {
2035 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2036 }
2037
RTW89_SET_WOW_CAM_UPD_VALID(void * h2c,u32 val)2038 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2039 {
2040 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2041 }
2042
2043 struct rtw89_h2c_wow_gtk_ofld {
2044 __le32 w0;
2045 __le32 w1;
2046 struct rtw89_wow_gtk_info gtk_info;
2047 } __packed;
2048
2049 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2050 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2051 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2052 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2053 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2054 #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2055 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2056 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2057 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2058 #define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)
2059
2060 struct rtw89_h2c_arp_offload {
2061 __le32 w0;
2062 __le32 w1;
2063 } __packed;
2064
2065 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2066 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2067 #define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2068 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2069 #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2070
2071 enum rtw89_btc_btf_h2c_class {
2072 BTFC_SET = 0x10,
2073 BTFC_GET = 0x11,
2074 BTFC_FW_EVENT = 0x12,
2075 };
2076
2077 enum rtw89_btc_btf_set {
2078 SET_REPORT_EN = 0x0,
2079 SET_SLOT_TABLE,
2080 SET_MREG_TABLE,
2081 SET_CX_POLICY,
2082 SET_GPIO_DBG,
2083 SET_DRV_INFO,
2084 SET_DRV_EVENT,
2085 SET_BT_WREG_ADDR,
2086 SET_BT_WREG_VAL,
2087 SET_BT_RREG_ADDR,
2088 SET_BT_WL_CH_INFO,
2089 SET_BT_INFO_REPORT,
2090 SET_BT_IGNORE_WLAN_ACT,
2091 SET_BT_TX_PWR,
2092 SET_BT_LNA_CONSTRAIN,
2093 SET_BT_QUERY_DEV_LIST,
2094 SET_BT_QUERY_DEV_INFO,
2095 SET_BT_PSD_REPORT,
2096 SET_H2C_TEST,
2097 SET_IOFLD_RF,
2098 SET_IOFLD_BB,
2099 SET_IOFLD_MAC,
2100 SET_IOFLD_SCBD,
2101 SET_H2C_MACRO,
2102 SET_MAX1,
2103 };
2104
2105 enum rtw89_btc_cxdrvinfo {
2106 CXDRVINFO_INIT = 0,
2107 CXDRVINFO_ROLE,
2108 CXDRVINFO_DBCC,
2109 CXDRVINFO_SMAP,
2110 CXDRVINFO_RFK,
2111 CXDRVINFO_RUN,
2112 CXDRVINFO_CTRL,
2113 CXDRVINFO_SCAN,
2114 CXDRVINFO_TRX, /* WL traffic to WL fw */
2115 CXDRVINFO_TXPWR,
2116 CXDRVINFO_FDDT,
2117 CXDRVINFO_MLO,
2118 CXDRVINFO_OSI,
2119 CXDRVINFO_MAX,
2120 };
2121
2122 enum rtw89_scan_mode {
2123 RTW89_SCAN_IMMEDIATE,
2124 RTW89_SCAN_DELAY,
2125 };
2126
2127 enum rtw89_scan_type {
2128 RTW89_SCAN_ONCE,
2129 RTW89_SCAN_NORMAL,
2130 RTW89_SCAN_NORMAL_SLOW,
2131 RTW89_SCAN_SEAMLESS,
2132 RTW89_SCAN_MAX,
2133 };
2134
RTW89_SET_FWCMD_CXHDR_TYPE(void * cmd,u8 val)2135 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2136 {
2137 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2138 }
2139
RTW89_SET_FWCMD_CXHDR_LEN(void * cmd,u8 val)2140 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2141 {
2142 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2143 }
2144
2145 struct rtw89_h2c_cxhdr {
2146 u8 type;
2147 u8 len;
2148 } __packed;
2149
2150 struct rtw89_h2c_cxhdr_v7 {
2151 u8 type;
2152 u8 ver;
2153 u8 len;
2154 } __packed;
2155
2156 struct rtw89_h2c_cxctrl_v7 {
2157 struct rtw89_h2c_cxhdr_v7 hdr;
2158 struct rtw89_btc_ctrl_v7 ctrl;
2159 } __packed;
2160
2161 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2162 #define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2163
2164 struct rtw89_btc_wl_role_info_v7_u8 {
2165 u8 connect_cnt;
2166 u8 link_mode;
2167 u8 link_mode_chg;
2168 u8 p2p_2g;
2169
2170 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
2171 } __packed;
2172
2173 struct rtw89_btc_wl_role_info_v7_u32 {
2174 __le32 role_map;
2175 __le32 mrole_type;
2176 __le32 mrole_noa_duration;
2177 __le32 dbcc_en;
2178 __le32 dbcc_chg;
2179 __le32 dbcc_2g_phy;
2180 } __packed;
2181
2182 struct rtw89_h2c_cxrole_v7 {
2183 struct rtw89_h2c_cxhdr_v7 hdr;
2184 struct rtw89_btc_wl_role_info_v7_u8 _u8;
2185 struct rtw89_btc_wl_role_info_v7_u32 _u32;
2186 } __packed;
2187
2188 struct rtw89_btc_wl_role_info_v8_u8 {
2189 u8 connect_cnt;
2190 u8 link_mode;
2191 u8 link_mode_chg;
2192 u8 p2p_2g;
2193
2194 u8 pta_req_band;
2195 u8 dbcc_en;
2196 u8 dbcc_chg;
2197 u8 dbcc_2g_phy;
2198
2199 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
2200 } __packed;
2201
2202 struct rtw89_btc_wl_role_info_v8_u32 {
2203 __le32 role_map;
2204 __le32 mrole_type;
2205 __le32 mrole_noa_duration;
2206 } __packed;
2207
2208 struct rtw89_h2c_cxrole_v8 {
2209 struct rtw89_h2c_cxhdr_v7 hdr;
2210 struct rtw89_btc_wl_role_info_v8_u8 _u8;
2211 struct rtw89_btc_wl_role_info_v8_u32 _u32;
2212 } __packed;
2213
2214 struct rtw89_h2c_cxinit {
2215 struct rtw89_h2c_cxhdr hdr;
2216 u8 ant_type;
2217 u8 ant_num;
2218 u8 ant_iso;
2219 u8 ant_info;
2220 u8 mod_rfe;
2221 u8 mod_cv;
2222 u8 mod_info;
2223 u8 mod_adie_kt;
2224 u8 wl_gch;
2225 u8 info;
2226 u8 rsvd;
2227 u8 rsvd1;
2228 } __packed;
2229
2230 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2231 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2232 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2233 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2234
2235 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2236 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2237 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2238 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2239
2240 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2241 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2242 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2243 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2244 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2245
2246 struct rtw89_h2c_cxinit_v7 {
2247 struct rtw89_h2c_cxhdr_v7 hdr;
2248 struct rtw89_btc_init_info_v7 init;
2249 } __packed;
2250
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void * cmd,u8 val)2251 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2252 {
2253 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2254 }
2255
RTW89_SET_FWCMD_CXROLE_LINK_MODE(void * cmd,u8 val)2256 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2257 {
2258 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2259 }
2260
RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void * cmd,u16 val)2261 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2262 {
2263 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2264 }
2265
RTW89_SET_FWCMD_CXROLE_ROLE_STA(void * cmd,u16 val)2266 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2267 {
2268 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2269 }
2270
RTW89_SET_FWCMD_CXROLE_ROLE_AP(void * cmd,u16 val)2271 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2272 {
2273 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2274 }
2275
RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void * cmd,u16 val)2276 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2277 {
2278 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2279 }
2280
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void * cmd,u16 val)2281 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2282 {
2283 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2284 }
2285
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void * cmd,u16 val)2286 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2287 {
2288 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2289 }
2290
RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void * cmd,u16 val)2291 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2292 {
2293 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2294 }
2295
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void * cmd,u16 val)2296 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2297 {
2298 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2299 }
2300
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void * cmd,u16 val)2301 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2302 {
2303 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2304 }
2305
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void * cmd,u16 val)2306 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2307 {
2308 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2309 }
2310
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void * cmd,u16 val)2311 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2312 {
2313 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2314 }
2315
RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void * cmd,u16 val)2316 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2317 {
2318 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2319 }
2320
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void * cmd,u8 val,int n,u8 offset)2321 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2322 {
2323 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2324 }
2325
RTW89_SET_FWCMD_CXROLE_ACT_PID(void * cmd,u8 val,int n,u8 offset)2326 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2327 {
2328 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2329 }
2330
RTW89_SET_FWCMD_CXROLE_ACT_PHY(void * cmd,u8 val,int n,u8 offset)2331 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2332 {
2333 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2334 }
2335
RTW89_SET_FWCMD_CXROLE_ACT_NOA(void * cmd,u8 val,int n,u8 offset)2336 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2337 {
2338 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2339 }
2340
RTW89_SET_FWCMD_CXROLE_ACT_BAND(void * cmd,u8 val,int n,u8 offset)2341 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2342 {
2343 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2344 }
2345
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void * cmd,u8 val,int n,u8 offset)2346 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2347 {
2348 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2349 }
2350
RTW89_SET_FWCMD_CXROLE_ACT_BW(void * cmd,u8 val,int n,u8 offset)2351 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2352 {
2353 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2354 }
2355
RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void * cmd,u8 val,int n,u8 offset)2356 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2357 {
2358 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2359 }
2360
RTW89_SET_FWCMD_CXROLE_ACT_CH(void * cmd,u8 val,int n,u8 offset)2361 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2362 {
2363 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2364 }
2365
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void * cmd,u16 val,int n,u8 offset)2366 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2367 {
2368 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2369 }
2370
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void * cmd,u16 val,int n,u8 offset)2371 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2372 {
2373 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2374 }
2375
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void * cmd,u16 val,int n,u8 offset)2376 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2377 {
2378 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2379 }
2380
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void * cmd,u16 val,int n,u8 offset)2381 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2382 {
2383 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2384 }
2385
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void * cmd,u32 val,int n,u8 offset)2386 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2387 {
2388 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2389 }
2390
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void * cmd,u8 val,int n,u8 offset)2391 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2392 {
2393 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2394 }
2395
RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void * cmd,u8 val,int n,u8 offset)2396 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2397 {
2398 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2399 }
2400
RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void * cmd,u8 val,int n,u8 offset)2401 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2402 {
2403 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2404 }
2405
RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void * cmd,u8 val,int n,u8 offset)2406 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2407 {
2408 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2409 }
2410
RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void * cmd,u8 val,int n,u8 offset)2411 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2412 {
2413 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2414 }
2415
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void * cmd,u8 val,int n,u8 offset)2416 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2417 {
2418 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2419 }
2420
RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void * cmd,u8 val,int n,u8 offset)2421 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2422 {
2423 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2424 }
2425
RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void * cmd,u8 val,int n,u8 offset)2426 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2427 {
2428 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2429 }
2430
RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void * cmd,u8 val,int n,u8 offset)2431 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2432 {
2433 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2434 }
2435
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void * cmd,u32 val,int n,u8 offset)2436 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2437 {
2438 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2439 }
2440
RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void * cmd,u32 val,u8 offset)2441 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2442 {
2443 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2444 }
2445
RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void * cmd,u32 val,u8 offset)2446 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2447 {
2448 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2449 }
2450
RTW89_SET_FWCMD_CXROLE_DBCC_EN(void * cmd,u32 val,u8 offset)2451 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2452 {
2453 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2454 }
2455
RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void * cmd,u32 val,u8 offset)2456 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2457 {
2458 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2459 }
2460
RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void * cmd,u32 val,u8 offset)2461 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2462 {
2463 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2464 }
2465
RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void * cmd,u32 val,u8 offset)2466 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2467 {
2468 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2469 }
2470
RTW89_SET_FWCMD_CXCTRL_MANUAL(void * cmd,u32 val)2471 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2472 {
2473 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2474 }
2475
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void * cmd,u32 val)2476 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2477 {
2478 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2479 }
2480
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void * cmd,u32 val)2481 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2482 {
2483 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2484 }
2485
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void * cmd,u32 val)2486 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2487 {
2488 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2489 }
2490
RTW89_SET_FWCMD_CXTRX_TXLV(void * cmd,u8 val)2491 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2492 {
2493 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2494 }
2495
RTW89_SET_FWCMD_CXTRX_RXLV(void * cmd,u8 val)2496 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2497 {
2498 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2499 }
2500
RTW89_SET_FWCMD_CXTRX_WLRSSI(void * cmd,u8 val)2501 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2502 {
2503 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2504 }
2505
RTW89_SET_FWCMD_CXTRX_BTRSSI(void * cmd,u8 val)2506 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2507 {
2508 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2509 }
2510
RTW89_SET_FWCMD_CXTRX_TXPWR(void * cmd,s8 val)2511 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2512 {
2513 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2514 }
2515
RTW89_SET_FWCMD_CXTRX_RXGAIN(void * cmd,s8 val)2516 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2517 {
2518 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2519 }
2520
RTW89_SET_FWCMD_CXTRX_BTTXPWR(void * cmd,s8 val)2521 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2522 {
2523 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2524 }
2525
RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void * cmd,s8 val)2526 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2527 {
2528 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2529 }
2530
RTW89_SET_FWCMD_CXTRX_CN(void * cmd,u8 val)2531 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2532 {
2533 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2534 }
2535
RTW89_SET_FWCMD_CXTRX_NHM(void * cmd,s8 val)2536 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2537 {
2538 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2539 }
2540
RTW89_SET_FWCMD_CXTRX_BTPROFILE(void * cmd,u8 val)2541 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2542 {
2543 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2544 }
2545
RTW89_SET_FWCMD_CXTRX_RSVD2(void * cmd,u8 val)2546 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2547 {
2548 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2549 }
2550
RTW89_SET_FWCMD_CXTRX_TXRATE(void * cmd,u16 val)2551 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2552 {
2553 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2554 }
2555
RTW89_SET_FWCMD_CXTRX_RXRATE(void * cmd,u16 val)2556 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2557 {
2558 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2559 }
2560
RTW89_SET_FWCMD_CXTRX_TXTP(void * cmd,u32 val)2561 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2562 {
2563 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2564 }
2565
RTW89_SET_FWCMD_CXTRX_RXTP(void * cmd,u32 val)2566 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2567 {
2568 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2569 }
2570
RTW89_SET_FWCMD_CXTRX_RXERRRA(void * cmd,u32 val)2571 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2572 {
2573 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2574 }
2575
RTW89_SET_FWCMD_CXRFK_STATE(void * cmd,u32 val)2576 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2577 {
2578 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2579 }
2580
RTW89_SET_FWCMD_CXRFK_PATH_MAP(void * cmd,u32 val)2581 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2582 {
2583 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2584 }
2585
RTW89_SET_FWCMD_CXRFK_PHY_MAP(void * cmd,u32 val)2586 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2587 {
2588 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2589 }
2590
RTW89_SET_FWCMD_CXRFK_BAND(void * cmd,u32 val)2591 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2592 {
2593 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2594 }
2595
RTW89_SET_FWCMD_CXRFK_TYPE(void * cmd,u32 val)2596 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2597 {
2598 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2599 }
2600
RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void * cmd,u32 val)2601 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2602 {
2603 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2604 }
2605
RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void * cmd,u32 val)2606 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2607 {
2608 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2609 }
2610
RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void * cmd,u32 val)2611 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2612 {
2613 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2614 }
2615
2616 struct rtw89_h2c_chinfo_elem {
2617 __le32 w0;
2618 __le32 w1;
2619 __le32 w2;
2620 __le32 w3;
2621 __le32 w4;
2622 __le32 w5;
2623 __le32 w6;
2624 } __packed;
2625
2626 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2627 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2628 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2629 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2630 #define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2631 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2632 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2633 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2634 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2635 #define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2636 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2637 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2638 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2639 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2640 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2641 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2642 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2643 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2644 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2645 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2646 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2647 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2648 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2649 #define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2650
2651 struct rtw89_h2c_chinfo_elem_be {
2652 __le32 w0;
2653 __le32 w1;
2654 __le32 w2;
2655 __le32 w3;
2656 __le32 w4;
2657 __le32 w5;
2658 __le32 w6;
2659 } __packed;
2660
2661 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2662 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2663 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2664 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2665 #define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2666 #define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2667 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2668 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2669 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2670 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2671 #define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2672 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2673 #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
2674 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2675 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2676 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2677 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2678 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2679 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2680 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2681 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2682 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2683 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2684 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2685 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2686 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2687 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2688 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
2689 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2690
2691 struct rtw89_h2c_chinfo {
2692 u8 ch_num;
2693 u8 elem_size;
2694 u8 arg;
2695 u8 rsvd0;
2696 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
2697 } __packed;
2698
2699 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2700 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2701
2702 struct rtw89_h2c_scanofld {
2703 __le32 w0;
2704 __le32 w1;
2705 __le32 w2;
2706 __le32 tsf_high;
2707 __le32 tsf_low;
2708 __le32 w5;
2709 __le32 w6;
2710 } __packed;
2711
2712 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2713 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2714 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2715 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2716 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2717 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2718 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2719 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2720 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2721 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2722 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2723 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2724 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2725 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2726 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2727 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2728 #define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)
2729 #define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)
2730
2731 struct rtw89_h2c_scanofld_be_macc_role {
2732 __le32 w0;
2733 } __packed;
2734
2735 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
2736 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
2737 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
2738 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2739
2740 struct rtw89_h2c_scanofld_be_opch {
2741 __le32 w0;
2742 __le32 w1;
2743 __le32 w2;
2744 __le32 w3;
2745 } __packed;
2746
2747 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
2748 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
2749 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
2750 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
2751 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2752 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2753 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
2754 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
2755 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
2756 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
2757 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
2758 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2759 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
2760 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
2761 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
2762 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
2763 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
2764 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
2765 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2766
2767 struct rtw89_h2c_scanofld_be {
2768 __le32 w0;
2769 __le32 w1;
2770 __le32 w2;
2771 __le32 w3;
2772 __le32 w4;
2773 __le32 w5;
2774 __le32 w6;
2775 __le32 w7;
2776 __le32 w8;
2777 __le32 w9; /* Added after SCAN_OFFLOAD_BE_V1 */
2778 /* struct rtw89_h2c_scanofld_be_macc_role (flexible number) */
2779 /* struct rtw89_h2c_scanofld_be_opch (flexible number) */
2780 } __packed;
2781
2782 #define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
2783 #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
2784 #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
2785 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2786 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2787 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
2788 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
2789 #define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
2790 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2791 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
2792 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
2793 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2794 #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
2795 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
2796 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2797 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
2798 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
2799 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
2800 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2801 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
2802 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
2803 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2804 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
2805 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
2806 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
2807 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)
2808 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)
2809 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)
2810 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
2811 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
2812 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
2813
2814 struct rtw89_h2c_fwips {
2815 __le32 w0;
2816 } __packed;
2817
2818 #define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)
2819 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
2820
RTW89_SET_FWCMD_P2P_MACID(void * cmd,u32 val)2821 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2822 {
2823 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2824 }
2825
RTW89_SET_FWCMD_P2P_P2PID(void * cmd,u32 val)2826 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2827 {
2828 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2829 }
2830
RTW89_SET_FWCMD_P2P_NOAID(void * cmd,u32 val)2831 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2832 {
2833 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2834 }
2835
RTW89_SET_FWCMD_P2P_ACT(void * cmd,u32 val)2836 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2837 {
2838 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2839 }
2840
RTW89_SET_FWCMD_P2P_TYPE(void * cmd,u32 val)2841 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2842 {
2843 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2844 }
2845
RTW89_SET_FWCMD_P2P_ALL_SLEP(void * cmd,u32 val)2846 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2847 {
2848 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2849 }
2850
RTW89_SET_FWCMD_NOA_START_TIME(void * cmd,__le32 val)2851 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2852 {
2853 *((__le32 *)cmd + 1) = val;
2854 }
2855
RTW89_SET_FWCMD_NOA_INTERVAL(void * cmd,__le32 val)2856 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2857 {
2858 *((__le32 *)cmd + 2) = val;
2859 }
2860
RTW89_SET_FWCMD_NOA_DURATION(void * cmd,__le32 val)2861 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2862 {
2863 *((__le32 *)cmd + 3) = val;
2864 }
2865
RTW89_SET_FWCMD_NOA_COUNT(void * cmd,u32 val)2866 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2867 {
2868 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2869 }
2870
RTW89_SET_FWCMD_NOA_CTWINDOW(void * cmd,u32 val)2871 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2872 {
2873 u8 ctwnd;
2874
2875 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2876 return;
2877 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2878 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2879 }
2880
RTW89_SET_FWCMD_TSF32_TOGL_BAND(void * cmd,u32 val)2881 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2882 {
2883 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2884 }
2885
RTW89_SET_FWCMD_TSF32_TOGL_EN(void * cmd,u32 val)2886 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2887 {
2888 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2889 }
2890
RTW89_SET_FWCMD_TSF32_TOGL_PORT(void * cmd,u32 val)2891 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2892 {
2893 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2894 }
2895
RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void * cmd,u32 val)2896 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2897 {
2898 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2899 }
2900
2901 enum rtw89_fw_mcc_c2h_rpt_cfg {
2902 RTW89_FW_MCC_C2H_RPT_OFF = 0,
2903 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
2904 RTW89_FW_MCC_C2H_RPT_ALL = 2,
2905 };
2906
2907 struct rtw89_fw_mcc_add_req {
2908 u8 macid;
2909 u8 central_ch_seg0;
2910 u8 central_ch_seg1;
2911 u8 primary_ch;
2912 enum rtw89_bandwidth bandwidth: 4;
2913 u32 group: 2;
2914 u32 c2h_rpt: 2;
2915 u32 dis_tx_null: 1;
2916 u32 dis_sw_retry: 1;
2917 u32 in_curr_ch: 1;
2918 u32 sw_retry_count: 3;
2919 u32 tx_null_early: 4;
2920 u32 btc_in_2g: 1;
2921 u32 pta_en: 1;
2922 u32 rfk_by_pass: 1;
2923 u32 ch_band_type: 2;
2924 u32 rsvd0: 9;
2925 u32 duration;
2926 u8 courtesy_en;
2927 u8 courtesy_num;
2928 u8 courtesy_target;
2929 u8 rsvd1;
2930 };
2931
RTW89_SET_FWCMD_ADD_MCC_MACID(void * cmd,u32 val)2932 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2933 {
2934 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2935 }
2936
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void * cmd,u32 val)2937 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2938 {
2939 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2940 }
2941
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void * cmd,u32 val)2942 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2943 {
2944 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2945 }
2946
RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void * cmd,u32 val)2947 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2948 {
2949 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2950 }
2951
RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void * cmd,u32 val)2952 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2953 {
2954 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
2955 }
2956
RTW89_SET_FWCMD_ADD_MCC_GROUP(void * cmd,u32 val)2957 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
2958 {
2959 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
2960 }
2961
RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void * cmd,u32 val)2962 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
2963 {
2964 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
2965 }
2966
RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void * cmd,u32 val)2967 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
2968 {
2969 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
2970 }
2971
RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void * cmd,u32 val)2972 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
2973 {
2974 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
2975 }
2976
RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void * cmd,u32 val)2977 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
2978 {
2979 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
2980 }
2981
RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void * cmd,u32 val)2982 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
2983 {
2984 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
2985 }
2986
RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void * cmd,u32 val)2987 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
2988 {
2989 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
2990 }
2991
RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void * cmd,u32 val)2992 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
2993 {
2994 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
2995 }
2996
RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void * cmd,u32 val)2997 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
2998 {
2999 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
3000 }
3001
RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void * cmd,u32 val)3002 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
3003 {
3004 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
3005 }
3006
RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void * cmd,u32 val)3007 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
3008 {
3009 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
3010 }
3011
RTW89_SET_FWCMD_ADD_MCC_DURATION(void * cmd,u32 val)3012 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
3013 {
3014 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3015 }
3016
RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void * cmd,u32 val)3017 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3018 {
3019 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3020 }
3021
RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void * cmd,u32 val)3022 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3023 {
3024 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
3025 }
3026
RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void * cmd,u32 val)3027 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3028 {
3029 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
3030 }
3031
3032 enum rtw89_fw_mcc_old_group_actions {
3033 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
3034 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
3035 };
3036
3037 struct rtw89_fw_mcc_start_req {
3038 u32 group: 2;
3039 u32 btc_in_group: 1;
3040 u32 old_group_action: 2;
3041 u32 old_group: 2;
3042 u32 rsvd0: 9;
3043 u32 notify_cnt: 3;
3044 u32 rsvd1: 2;
3045 u32 notify_rxdbg_en: 1;
3046 u32 rsvd2: 2;
3047 u32 macid: 8;
3048 u32 tsf_low;
3049 u32 tsf_high;
3050 };
3051
RTW89_SET_FWCMD_START_MCC_GROUP(void * cmd,u32 val)3052 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3053 {
3054 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3055 }
3056
RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void * cmd,u32 val)3057 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3058 {
3059 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3060 }
3061
RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void * cmd,u32 val)3062 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3063 {
3064 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3065 }
3066
RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void * cmd,u32 val)3067 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3068 {
3069 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3070 }
3071
RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void * cmd,u32 val)3072 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3073 {
3074 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3075 }
3076
RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void * cmd,u32 val)3077 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3078 {
3079 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3080 }
3081
RTW89_SET_FWCMD_START_MCC_MACID(void * cmd,u32 val)3082 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3083 {
3084 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3085 }
3086
RTW89_SET_FWCMD_START_MCC_TSF_LOW(void * cmd,u32 val)3087 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3088 {
3089 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3090 }
3091
RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void * cmd,u32 val)3092 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3093 {
3094 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3095 }
3096
RTW89_SET_FWCMD_STOP_MCC_MACID(void * cmd,u32 val)3097 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3098 {
3099 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3100 }
3101
RTW89_SET_FWCMD_STOP_MCC_GROUP(void * cmd,u32 val)3102 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3103 {
3104 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3105 }
3106
RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void * cmd,u32 val)3107 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3108 {
3109 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3110 }
3111
RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void * cmd,u32 val)3112 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3113 {
3114 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3115 }
3116
RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void * cmd,u32 val)3117 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3118 {
3119 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3120 }
3121
RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void * cmd,u32 val)3122 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3123 {
3124 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3125 }
3126
3127 struct rtw89_fw_mcc_tsf_req {
3128 u8 group: 2;
3129 u8 rsvd0: 6;
3130 u8 macid_x;
3131 u8 macid_y;
3132 u8 rsvd1;
3133 };
3134
RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void * cmd,u32 val)3135 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3136 {
3137 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3138 }
3139
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void * cmd,u32 val)3140 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3141 {
3142 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3143 }
3144
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void * cmd,u32 val)3145 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3146 {
3147 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3148 }
3149
RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void * cmd,u32 val)3150 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3151 {
3152 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3153 }
3154
RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void * cmd,u32 val)3155 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3156 {
3157 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3158 }
3159
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void * cmd,u32 val)3160 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3161 {
3162 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3163 }
3164
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void * cmd,u8 * bitmap,u8 len)3165 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3166 u8 *bitmap, u8 len)
3167 {
3168 memcpy((__le32 *)cmd + 1, bitmap, len);
3169 }
3170
RTW89_SET_FWCMD_MCC_SYNC_GROUP(void * cmd,u32 val)3171 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3172 {
3173 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3174 }
3175
RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void * cmd,u32 val)3176 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3177 {
3178 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3179 }
3180
RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void * cmd,u32 val)3181 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3182 {
3183 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3184 }
3185
RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void * cmd,u32 val)3186 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3187 {
3188 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3189 }
3190
3191 struct rtw89_fw_mcc_duration {
3192 u32 group: 2;
3193 u32 btc_in_group: 1;
3194 u32 rsvd0: 5;
3195 u32 start_macid: 8;
3196 u32 macid_x: 8;
3197 u32 macid_y: 8;
3198 u32 start_tsf_low;
3199 u32 start_tsf_high;
3200 u32 duration_x;
3201 u32 duration_y;
3202 };
3203
RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void * cmd,u32 val)3204 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3205 {
3206 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3207 }
3208
3209 static
RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void * cmd,u32 val)3210 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3211 {
3212 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3213 }
3214
3215 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void * cmd,u32 val)3216 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3217 {
3218 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3219 }
3220
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void * cmd,u32 val)3221 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3222 {
3223 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3224 }
3225
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void * cmd,u32 val)3226 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3227 {
3228 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3229 }
3230
3231 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void * cmd,u32 val)3232 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3233 {
3234 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3235 }
3236
3237 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void * cmd,u32 val)3238 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3239 {
3240 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3241 }
3242
3243 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void * cmd,u32 val)3244 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3245 {
3246 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3247 }
3248
3249 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void * cmd,u32 val)3250 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3251 {
3252 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3253 }
3254
3255 enum rtw89_h2c_mrc_sch_types {
3256 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3257 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3258 RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3259 };
3260
3261 enum rtw89_h2c_mrc_role_types {
3262 RTW89_H2C_MRC_ROLE_WIFI = 0,
3263 RTW89_H2C_MRC_ROLE_BT = 1,
3264 RTW89_H2C_MRC_ROLE_EMPTY = 2,
3265 };
3266
3267 #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3268 #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3269
3270 struct rtw89_fw_mrc_add_slot_arg {
3271 u16 duration; /* unit: TU */
3272 bool courtesy_en;
3273 u8 courtesy_period;
3274 u8 courtesy_target; /* slot idx */
3275
3276 unsigned int role_num;
3277 struct {
3278 enum rtw89_h2c_mrc_role_types role_type;
3279 bool is_master;
3280 bool en_tx_null;
3281 enum rtw89_band band;
3282 enum rtw89_bandwidth bw;
3283 u8 macid;
3284 u8 central_ch;
3285 u8 primary_ch;
3286 u8 null_early; /* unit: TU */
3287
3288 /* if MLD, for macid: [0, chip::support_mld_num)
3289 * otherwise, for macid: [0, 32)
3290 */
3291 u32 macid_main_bitmap;
3292 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3293 u32 macid_paired_bitmap;
3294 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3295 };
3296
3297 struct rtw89_fw_mrc_add_arg {
3298 u8 sch_idx;
3299 enum rtw89_h2c_mrc_sch_types sch_type;
3300 bool btc_in_sch;
3301
3302 unsigned int slot_num;
3303 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3304 };
3305
3306 struct rtw89_h2c_mrc_add_role {
3307 __le32 w0;
3308 __le32 w1;
3309 __le32 w2;
3310 __le32 macid_main_bitmap;
3311 __le32 macid_paired_bitmap;
3312 } __packed;
3313
3314 #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3315 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3316 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3317 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3318 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3319 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3320 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3321 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3322 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3323 #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3324 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3325 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3326 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3327 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3328 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3329 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3330
3331 struct rtw89_h2c_mrc_add_slot {
3332 __le32 w0;
3333 __le32 w1;
3334 struct rtw89_h2c_mrc_add_role roles[];
3335 } __packed;
3336
3337 #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3338 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3339 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3340 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3341 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3342
3343 struct rtw89_h2c_mrc_add {
3344 __le32 w0;
3345 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3346 * are other flexible array inside it. We cannot access them correctly
3347 * through this struct. So, in case misusing, we don't really declare
3348 * it here.
3349 */
3350 } __packed;
3351
3352 #define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3353 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3354 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3355 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3356
3357 enum rtw89_h2c_mrc_start_actions {
3358 RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3359 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3360 };
3361
3362 struct rtw89_fw_mrc_start_arg {
3363 u8 sch_idx;
3364 u8 old_sch_idx;
3365 u64 start_tsf;
3366 enum rtw89_h2c_mrc_start_actions action;
3367 };
3368
3369 struct rtw89_h2c_mrc_start {
3370 __le32 w0;
3371 __le32 start_tsf_low;
3372 __le32 start_tsf_high;
3373 } __packed;
3374
3375 #define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3376 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3377 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3378
3379 struct rtw89_h2c_mrc_del {
3380 __le32 w0;
3381 } __packed;
3382
3383 #define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3384 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3385 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3386 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3387 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3388 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3389
3390 #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3391
3392 struct rtw89_fw_mrc_req_tsf_arg {
3393 unsigned int num;
3394 struct {
3395 u8 band;
3396 u8 port;
3397 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3398 };
3399
3400 struct rtw89_h2c_mrc_req_tsf {
3401 u8 req_tsf_num;
3402 u8 infos[] __counted_by(req_tsf_num);
3403 } __packed;
3404
3405 #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3406 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3407
3408 enum rtw89_h2c_mrc_upd_bitmap_actions {
3409 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3410 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3411 };
3412
3413 struct rtw89_fw_mrc_upd_bitmap_arg {
3414 u8 sch_idx;
3415 u8 macid;
3416 u8 client_macid;
3417 enum rtw89_h2c_mrc_upd_bitmap_actions action;
3418 };
3419
3420 struct rtw89_h2c_mrc_upd_bitmap {
3421 __le32 w0;
3422 __le32 w1;
3423 } __packed;
3424
3425 #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3426 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3427 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3428 #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3429
3430 struct rtw89_fw_mrc_sync_arg {
3431 u8 offset; /* unit: TU */
3432 struct {
3433 u8 band;
3434 u8 port;
3435 } src, dest;
3436 };
3437
3438 struct rtw89_h2c_mrc_sync {
3439 __le32 w0;
3440 __le32 w1;
3441 } __packed;
3442
3443 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3444 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3445 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3446 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3447 #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3448 #define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3449
3450 struct rtw89_fw_mrc_upd_duration_arg {
3451 u8 sch_idx;
3452 u64 start_tsf;
3453
3454 unsigned int slot_num;
3455 struct {
3456 u8 slot_idx;
3457 u16 duration; /* unit: TU */
3458 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3459 };
3460
3461 struct rtw89_h2c_mrc_upd_duration {
3462 __le32 w0;
3463 __le32 start_tsf_low;
3464 __le32 start_tsf_high;
3465 __le32 slots[];
3466 } __packed;
3467
3468 #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3469 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3470 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3471 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3472 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3473
3474 struct rtw89_h2c_wow_aoac {
3475 __le32 w0;
3476 } __packed;
3477
3478 #define RTW89_C2H_HEADER_LEN 8
3479
3480 struct rtw89_c2h_hdr {
3481 __le32 w0;
3482 __le32 w1;
3483 } __packed;
3484
3485 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3486 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3487 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3488 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3489
3490 struct rtw89_fw_c2h_attr {
3491 u8 category;
3492 u8 class;
3493 u8 func;
3494 u16 len;
3495 };
3496
RTW89_SKB_C2H_CB(struct sk_buff * skb)3497 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3498 {
3499 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3500
3501 return (struct rtw89_fw_c2h_attr *)skb->cb;
3502 }
3503
3504 struct rtw89_c2h_done_ack {
3505 __le32 w0;
3506 __le32 w1;
3507 __le32 w2;
3508 } __packed;
3509
3510 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3511 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3512 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3513 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3514 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3515
3516 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3517 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3518 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3519 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3520 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3521 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3522 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3523 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3524
3525 struct rtw89_fw_c2h_log_fmt {
3526 __le16 signature;
3527 u8 feature;
3528 u8 syntax;
3529 __le32 fmt_id;
3530 u8 file_num;
3531 __le16 line_num;
3532 u8 argc;
3533 union {
3534 DECLARE_FLEX_ARRAY(u8, raw);
3535 DECLARE_FLEX_ARRAY(__le32, argv);
3536 } __packed u;
3537 } __packed;
3538
3539 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3540 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3541 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3542 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3543 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3544
3545 struct rtw89_c2h_mac_bcnfltr_rpt {
3546 __le32 w0;
3547 __le32 w1;
3548 __le32 w2;
3549 } __packed;
3550
3551 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3552 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3553 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3554 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3555
3556 struct rtw89_c2h_ra_rpt {
3557 struct rtw89_c2h_hdr hdr;
3558 __le32 w2;
3559 __le32 w3;
3560 } __packed;
3561
3562 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3563 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3564 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3565 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3566 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3567 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3568 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3569 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3570 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3571
3572 /* For WiFi 6 chips:
3573 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3574 * HT-new: [6:5]: NA, [4:0]: MCS
3575 * For WiFi 7 chips (V1):
3576 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3577 */
3578 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3579 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3580 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3581 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3582 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3583 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3584 FIELD_PREP(GENMASK(2, 0), mcs))
3585
3586 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3587 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3588 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3589 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3590 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3591 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3592
3593 struct rtw89_c2h_scanofld {
3594 __le32 w0;
3595 __le32 w1;
3596 __le32 w2;
3597 __le32 w3;
3598 __le32 w4;
3599 __le32 w5;
3600 __le32 w6;
3601 __le32 w7;
3602 } __packed;
3603
3604 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3605 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3606 #define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
3607 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3608 #define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
3609 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3610 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3611 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3612 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3613 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3614 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3615 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3616
3617 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3618 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3619 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3620 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3621
3622 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3623 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3624 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3625 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3626 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3627 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3628
3629 struct rtw89_mac_mcc_tsf_rpt {
3630 u32 macid_x;
3631 u32 macid_y;
3632 u32 tsf_x_low;
3633 u32 tsf_x_high;
3634 u32 tsf_y_low;
3635 u32 tsf_y_high;
3636 };
3637
3638 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3639
3640 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3641 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3642 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3643 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3644 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3645 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3646 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3647 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3648 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3649 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3650 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3651 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3652 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3653 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3654
3655 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3656 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3657 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3658 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3659 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3660 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3661 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3662 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3663 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3664 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3665
3666 struct rtw89_mac_mrc_tsf_rpt {
3667 unsigned int num;
3668 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3669 };
3670
3671 static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3672
3673 struct rtw89_c2h_mrc_tsf_rpt_info {
3674 __le32 tsf_low;
3675 __le32 tsf_high;
3676 } __packed;
3677
3678 struct rtw89_c2h_mrc_tsf_rpt {
3679 struct rtw89_c2h_hdr hdr;
3680 __le32 w2;
3681 struct rtw89_c2h_mrc_tsf_rpt_info infos[];
3682 } __packed;
3683
3684 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
3685
3686 struct rtw89_c2h_mrc_status_rpt {
3687 struct rtw89_c2h_hdr hdr;
3688 __le32 w2;
3689 __le32 tsf_low;
3690 __le32 tsf_high;
3691 } __packed;
3692
3693 #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
3694 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
3695
3696 struct rtw89_c2h_pkt_ofld_rsp {
3697 __le32 w0;
3698 __le32 w1;
3699 __le32 w2;
3700 } __packed;
3701
3702 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3703 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3704 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3705
3706 struct rtw89_c2h_wow_aoac_report {
3707 struct rtw89_c2h_hdr c2h_hdr;
3708 u8 rpt_ver;
3709 u8 sec_type;
3710 u8 key_idx;
3711 u8 pattern_idx;
3712 u8 rekey_ok;
3713 u8 rsvd1[3];
3714 u8 ptk_tx_iv[8];
3715 u8 eapol_key_replay_count[8];
3716 u8 gtk[32];
3717 u8 ptk_rx_iv[8];
3718 u8 gtk_rx_iv[4][8];
3719 __le64 igtk_key_id;
3720 __le64 igtk_ipn;
3721 u8 igtk[32];
3722 u8 csa_pri_ch;
3723 u8 csa_bw_ch_offset;
3724 u8 csa_ch_band_chsw_failed;
3725 u8 csa_rsvd1;
3726 } __packed;
3727
3728 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3729
3730 struct rtw89_h2c_bcnfltr {
3731 __le32 w0;
3732 } __packed;
3733
3734 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3735 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3736 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3737 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3738 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3739 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3740 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3741 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3742
3743 struct rtw89_h2c_ofld_rssi {
3744 __le32 w0;
3745 __le32 w1;
3746 } __packed;
3747
3748 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3749 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3750 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3751
3752 struct rtw89_h2c_ofld {
3753 __le32 w0;
3754 } __packed;
3755
3756 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3757 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3758 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3759
3760 #define RTW89_MFW_SIG 0xFF
3761
3762 struct rtw89_mfw_info {
3763 u8 cv;
3764 u8 type; /* enum rtw89_fw_type */
3765 u8 mp;
3766 u8 rsvd;
3767 __le32 shift;
3768 __le32 size;
3769 u8 rsvd2[4];
3770 } __packed;
3771
3772 struct rtw89_mfw_hdr {
3773 u8 sig; /* RTW89_MFW_SIG */
3774 u8 fw_nr;
3775 u8 rsvd0[2];
3776 struct {
3777 u8 major;
3778 u8 minor;
3779 u8 sub;
3780 u8 idx;
3781 } ver;
3782 u8 rsvd1[8];
3783 struct rtw89_mfw_info info[];
3784 } __packed;
3785
3786 struct rtw89_fw_logsuit_hdr {
3787 __le32 rsvd;
3788 __le32 count;
3789 __le32 ids[];
3790 } __packed;
3791
3792 #define RTW89_FW_ELEMENT_ALIGN 16
3793
3794 enum rtw89_fw_element_id {
3795 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
3796 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
3797 RTW89_FW_ELEMENT_ID_BB_REG = 2,
3798 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
3799 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
3800 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
3801 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
3802 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3803 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3804 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
3805 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
3806 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
3807 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
3808 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
3809 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
3810 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
3811 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
3812 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
3813 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
3814 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
3815
3816 RTW89_FW_ELEMENT_ID_NUM,
3817 };
3818
3819 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ \
3820 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3821 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3822 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3823 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3824 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3825 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3826 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3827
3828 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
3829 (BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ | \
3830 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3831 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
3832
3833 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ \
3834 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3835 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3836 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3837 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3838 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3839 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
3840
3841 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
3842 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3843 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3844 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3845 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3846 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3847 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
3848
3849 struct __rtw89_fw_txpwr_element {
3850 u8 rsvd0;
3851 u8 rsvd1;
3852 u8 rfe_type;
3853 u8 ent_sz;
3854 __le32 num_ents;
3855 u8 content[];
3856 } __packed;
3857
3858 enum rtw89_fw_txpwr_trk_type {
3859 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
3860 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
3861 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
3862 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
3863 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
3864 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
3865
3866 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
3867 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
3868 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
3869 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
3870 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
3871 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
3872
3873 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
3874 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
3875 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
3876 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
3877 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
3878 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
3879 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
3880 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
3881 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
3882 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
3883
3884 RTW89_FW_TXPWR_TRK_TYPE_NR,
3885 };
3886
3887 struct rtw89_fw_txpwr_track_cfg {
3888 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
3889 };
3890
3891 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
3892 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
3893 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
3894 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
3895 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
3896 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
3897 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
3898 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
3899 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
3900 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
3901 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
3902 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
3903 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
3904 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
3905 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
3906 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
3907 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
3908 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
3909 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
3910
3911 struct rtw89_fw_element_hdr {
3912 __le32 id; /* enum rtw89_fw_element_id */
3913 __le32 size; /* exclude header size */
3914 u8 ver[4];
3915 __le32 rsvd0;
3916 __le32 rsvd1;
3917 __le32 rsvd2;
3918 union {
3919 struct {
3920 u8 priv[8];
3921 u8 contents[];
3922 } __packed common;
3923 struct {
3924 u8 idx;
3925 u8 rsvd[7];
3926 struct {
3927 __le32 addr;
3928 __le32 data;
3929 } __packed regs[];
3930 } __packed reg2;
3931 struct {
3932 u8 cv;
3933 u8 priv[7];
3934 u8 contents[];
3935 } __packed bbmcu;
3936 struct {
3937 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
3938 __le32 rsvd;
3939 s8 contents[][DELTA_SWINGIDX_SIZE];
3940 } __packed txpwr_trk;
3941 struct {
3942 u8 nr;
3943 u8 rsvd[3];
3944 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
3945 u8 rsvd1[3];
3946 __le16 offset[];
3947 } __packed rfk_log_fmt;
3948 struct __rtw89_fw_txpwr_element txpwr;
3949 } __packed u;
3950 } __packed;
3951
3952 struct fwcmd_hdr {
3953 __le32 hdr0;
3954 __le32 hdr1;
3955 };
3956
3957 union rtw89_compat_fw_hdr {
3958 struct rtw89_mfw_hdr mfw_hdr;
3959 struct rtw89_fw_hdr fw_hdr;
3960 };
3961
rtw89_compat_fw_hdr_ver_code(const void * fw_buf)3962 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
3963 {
3964 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
3965
3966 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
3967 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
3968 else
3969 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
3970 }
3971
rtw89_fw_get_filename(char * buf,size_t size,const char * fw_basename,int fw_format)3972 static inline void rtw89_fw_get_filename(char *buf, size_t size,
3973 const char *fw_basename, int fw_format)
3974 {
3975 if (fw_format <= 0)
3976 snprintf(buf, size, "%s.bin", fw_basename);
3977 else
3978 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
3979 }
3980
3981 #define RTW89_H2C_RF_PAGE_SIZE 500
3982 #define RTW89_H2C_RF_PAGE_NUM 3
3983 struct rtw89_fw_h2c_rf_reg_info {
3984 enum rtw89_rf_path rf_path;
3985 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
3986 u16 curr_idx;
3987 };
3988
3989 #define H2C_SEC_CAM_LEN 24
3990
3991 #define H2C_HEADER_LEN 8
3992 #define H2C_HDR_CAT GENMASK(1, 0)
3993 #define H2C_HDR_CLASS GENMASK(7, 2)
3994 #define H2C_HDR_FUNC GENMASK(15, 8)
3995 #define H2C_HDR_DEL_TYPE GENMASK(19, 16)
3996 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
3997 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
3998 #define H2C_HDR_REC_ACK BIT(14)
3999 #define H2C_HDR_DONE_ACK BIT(15)
4000
4001 #define FWCMD_TYPE_H2C 0
4002
4003 #define H2C_CAT_TEST 0x0
4004
4005 /* CLASS 5 - FW STATUS TEST */
4006 #define H2C_CL_FW_STATUS_TEST 0x5
4007 #define H2C_FUNC_CPU_EXCEPTION 0x1
4008
4009 #define H2C_CAT_MAC 0x1
4010
4011 /* CLASS 0 - FW INFO */
4012 #define H2C_CL_FW_INFO 0x0
4013 #define H2C_FUNC_LOG_CFG 0x0
4014 #define H2C_FUNC_MAC_GENERAL_PKT 0x1
4015
4016 /* CLASS 1 - WOW */
4017 #define H2C_CL_MAC_WOW 0x1
4018 enum rtw89_wow_h2c_func {
4019 H2C_FUNC_KEEP_ALIVE = 0x0,
4020 H2C_FUNC_DISCONNECT_DETECT = 0x1,
4021 H2C_FUNC_WOW_GLOBAL = 0x2,
4022 H2C_FUNC_GTK_OFLD = 0x3,
4023 H2C_FUNC_ARP_OFLD = 0x4,
4024 H2C_FUNC_NLO = 0x7,
4025 H2C_FUNC_WAKEUP_CTRL = 0x8,
4026 H2C_FUNC_WOW_CAM_UPD = 0xC,
4027 H2C_FUNC_AOAC_REPORT_REQ = 0xD,
4028
4029 NUM_OF_RTW89_WOW_H2C_FUNC,
4030 };
4031
4032 #define RTW89_WOW_WAIT_COND(tag, func) \
4033 ((tag) * NUM_OF_RTW89_WOW_H2C_FUNC + (func))
4034
4035 #define RTW89_WOW_WAIT_COND_AOAC \
4036 RTW89_WOW_WAIT_COND(0 /* don't care */, H2C_FUNC_AOAC_REPORT_REQ)
4037
4038 /* CLASS 2 - PS */
4039 #define H2C_CL_MAC_PS 0x2
4040 enum rtw89_ps_h2c_func {
4041 H2C_FUNC_MAC_LPS_PARM = 0x0,
4042 H2C_FUNC_P2P_ACT = 0x1,
4043 H2C_FUNC_IPS_CFG = 0x3,
4044
4045 NUM_OF_RTW89_PS_H2C_FUNC,
4046 };
4047
4048 #define RTW89_PS_WAIT_COND(tag, func) \
4049 ((tag) * NUM_OF_RTW89_PS_H2C_FUNC + (func))
4050
4051 #define RTW89_PS_WAIT_COND_IPS_CFG \
4052 RTW89_PS_WAIT_COND(0 /* don't care */, H2C_FUNC_IPS_CFG)
4053
4054 /* CLASS 3 - FW download */
4055 #define H2C_CL_MAC_FWDL 0x3
4056 #define H2C_FUNC_MAC_FWHDR_DL 0x0
4057
4058 /* CLASS 5 - Frame Exchange */
4059 #define H2C_CL_MAC_FR_EXCHG 0x5
4060 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2
4061 #define H2C_FUNC_MAC_BCN_UPD 0x5
4062 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
4063 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4064 #define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4065 #define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4066 #define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4067
4068 /* CLASS 6 - Address CAM */
4069 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
4070 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
4071
4072 /* CLASS 8 - Media Status Report */
4073 #define H2C_CL_MAC_MEDIA_RPT 0x8
4074 #define H2C_FUNC_MAC_JOININFO 0x0
4075 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
4076 #define H2C_FUNC_NOTIFY_DBCC 0x5
4077
4078 /* CLASS 9 - FW offload */
4079 #define H2C_CL_MAC_FW_OFLD 0x9
4080 enum rtw89_fw_ofld_h2c_func {
4081 H2C_FUNC_PACKET_OFLD = 0x1,
4082 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
4083 H2C_FUNC_USR_EDCA = 0xF,
4084 H2C_FUNC_TSF32_TOGL = 0x10,
4085 H2C_FUNC_OFLD_CFG = 0x14,
4086 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
4087 H2C_FUNC_SCANOFLD = 0x17,
4088 H2C_FUNC_PKT_DROP = 0x1b,
4089 H2C_FUNC_CFG_BCNFLTR = 0x1e,
4090 H2C_FUNC_OFLD_RSSI = 0x1f,
4091 H2C_FUNC_OFLD_TP = 0x20,
4092 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4093 H2C_FUNC_SCANOFLD_BE = 0x2c,
4094
4095 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4096 };
4097
4098 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
4099 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
4100
4101 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4102 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4103 H2C_FUNC_PACKET_OFLD)
4104
4105 #define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4106
4107 #define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4108 #define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4109 #define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4110 #define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4111
4112
4113 /* CLASS 10 - Security CAM */
4114 #define H2C_CL_MAC_SEC_CAM 0xa
4115 #define H2C_FUNC_MAC_SEC_UPD 0x1
4116
4117 /* CLASS 12 - BA CAM */
4118 #define H2C_CL_BA_CAM 0xc
4119 #define H2C_FUNC_MAC_BA_CAM 0x0
4120 #define H2C_FUNC_MAC_BA_CAM_V1 0x1
4121 #define H2C_FUNC_MAC_BA_CAM_INIT 0x2
4122
4123 /* CLASS 14 - MCC */
4124 #define H2C_CL_MCC 0xe
4125 enum rtw89_mcc_h2c_func {
4126 H2C_FUNC_ADD_MCC = 0x0,
4127 H2C_FUNC_START_MCC = 0x1,
4128 H2C_FUNC_STOP_MCC = 0x2,
4129 H2C_FUNC_DEL_MCC_GROUP = 0x3,
4130 H2C_FUNC_RESET_MCC_GROUP = 0x4,
4131 H2C_FUNC_MCC_REQ_TSF = 0x5,
4132 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
4133 H2C_FUNC_MCC_SYNC = 0x7,
4134 H2C_FUNC_MCC_SET_DURATION = 0x8,
4135
4136 NUM_OF_RTW89_MCC_H2C_FUNC,
4137 };
4138
4139 #define RTW89_MCC_WAIT_COND(group, func) \
4140 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4141
4142 /* CLASS 24 - MRC */
4143 #define H2C_CL_MRC 0x18
4144 enum rtw89_mrc_h2c_func {
4145 H2C_FUNC_MRC_REQ_TSF = 0x0,
4146 H2C_FUNC_ADD_MRC = 0x1,
4147 H2C_FUNC_START_MRC = 0x2,
4148 H2C_FUNC_DEL_MRC = 0x3,
4149 H2C_FUNC_MRC_SYNC = 0x4,
4150 H2C_FUNC_MRC_UPD_DURATION = 0x5,
4151 H2C_FUNC_MRC_UPD_BITMAP = 0x6,
4152
4153 NUM_OF_RTW89_MRC_H2C_FUNC,
4154 };
4155
4156 /* can consider MRC's sch_idx as MCC's group */
4157 #define RTW89_MRC_WAIT_COND(sch_idx, func) \
4158 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4159
4160 #define RTW89_MRC_WAIT_COND_REQ_TSF \
4161 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4162
4163 #define H2C_CAT_OUTSRC 0x2
4164
4165 #define H2C_CL_OUTSRC_RA 0x1
4166 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
4167
4168 #define H2C_CL_OUTSRC_DM 0x2
4169 #define H2C_FUNC_FW_LPS_CH_INFO 0xb
4170
4171 #define H2C_CL_OUTSRC_RF_REG_A 0x8
4172 #define H2C_CL_OUTSRC_RF_REG_B 0x9
4173 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4174 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4175 #define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4176
4177 enum rtw89_rfk_offload_h2c_func {
4178 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4179 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4180 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4181 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4182 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4183 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4184 H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4185 };
4186
4187 struct rtw89_fw_h2c_rf_get_mccch {
4188 __le32 ch_0;
4189 __le32 ch_1;
4190 __le32 band_0;
4191 __le32 band_1;
4192 __le32 current_channel;
4193 __le32 current_band_type;
4194 } __packed;
4195
4196 #define NUM_OF_RTW89_FW_RFK_PATH 2
4197 #define NUM_OF_RTW89_FW_RFK_TBL 3
4198
4199 struct rtw89_fw_h2c_rfk_pre_info_common {
4200 struct {
4201 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4202 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4203 } __packed dbcc;
4204
4205 __le32 mlo_mode;
4206 struct {
4207 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4208 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4209 } __packed tbl;
4210
4211 __le32 phy_idx;
4212 } __packed;
4213
4214 struct rtw89_fw_h2c_rfk_pre_info_v0 {
4215 struct rtw89_fw_h2c_rfk_pre_info_common common;
4216
4217 __le32 cur_band;
4218 __le32 cur_bw;
4219 __le32 cur_center_ch;
4220
4221 __le32 ktbl_sel0;
4222 __le32 ktbl_sel1;
4223 __le32 rfmod0;
4224 __le32 rfmod1;
4225
4226 __le32 mlo_1_1;
4227 __le32 rfe_type;
4228 __le32 drv_mode;
4229
4230 struct {
4231 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4232 __le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4233 } __packed mlo;
4234 } __packed;
4235
4236 struct rtw89_fw_h2c_rfk_pre_info {
4237 struct rtw89_fw_h2c_rfk_pre_info_common common;
4238 __le32 mlo_1_1;
4239 } __packed;
4240
4241 struct rtw89_h2c_rf_tssi {
4242 __le16 len;
4243 u8 phy;
4244 u8 ch;
4245 u8 bw;
4246 u8 band;
4247 u8 hwtx_en;
4248 u8 cv;
4249 s8 curr_tssi_cck_de[2];
4250 s8 curr_tssi_cck_de_20m[2];
4251 s8 curr_tssi_cck_de_40m[2];
4252 s8 curr_tssi_efuse_cck_de[2];
4253 s8 curr_tssi_ofdm_de[2];
4254 s8 curr_tssi_ofdm_de_20m[2];
4255 s8 curr_tssi_ofdm_de_40m[2];
4256 s8 curr_tssi_ofdm_de_80m[2];
4257 s8 curr_tssi_ofdm_de_160m[2];
4258 s8 curr_tssi_ofdm_de_320m[2];
4259 s8 curr_tssi_efuse_ofdm_de[2];
4260 s8 curr_tssi_ofdm_de_diff_20m[2];
4261 s8 curr_tssi_ofdm_de_diff_80m[2];
4262 s8 curr_tssi_ofdm_de_diff_160m[2];
4263 s8 curr_tssi_ofdm_de_diff_320m[2];
4264 s8 curr_tssi_trim_de[2];
4265 u8 pg_thermal[2];
4266 u8 ftable[2][128];
4267 u8 tssi_mode;
4268 } __packed;
4269
4270 struct rtw89_h2c_rf_iqk {
4271 __le32 phy_idx;
4272 __le32 dbcc;
4273 } __packed;
4274
4275 struct rtw89_h2c_rf_dpk {
4276 u8 len;
4277 u8 phy;
4278 u8 dpk_enable;
4279 u8 kpath;
4280 u8 cur_band;
4281 u8 cur_bw;
4282 u8 cur_ch;
4283 u8 dpk_dbg_en;
4284 } __packed;
4285
4286 struct rtw89_h2c_rf_txgapk {
4287 u8 len;
4288 u8 ktype;
4289 u8 phy;
4290 u8 kpath;
4291 u8 band;
4292 u8 bw;
4293 u8 ch;
4294 u8 cv;
4295 } __packed;
4296
4297 struct rtw89_h2c_rf_dack {
4298 __le32 len;
4299 __le32 phy;
4300 __le32 type;
4301 } __packed;
4302
4303 struct rtw89_h2c_rf_rxdck {
4304 u8 len;
4305 u8 phy;
4306 u8 is_afe;
4307 u8 kpath;
4308 u8 cur_band;
4309 u8 cur_bw;
4310 u8 cur_ch;
4311 u8 rxdck_dbg_en;
4312 } __packed;
4313
4314 enum rtw89_rf_log_type {
4315 RTW89_RF_RUN_LOG = 0,
4316 RTW89_RF_RPT_LOG = 1,
4317 };
4318
4319 struct rtw89_c2h_rf_log_hdr {
4320 u8 type; /* enum rtw89_rf_log_type */
4321 __le16 len;
4322 u8 content[];
4323 } __packed;
4324
4325 struct rtw89_c2h_rf_run_log {
4326 __le32 fmt_idx;
4327 __le32 arg[4];
4328 } __packed;
4329
4330 struct rtw89_c2h_rf_dpk_rpt_log {
4331 u8 ver;
4332 u8 idx[2];
4333 u8 band[2];
4334 u8 bw[2];
4335 u8 ch[2];
4336 u8 path_ok[2];
4337 u8 txagc[2];
4338 u8 ther[2];
4339 u8 gs[2];
4340 u8 dc_i[4];
4341 u8 dc_q[4];
4342 u8 corr_val[2];
4343 u8 corr_idx[2];
4344 u8 is_timeout[2];
4345 u8 rxbb_ov[2];
4346 u8 rsvd;
4347 } __packed;
4348
4349 struct rtw89_c2h_rf_dack_rpt_log {
4350 u8 fwdack_ver;
4351 u8 fwdack_rpt_ver;
4352 u8 msbk_d[2][2][16];
4353 u8 dadck_d[2][2];
4354 u8 cdack_d[2][2][2];
4355 __le16 addck2_d[2][2][2];
4356 u8 adgaink_d[2][2];
4357 __le16 biask_d[2][2];
4358 u8 addck_timeout;
4359 u8 cdack_timeout;
4360 u8 dadck_timeout;
4361 u8 msbk_timeout;
4362 u8 adgaink_timeout;
4363 u8 dack_fail;
4364 } __packed;
4365
4366 struct rtw89_c2h_rf_rxdck_rpt_log {
4367 u8 ver;
4368 u8 band[2];
4369 u8 bw[2];
4370 u8 ch[2];
4371 u8 timeout[2];
4372 } __packed;
4373
4374 struct rtw89_c2h_rf_txgapk_rpt_log {
4375 __le32 r0x8010[2];
4376 __le32 chk_cnt;
4377 u8 track_d[2][17];
4378 u8 power_d[2][17];
4379 u8 is_txgapk_ok;
4380 u8 chk_id;
4381 u8 ver;
4382 u8 rsv1;
4383 } __packed;
4384
4385 struct rtw89_c2h_rfk_report {
4386 struct rtw89_c2h_hdr hdr;
4387 u8 state; /* enum rtw89_rfk_report_state */
4388 u8 version;
4389 } __packed;
4390
4391 #define RTW89_FW_RSVD_PLE_SIZE 0x800
4392
4393 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
4394 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
4395 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
4396
4397 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
4398 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
4399
4400 #define FWDL_WAIT_CNT 400000
4401
4402 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
4403 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
4404 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
4405 const struct firmware *
4406 rtw89_early_fw_feature_recognize(struct device *device,
4407 const struct rtw89_chip_info *chip,
4408 struct rtw89_fw_info *early_fw,
4409 int *used_fw_format);
4410 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
4411 bool include_bb);
4412 void rtw89_load_firmware_work(struct work_struct *work);
4413 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
4414 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
4415 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
4416 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
4417 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4418 u8 type, u8 cat, u8 class, u8 func,
4419 bool rack, bool dack, u32 len);
4420 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4421 struct rtw89_vif_link *rtwvif_link,
4422 struct rtw89_sta_link *rtwsta_link);
4423 int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4424 struct rtw89_vif_link *rtwvif_link,
4425 struct rtw89_sta_link *rtwsta_link);
4426 int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
4427 struct rtw89_vif_link *rtwvif_link,
4428 struct rtw89_sta_link *rtwsta_link);
4429 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4430 struct rtw89_vif_link *rtwvif_link,
4431 struct rtw89_sta_link *rtwsta_link);
4432 int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4433 struct rtw89_vif_link *rtwvif_link,
4434 struct rtw89_sta_link *rtwsta_link);
4435 int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4436 struct rtw89_vif_link *rtwvif_link,
4437 struct rtw89_sta_link *rtwsta_link);
4438 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4439 struct rtw89_sta_link *rtwsta_link);
4440 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
4441 struct rtw89_sta_link *rtwsta_link);
4442 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
4443 struct rtw89_vif_link *rtwvif_link);
4444 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
4445 struct rtw89_vif_link *rtwvif_link);
4446 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif,
4447 struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr);
4448 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
4449 struct rtw89_vif_link *rtwvif_link,
4450 struct rtw89_sta_link *rtwsta_link);
4451 int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
4452 struct rtw89_vif_link *rtwvif_link,
4453 struct rtw89_sta_link *rtwsta_link);
4454 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
4455 void rtw89_fw_c2h_work(struct work_struct *work);
4456 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
4457 struct rtw89_vif_link *rtwvif_link,
4458 struct rtw89_sta_link *rtwsta_link,
4459 enum rtw89_upd_mode upd_mode);
4460 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4461 struct rtw89_sta_link *rtwsta_link, bool dis_conn);
4462 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
4463 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
4464 bool pause);
4465 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4466 u8 ac, u32 val);
4467 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
4468 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
4469 struct rtw89_vif_link *rtwvif_link,
4470 bool connect);
4471 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
4472 struct rtw89_rx_phy_ppdu *phy_ppdu);
4473 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
4474 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
4475 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
4476 int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
4477 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
4478 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
4479 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
4480 int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type);
4481 int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type);
4482 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
4483 int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
4484 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type);
4485 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
4486 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
4487 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
4488 struct sk_buff *skb_ofld);
4489 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int ch_num,
4490 struct list_head *chan_list);
4491 int rtw89_fw_h2c_scan_list_offload_be(struct rtw89_dev *rtwdev, int ch_num,
4492 struct list_head *chan_list);
4493 int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev,
4494 struct rtw89_scan_option *opt,
4495 struct rtw89_vif_link *vif,
4496 bool wowlan);
4497 int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
4498 struct rtw89_scan_option *opt,
4499 struct rtw89_vif_link *vif,
4500 bool wowlan);
4501 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
4502 struct rtw89_fw_h2c_rf_reg_info *info,
4503 u16 len, u8 page);
4504 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
4505 int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
4506 enum rtw89_phy_idx phy_idx);
4507 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4508 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode);
4509 int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4510 const struct rtw89_chan *chan);
4511 int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4512 const struct rtw89_chan *chan);
4513 int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4514 const struct rtw89_chan *chan);
4515 int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4516 const struct rtw89_chan *chan);
4517 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4518 const struct rtw89_chan *chan);
4519 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
4520 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
4521 bool rack, bool dack);
4522 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
4523 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
4524 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4525 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4526 u8 macid);
4527 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
4528 struct rtw89_vif_link *rtwvif_link,
4529 bool notify_fw);
4530 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
4531 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev,
4532 struct rtw89_vif_link *rtwvif_link,
4533 struct rtw89_sta_link *rtwsta_link,
4534 bool valid, struct ieee80211_ampdu_params *params);
4535 int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev,
4536 struct rtw89_vif_link *rtwvif_link,
4537 struct rtw89_sta_link *rtwsta_link,
4538 bool valid, struct ieee80211_ampdu_params *params);
4539 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
4540 int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
4541 u8 offset, u8 mac_idx);
4542
4543 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
4544 struct rtw89_lps_parm *lps_param);
4545 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev,
4546 struct rtw89_vif_link *rtwvif_link);
4547 int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4548 bool enable);
4549 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
4550 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
4551 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
4552 struct rtw89_mac_h2c_info *h2c_info,
4553 struct rtw89_mac_c2h_info *c2h_info);
4554 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
4555 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
4556 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
4557 struct rtw89_vif_link *rtwvif_link,
4558 struct ieee80211_scan_request *scan_req);
4559 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev,
4560 struct rtw89_vif_link *rtwvif_link,
4561 bool aborted);
4562 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev,
4563 struct rtw89_vif_link *rtwvif_link,
4564 bool enable);
4565 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev,
4566 struct rtw89_vif_link *rtwvif_link);
4567 int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4568 struct rtw89_vif_link *rtwvif_link, bool connected);
4569 int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4570 struct rtw89_vif_link *rtwvif_link);
4571 int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4572 struct rtw89_vif_link *rtwvif_link, bool connected);
4573 int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4574 struct rtw89_vif_link *rtwvif_link);
4575 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
4576 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
4577 const struct rtw89_pkt_drop_params *params);
4578 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev,
4579 struct rtw89_vif_link *rtwvif_link,
4580 struct ieee80211_bss_conf *bss_conf,
4581 struct ieee80211_p2p_noa_desc *desc,
4582 u8 act, u8 noa_id);
4583 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev,
4584 struct rtw89_vif_link *rtwvif_link,
4585 bool en);
4586 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4587 bool enable);
4588 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4589 struct rtw89_vif_link *rtwvif_link, bool enable);
4590 int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4591 bool enable);
4592 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4593 bool enable);
4594 int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev,
4595 struct rtw89_vif_link *rtwvif_link, bool enable);
4596 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
4597 struct rtw89_vif_link *rtwvif_link, bool enable);
4598 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4599 bool enable);
4600 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4601 struct rtw89_vif_link *rtwvif_link, bool enable);
4602 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
4603 struct rtw89_wow_cam_info *cam_info);
4604 int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
4605 struct rtw89_vif_link *rtwvif_link,
4606 bool enable);
4607 int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev);
4608 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
4609 const struct rtw89_fw_mcc_add_req *p);
4610 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
4611 const struct rtw89_fw_mcc_start_req *p);
4612 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4613 bool prev_groups);
4614 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
4615 bool prev_groups);
4616 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
4617 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
4618 const struct rtw89_fw_mcc_tsf_req *req,
4619 struct rtw89_mac_mcc_tsf_rpt *rpt);
4620 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4621 u8 *bitmap);
4622 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
4623 u8 target, u8 offset);
4624 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
4625 const struct rtw89_fw_mcc_duration *p);
4626 int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
4627 const struct rtw89_fw_mrc_add_arg *arg);
4628 int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
4629 const struct rtw89_fw_mrc_start_arg *arg);
4630 int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx);
4631 int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
4632 const struct rtw89_fw_mrc_req_tsf_arg *arg,
4633 struct rtw89_mac_mrc_tsf_rpt *rpt);
4634 int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
4635 const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
4636 int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
4637 const struct rtw89_fw_mrc_sync_arg *arg);
4638 int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
4639 const struct rtw89_fw_mrc_upd_duration_arg *arg);
4640
rtw89_fw_h2c_init_ba_cam(struct rtw89_dev * rtwdev)4641 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
4642 {
4643 const struct rtw89_chip_info *chip = rtwdev->chip;
4644
4645 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
4646 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
4647 }
4648
rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4649 static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4650 struct rtw89_vif_link *rtwvif_link,
4651 struct rtw89_sta_link *rtwsta_link)
4652 {
4653 const struct rtw89_chip_info *chip = rtwdev->chip;
4654
4655 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4656 }
4657
rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4658 static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
4659 struct rtw89_vif_link *rtwvif_link,
4660 struct rtw89_sta_link *rtwsta_link)
4661 {
4662 const struct rtw89_chip_info *chip = rtwdev->chip;
4663
4664 if (chip->ops->h2c_default_dmac_tbl)
4665 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4666
4667 return 0;
4668 }
4669
rtw89_chip_h2c_update_beacon(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4670 static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
4671 struct rtw89_vif_link *rtwvif_link)
4672 {
4673 const struct rtw89_chip_info *chip = rtwdev->chip;
4674
4675 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link);
4676 }
4677
rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4678 static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4679 struct rtw89_vif_link *rtwvif_link,
4680 struct rtw89_sta_link *rtwsta_link)
4681 {
4682 const struct rtw89_chip_info *chip = rtwdev->chip;
4683
4684 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4685 }
4686
4687 static inline
rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4688 int rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev *rtwdev,
4689 struct rtw89_vif_link *rtwvif_link,
4690 struct rtw89_sta_link *rtwsta_link)
4691 {
4692 const struct rtw89_chip_info *chip = rtwdev->chip;
4693
4694 if (chip->ops->h2c_ampdu_cmac_tbl)
4695 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link,
4696 rtwsta_link);
4697
4698 return 0;
4699 }
4700
rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)4701 static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
4702 struct rtw89_vif *rtwvif,
4703 struct rtw89_sta *rtwsta)
4704 {
4705 struct rtw89_vif_link *rtwvif_link;
4706 struct rtw89_sta_link *rtwsta_link;
4707 unsigned int link_id;
4708 int ret;
4709
4710 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
4711 rtwvif_link = rtwsta_link->rtwvif_link;
4712 ret = rtw89_chip_h2c_ampdu_link_cmac_tbl(rtwdev, rtwvif_link,
4713 rtwsta_link);
4714 if (ret)
4715 return ret;
4716 }
4717
4718 return 0;
4719 }
4720
4721 static inline
rtw89_chip_h2c_ba_cam(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool valid,struct ieee80211_ampdu_params * params)4722 int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4723 bool valid, struct ieee80211_ampdu_params *params)
4724 {
4725 const struct rtw89_chip_info *chip = rtwdev->chip;
4726 struct rtw89_vif_link *rtwvif_link;
4727 struct rtw89_sta_link *rtwsta_link;
4728 unsigned int link_id;
4729 int ret;
4730
4731 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
4732 rtwvif_link = rtwsta_link->rtwvif_link;
4733 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link,
4734 valid, params);
4735 if (ret)
4736 return ret;
4737 }
4738
4739 return 0;
4740 }
4741
4742 /* must consider compatibility; don't insert new in the mid */
4743 struct rtw89_fw_txpwr_byrate_entry {
4744 u8 band;
4745 u8 nss;
4746 u8 rs;
4747 u8 shf;
4748 u8 len;
4749 __le32 data;
4750 u8 bw;
4751 u8 ofdma;
4752 } __packed;
4753
4754 /* must consider compatibility; don't insert new in the mid */
4755 struct rtw89_fw_txpwr_lmt_2ghz_entry {
4756 u8 bw;
4757 u8 nt;
4758 u8 rs;
4759 u8 bf;
4760 u8 regd;
4761 u8 ch_idx;
4762 s8 v;
4763 } __packed;
4764
4765 /* must consider compatibility; don't insert new in the mid */
4766 struct rtw89_fw_txpwr_lmt_5ghz_entry {
4767 u8 bw;
4768 u8 nt;
4769 u8 rs;
4770 u8 bf;
4771 u8 regd;
4772 u8 ch_idx;
4773 s8 v;
4774 } __packed;
4775
4776 /* must consider compatibility; don't insert new in the mid */
4777 struct rtw89_fw_txpwr_lmt_6ghz_entry {
4778 u8 bw;
4779 u8 nt;
4780 u8 rs;
4781 u8 bf;
4782 u8 regd;
4783 u8 reg_6ghz_power;
4784 u8 ch_idx;
4785 s8 v;
4786 } __packed;
4787
4788 /* must consider compatibility; don't insert new in the mid */
4789 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
4790 u8 ru;
4791 u8 nt;
4792 u8 regd;
4793 u8 ch_idx;
4794 s8 v;
4795 } __packed;
4796
4797 /* must consider compatibility; don't insert new in the mid */
4798 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
4799 u8 ru;
4800 u8 nt;
4801 u8 regd;
4802 u8 ch_idx;
4803 s8 v;
4804 } __packed;
4805
4806 /* must consider compatibility; don't insert new in the mid */
4807 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
4808 u8 ru;
4809 u8 nt;
4810 u8 regd;
4811 u8 reg_6ghz_power;
4812 u8 ch_idx;
4813 s8 v;
4814 } __packed;
4815
4816 /* must consider compatibility; don't insert new in the mid */
4817 struct rtw89_fw_tx_shape_lmt_entry {
4818 u8 band;
4819 u8 tx_shape_rs;
4820 u8 regd;
4821 u8 v;
4822 } __packed;
4823
4824 /* must consider compatibility; don't insert new in the mid */
4825 struct rtw89_fw_tx_shape_lmt_ru_entry {
4826 u8 band;
4827 u8 regd;
4828 u8 v;
4829 } __packed;
4830
4831 const struct rtw89_rfe_parms *
4832 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
4833 const struct rtw89_rfe_parms *init);
4834
4835 enum rtw89_wow_wakeup_ver {
4836 RTW89_WOW_REASON_V0,
4837 RTW89_WOW_REASON_V1,
4838 RTW89_WOW_REASON_NUM,
4839 };
4840
4841 #endif
4842