1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #ifndef PMF_H 12 #define PMF_H 13 14 #include <linux/acpi.h> 15 #include <linux/input.h> 16 #include <linux/platform_profile.h> 17 18 #define POLICY_BUF_MAX_SZ 0x4b000 19 #define POLICY_SIGN_COOKIE 0x31535024 20 #define POLICY_COOKIE_OFFSET 0x10 21 22 /* List of supported CPU ids */ 23 #define AMD_CPU_ID_RMB 0x14b5 24 #define AMD_CPU_ID_PS 0x14e8 25 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 26 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 27 28 struct cookie_header { 29 u32 sign; 30 u32 length; 31 } __packed; 32 33 /* APMF Functions */ 34 #define APMF_FUNC_VERIFY_INTERFACE 0 35 #define APMF_FUNC_GET_SYS_PARAMS 1 36 #define APMF_FUNC_SBIOS_REQUESTS 2 37 #define APMF_FUNC_SBIOS_HEARTBEAT 4 38 #define APMF_FUNC_AUTO_MODE 5 39 #define APMF_FUNC_SET_FAN_IDX 7 40 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 41 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 42 #define APMF_FUNC_DYN_SLIDER_AC 11 43 #define APMF_FUNC_DYN_SLIDER_DC 12 44 #define APMF_FUNC_NOTIFY_SMART_PC_UPDATES 14 45 #define APMF_FUNC_SBIOS_HEARTBEAT_V2 16 46 47 /* Message Definitions */ 48 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ 49 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ 50 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ 51 #define GET_SPL 0x0B 52 #define GET_SPPT 0x0D 53 #define GET_FPPT 0x0F 54 #define SET_DRAM_ADDR_HIGH 0x14 55 #define SET_DRAM_ADDR_LOW 0x15 56 #define SET_TRANSFER_TABLE 0x16 57 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ 58 #define SET_STT_LIMIT_APU 0x19 59 #define SET_STT_LIMIT_HS2 0x1A 60 #define SET_SPPT_APU_ONLY 0x1D 61 #define GET_SPPT_APU_ONLY 0x1E 62 #define GET_STT_MIN_LIMIT 0x1F 63 #define GET_STT_LIMIT_APU 0x20 64 #define GET_STT_LIMIT_HS2 0x21 65 #define SET_P3T 0x23 /* P3T: Peak Package Power Limit */ 66 #define SET_PMF_PPT 0x25 67 #define SET_PMF_PPT_APU_ONLY 0x26 68 69 /* OS slider update notification */ 70 #define DC_BEST_PERF 0 71 #define DC_BETTER_PERF 1 72 #define DC_BATTERY_SAVER 3 73 #define AC_BEST_PERF 4 74 #define AC_BETTER_PERF 5 75 #define AC_BETTER_BATTERY 6 76 77 /* Fan Index for Auto Mode */ 78 #define FAN_INDEX_AUTO 0xFFFFFFFF 79 80 #define ARG_NONE 0 81 #define AVG_SAMPLE_SIZE 3 82 83 /* Policy Actions */ 84 #define PMF_POLICY_SPL 2 85 #define PMF_POLICY_SPPT 3 86 #define PMF_POLICY_FPPT 4 87 #define PMF_POLICY_SPPT_APU_ONLY 5 88 #define PMF_POLICY_STT_MIN 6 89 #define PMF_POLICY_STT_SKINTEMP_APU 7 90 #define PMF_POLICY_STT_SKINTEMP_HS2 8 91 #define PMF_POLICY_SYSTEM_STATE 9 92 #define PMF_POLICY_BIOS_OUTPUT_1 10 93 #define PMF_POLICY_BIOS_OUTPUT_2 11 94 #define PMF_POLICY_P3T 38 95 #define PMF_POLICY_BIOS_OUTPUT_3 57 96 #define PMF_POLICY_BIOS_OUTPUT_4 58 97 #define PMF_POLICY_BIOS_OUTPUT_5 59 98 #define PMF_POLICY_BIOS_OUTPUT_6 60 99 #define PMF_POLICY_BIOS_OUTPUT_7 61 100 #define PMF_POLICY_BIOS_OUTPUT_8 62 101 #define PMF_POLICY_BIOS_OUTPUT_9 63 102 #define PMF_POLICY_BIOS_OUTPUT_10 64 103 104 /* TA macros */ 105 #define PMF_TA_IF_VERSION_MAJOR 1 106 #define TA_PMF_ACTION_MAX 32 107 #define TA_PMF_UNDO_MAX 8 108 #define TA_OUTPUT_RESERVED_MEM 922 109 #define MAX_OPERATION_PARAMS 4 110 111 #define TA_ERROR_CRYPTO_INVALID_PARAM 0x20002 112 #define TA_ERROR_CRYPTO_BIN_TOO_LARGE 0x2000d 113 114 #define PMF_IF_V1 1 115 #define PMF_IF_V2 2 116 117 #define APTS_MAX_STATES 16 118 119 /* APTS PMF BIOS Interface */ 120 struct amd_pmf_apts_output { 121 u16 table_version; 122 u32 fan_table_idx; 123 u32 pmf_ppt; 124 u32 ppt_pmf_apu_only; 125 u32 stt_min_limit; 126 u8 stt_skin_temp_limit_apu; 127 u8 stt_skin_temp_limit_hs2; 128 } __packed; 129 130 struct amd_pmf_apts_granular_output { 131 u16 size; 132 struct amd_pmf_apts_output val; 133 } __packed; 134 135 struct amd_pmf_apts_granular { 136 u16 size; 137 struct amd_pmf_apts_output val[APTS_MAX_STATES]; 138 }; 139 140 struct sbios_hb_event_v2 { 141 u16 size; 142 u8 load; 143 u8 unload; 144 u8 suspend; 145 u8 resume; 146 } __packed; 147 148 enum sbios_hb_v2 { 149 ON_LOAD, 150 ON_UNLOAD, 151 ON_SUSPEND, 152 ON_RESUME, 153 }; 154 155 /* AMD PMF BIOS interfaces */ 156 struct apmf_verify_interface { 157 u16 size; 158 u16 version; 159 u32 notification_mask; 160 u32 supported_functions; 161 } __packed; 162 163 struct apmf_system_params { 164 u16 size; 165 u32 valid_mask; 166 u32 flags; 167 u8 command_code; 168 u32 heartbeat_int; 169 } __packed; 170 171 struct apmf_sbios_req { 172 u16 size; 173 u32 pending_req; 174 u8 rsd; 175 u8 cql_event; 176 u8 amt_event; 177 u32 fppt; 178 u32 sppt; 179 u32 fppt_apu_only; 180 u32 spl; 181 u32 stt_min_limit; 182 u8 skin_temp_apu; 183 u8 skin_temp_hs2; 184 } __packed; 185 186 struct apmf_sbios_req_v2 { 187 u16 size; 188 u32 pending_req; 189 u8 rsd; 190 u32 ppt_pmf; 191 u32 ppt_pmf_apu_only; 192 u32 stt_min_limit; 193 u8 skin_temp_apu; 194 u8 skin_temp_hs2; 195 u32 custom_policy[10]; 196 } __packed; 197 198 struct apmf_fan_idx { 199 u16 size; 200 u8 fan_ctl_mode; 201 u32 fan_ctl_idx; 202 } __packed; 203 204 struct smu_pmf_metrics_v2 { 205 u16 core_frequency[16]; /* MHz */ 206 u16 core_power[16]; /* mW */ 207 u16 core_temp[16]; /* centi-C */ 208 u16 gfx_temp; /* centi-C */ 209 u16 soc_temp; /* centi-C */ 210 u16 stapm_opn_limit; /* mW */ 211 u16 stapm_cur_limit; /* mW */ 212 u16 infra_cpu_maxfreq; /* MHz */ 213 u16 infra_gfx_maxfreq; /* MHz */ 214 u16 skin_temp; /* centi-C */ 215 u16 gfxclk_freq; /* MHz */ 216 u16 fclk_freq; /* MHz */ 217 u16 gfx_activity; /* GFX busy % [0-100] */ 218 u16 socclk_freq; /* MHz */ 219 u16 vclk_freq; /* MHz */ 220 u16 vcn_activity; /* VCN busy % [0-100] */ 221 u16 vpeclk_freq; /* MHz */ 222 u16 ipuclk_freq; /* MHz */ 223 u16 ipu_busy[8]; /* NPU busy % [0-100] */ 224 u16 dram_reads; /* MB/sec */ 225 u16 dram_writes; /* MB/sec */ 226 u16 core_c0residency[16]; /* C0 residency % [0-100] */ 227 u16 ipu_power; /* mW */ 228 u32 apu_power; /* mW */ 229 u32 gfx_power; /* mW */ 230 u32 dgpu_power; /* mW */ 231 u32 socket_power; /* mW */ 232 u32 all_core_power; /* mW */ 233 u32 filter_alpha_value; /* time constant [us] */ 234 u32 metrics_counter; 235 u16 memclk_freq; /* MHz */ 236 u16 mpipuclk_freq; /* MHz */ 237 u16 ipu_reads; /* MB/sec */ 238 u16 ipu_writes; /* MB/sec */ 239 u32 throttle_residency_prochot; 240 u32 throttle_residency_spl; 241 u32 throttle_residency_fppt; 242 u32 throttle_residency_sppt; 243 u32 throttle_residency_thm_core; 244 u32 throttle_residency_thm_gfx; 245 u32 throttle_residency_thm_soc; 246 u16 psys; 247 u16 spare1; 248 u32 spare[6]; 249 } __packed; 250 251 struct smu_pmf_metrics { 252 u16 gfxclk_freq; /* in MHz */ 253 u16 socclk_freq; /* in MHz */ 254 u16 vclk_freq; /* in MHz */ 255 u16 dclk_freq; /* in MHz */ 256 u16 memclk_freq; /* in MHz */ 257 u16 spare; 258 u16 gfx_activity; /* in Centi */ 259 u16 uvd_activity; /* in Centi */ 260 u16 voltage[2]; /* in mV */ 261 u16 currents[2]; /* in mA */ 262 u16 power[2];/* in mW */ 263 u16 core_freq[8]; /* in MHz */ 264 u16 core_power[8]; /* in mW */ 265 u16 core_temp[8]; /* in centi-Celsius */ 266 u16 l3_freq; /* in MHz */ 267 u16 l3_temp; /* in centi-Celsius */ 268 u16 gfx_temp; /* in centi-Celsius */ 269 u16 soc_temp; /* in centi-Celsius */ 270 u16 throttler_status; 271 u16 current_socketpower; /* in mW */ 272 u16 stapm_orig_limit; /* in W */ 273 u16 stapm_cur_limit; /* in W */ 274 u32 apu_power; /* in mW */ 275 u32 dgpu_power; /* in mW */ 276 u16 vdd_tdc_val; /* in mA */ 277 u16 soc_tdc_val; /* in mA */ 278 u16 vdd_edc_val; /* in mA */ 279 u16 soc_edcv_al; /* in mA */ 280 u16 infra_cpu_maxfreq; /* in MHz */ 281 u16 infra_gfx_maxfreq; /* in MHz */ 282 u16 skin_temp; /* in centi-Celsius */ 283 u16 device_state; 284 u16 curtemp; /* in centi-Celsius */ 285 u16 filter_alpha_value; 286 u16 avg_gfx_clkfrequency; 287 u16 avg_fclk_frequency; 288 u16 avg_gfx_activity; 289 u16 avg_socclk_frequency; 290 u16 avg_vclk_frequency; 291 u16 avg_vcn_activity; 292 u16 avg_dram_reads; 293 u16 avg_dram_writes; 294 u16 avg_socket_power; 295 u16 avg_core_power[2]; 296 u16 avg_core_c0residency[16]; 297 u16 spare1; 298 u32 metrics_counter; 299 } __packed; 300 301 enum amd_stt_skin_temp { 302 STT_TEMP_APU, 303 STT_TEMP_HS2, 304 STT_TEMP_COUNT, 305 }; 306 307 enum amd_slider_op { 308 SLIDER_OP_GET, 309 SLIDER_OP_SET, 310 }; 311 312 enum power_source { 313 POWER_SOURCE_AC, 314 POWER_SOURCE_DC, 315 POWER_SOURCE_MAX, 316 }; 317 318 enum power_modes { 319 POWER_MODE_PERFORMANCE, 320 POWER_MODE_BALANCED_POWER, 321 POWER_MODE_POWER_SAVER, 322 POWER_MODE_MAX, 323 }; 324 325 enum power_modes_v2 { 326 POWER_MODE_BEST_PERFORMANCE, 327 POWER_MODE_BALANCED, 328 POWER_MODE_BEST_POWER_EFFICIENCY, 329 POWER_MODE_ENERGY_SAVE, 330 POWER_MODE_V2_MAX, 331 }; 332 333 struct amd_pmf_dev { 334 void __iomem *regbase; 335 void __iomem *smu_virt_addr; 336 void *buf; 337 u32 base_addr; 338 u32 cpu_id; 339 struct device *dev; 340 struct mutex lock; /* protects the PMF interface */ 341 u32 supported_func; 342 enum platform_profile_option current_profile; 343 struct platform_profile_handler pprof; 344 struct dentry *dbgfs_dir; 345 int hb_interval; /* SBIOS heartbeat interval */ 346 struct delayed_work heart_beat; 347 struct smu_pmf_metrics m_table; 348 struct smu_pmf_metrics_v2 m_table_v2; 349 struct delayed_work work_buffer; 350 ktime_t start_time; 351 int socket_power_history[AVG_SAMPLE_SIZE]; 352 int socket_power_history_idx; 353 bool amt_enabled; 354 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */ 355 bool cnqf_enabled; 356 bool cnqf_supported; 357 struct notifier_block pwr_src_notifier; 358 /* Smart PC solution builder */ 359 struct dentry *esbin; 360 unsigned char *policy_buf; 361 u32 policy_sz; 362 struct tee_context *tee_ctx; 363 struct tee_shm *fw_shm_pool; 364 u32 session_id; 365 void *shbuf; 366 struct delayed_work pb_work; 367 struct pmf_action_table *prev_data; 368 u64 policy_addr; 369 void __iomem *policy_base; 370 bool smart_pc_enabled; 371 u16 pmf_if_version; 372 struct input_dev *pmf_idev; 373 size_t mtable_size; 374 }; 375 376 struct apmf_sps_prop_granular_v2 { 377 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX]; 378 } __packed; 379 380 struct apmf_sps_prop_granular { 381 u32 fppt; 382 u32 sppt; 383 u32 sppt_apu_only; 384 u32 spl; 385 u32 stt_min; 386 u8 stt_skin_temp[STT_TEMP_COUNT]; 387 u32 fan_id; 388 } __packed; 389 390 /* Static Slider */ 391 struct apmf_static_slider_granular_output { 392 u16 size; 393 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; 394 } __packed; 395 396 struct amd_pmf_static_slider_granular { 397 u16 size; 398 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 399 }; 400 401 struct apmf_static_slider_granular_output_v2 { 402 u16 size; 403 struct apmf_sps_prop_granular_v2 sps_idx; 404 } __packed; 405 406 struct amd_pmf_static_slider_granular_v2 { 407 u16 size; 408 struct apmf_sps_prop_granular_v2 sps_idx; 409 }; 410 411 struct os_power_slider { 412 u16 size; 413 u8 slider_event; 414 } __packed; 415 416 struct amd_pmf_notify_smart_pc_update { 417 u16 size; 418 u32 pending_req; 419 u32 custom_bios[10]; 420 } __packed; 421 422 struct fan_table_control { 423 bool manual; 424 unsigned long fan_id; 425 }; 426 427 struct power_table_control { 428 u32 spl; 429 u32 sppt; 430 u32 fppt; 431 u32 sppt_apu_only; 432 u32 stt_min; 433 u32 stt_skin_temp[STT_TEMP_COUNT]; 434 u32 reserved[16]; 435 }; 436 437 /* Auto Mode Layer */ 438 enum auto_mode_transition_priority { 439 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ 440 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 441 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 442 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ 443 AUTO_TRANSITION_MAX, 444 }; 445 446 enum auto_mode_mode { 447 AUTO_QUIET, 448 AUTO_BALANCE, 449 AUTO_PERFORMANCE_ON_LAP, 450 AUTO_PERFORMANCE, 451 AUTO_MODE_MAX, 452 }; 453 454 struct auto_mode_trans_params { 455 u32 time_constant; /* minimum time required to switch to next mode */ 456 u32 power_delta; /* delta power to shift mode */ 457 u32 power_threshold; 458 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ 459 u32 applied; 460 enum auto_mode_mode target_mode; 461 u32 shifting_up; 462 }; 463 464 struct auto_mode_mode_settings { 465 struct power_table_control power_control; 466 struct fan_table_control fan_control; 467 u32 power_floor; 468 }; 469 470 struct auto_mode_mode_config { 471 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; 472 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; 473 enum auto_mode_mode current_mode; 474 }; 475 476 struct apmf_auto_mode { 477 u16 size; 478 /* time constant */ 479 u32 balanced_to_perf; 480 u32 perf_to_balanced; 481 u32 quiet_to_balanced; 482 u32 balanced_to_quiet; 483 /* power floor */ 484 u32 pfloor_perf; 485 u32 pfloor_balanced; 486 u32 pfloor_quiet; 487 /* Power delta for mode change */ 488 u32 pd_balanced_to_perf; 489 u32 pd_perf_to_balanced; 490 u32 pd_quiet_to_balanced; 491 u32 pd_balanced_to_quiet; 492 /* skin temperature limits */ 493 u8 stt_apu_perf_on_lap; /* CQL ON */ 494 u8 stt_hs2_perf_on_lap; /* CQL ON */ 495 u8 stt_apu_perf; 496 u8 stt_hs2_perf; 497 u8 stt_apu_balanced; 498 u8 stt_hs2_balanced; 499 u8 stt_apu_quiet; 500 u8 stt_hs2_quiet; 501 u32 stt_min_limit_perf_on_lap; /* CQL ON */ 502 u32 stt_min_limit_perf; 503 u32 stt_min_limit_balanced; 504 u32 stt_min_limit_quiet; 505 /* SPL based */ 506 u32 fppt_perf_on_lap; /* CQL ON */ 507 u32 sppt_perf_on_lap; /* CQL ON */ 508 u32 spl_perf_on_lap; /* CQL ON */ 509 u32 sppt_apu_only_perf_on_lap; /* CQL ON */ 510 u32 fppt_perf; 511 u32 sppt_perf; 512 u32 spl_perf; 513 u32 sppt_apu_only_perf; 514 u32 fppt_balanced; 515 u32 sppt_balanced; 516 u32 spl_balanced; 517 u32 sppt_apu_only_balanced; 518 u32 fppt_quiet; 519 u32 sppt_quiet; 520 u32 spl_quiet; 521 u32 sppt_apu_only_quiet; 522 /* Fan ID */ 523 u32 fan_id_perf; 524 u32 fan_id_balanced; 525 u32 fan_id_quiet; 526 } __packed; 527 528 /* CnQF Layer */ 529 enum cnqf_trans_priority { 530 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ 531 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ 532 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 533 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 534 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ 535 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ 536 CNQF_TRANSITION_MAX, 537 }; 538 539 enum cnqf_mode { 540 CNQF_MODE_QUIET, 541 CNQF_MODE_BALANCE, 542 CNQF_MODE_PERFORMANCE, 543 CNQF_MODE_TURBO, 544 CNQF_MODE_MAX, 545 }; 546 547 enum apmf_cnqf_pos { 548 APMF_CNQF_TURBO, 549 APMF_CNQF_PERFORMANCE, 550 APMF_CNQF_BALANCE, 551 APMF_CNQF_QUIET, 552 APMF_CNQF_MAX, 553 }; 554 555 struct cnqf_mode_settings { 556 struct power_table_control power_control; 557 struct fan_table_control fan_control; 558 u32 power_floor; 559 }; 560 561 struct cnqf_tran_params { 562 u32 time_constant; /* minimum time required to switch to next mode */ 563 u32 power_threshold; 564 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ 565 u32 total_power; 566 u32 count; 567 bool priority; 568 bool shifting_up; 569 enum cnqf_mode target_mode; 570 }; 571 572 struct cnqf_config { 573 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; 574 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; 575 struct power_table_control defaults; 576 enum cnqf_mode current_mode; 577 u32 power_src; 578 u32 avg_power; 579 }; 580 581 struct apmf_cnqf_power_set { 582 u32 pfloor; 583 u32 fppt; 584 u32 sppt; 585 u32 sppt_apu_only; 586 u32 spl; 587 u32 stt_min_limit; 588 u8 stt_skintemp[STT_TEMP_COUNT]; 589 u32 fan_id; 590 } __packed; 591 592 struct apmf_dyn_slider_output { 593 u16 size; 594 u16 flags; 595 u32 t_perf_to_turbo; 596 u32 t_balanced_to_perf; 597 u32 t_quiet_to_balanced; 598 u32 t_balanced_to_quiet; 599 u32 t_perf_to_balanced; 600 u32 t_turbo_to_perf; 601 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; 602 } __packed; 603 604 /* Smart PC - TA internals */ 605 enum system_state { 606 SYSTEM_STATE_S0i3, 607 SYSTEM_STATE_S4, 608 SYSTEM_STATE_SCREEN_LOCK, 609 SYSTEM_STATE_MAX, 610 }; 611 612 enum ta_slider { 613 TA_BEST_BATTERY, 614 TA_BETTER_BATTERY, 615 TA_BETTER_PERFORMANCE, 616 TA_BEST_PERFORMANCE, 617 TA_MAX, 618 }; 619 620 /* Command ids for TA communication */ 621 enum ta_pmf_command { 622 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE, 623 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES, 624 }; 625 626 enum ta_pmf_error_type { 627 TA_PMF_TYPE_SUCCESS, 628 TA_PMF_ERROR_TYPE_GENERIC, 629 TA_PMF_ERROR_TYPE_CRYPTO, 630 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE, 631 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM, 632 TA_PMF_ERROR_TYPE_POLICY_BUILDER, 633 TA_PMF_ERROR_TYPE_PB_CONVERT, 634 TA_PMF_ERROR_TYPE_PB_SETUP, 635 TA_PMF_ERROR_TYPE_PB_ENACT, 636 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO, 637 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO, 638 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION, 639 TA_PMF_ERROR_TYPE_MAX, 640 }; 641 642 struct pmf_action_table { 643 enum system_state system_state; 644 u32 spl; /* in mW */ 645 u32 sppt; /* in mW */ 646 u32 sppt_apuonly; /* in mW */ 647 u32 fppt; /* in mW */ 648 u32 stt_minlimit; /* in mW */ 649 u32 stt_skintemp_apu; /* in C */ 650 u32 stt_skintemp_hs2; /* in C */ 651 u32 p3t_limit; /* in mW */ 652 }; 653 654 /* Input conditions */ 655 struct ta_pmf_condition_info { 656 u32 power_source; 657 u32 bat_percentage; 658 u32 power_slider; 659 u32 lid_state; 660 bool user_present; 661 u32 rsvd1[2]; 662 u32 monitor_count; 663 u32 rsvd2[2]; 664 u32 bat_design; 665 u32 full_charge_capacity; 666 int drain_rate; 667 bool user_engaged; 668 u32 device_state; 669 u32 socket_power; 670 u32 skin_temperature; 671 u32 rsvd3[5]; 672 u32 ambient_light; 673 u32 length; 674 u32 avg_c0residency; 675 u32 max_c0residency; 676 u32 s0i3_entry; 677 u32 gfx_busy; 678 u32 rsvd4[7]; 679 bool camera_state; 680 u32 workload_type; 681 u32 display_type; 682 u32 display_state; 683 u32 rsvd5[150]; 684 }; 685 686 struct ta_pmf_load_policy_table { 687 u32 table_size; 688 u8 table[POLICY_BUF_MAX_SZ]; 689 }; 690 691 /* TA initialization params */ 692 struct ta_pmf_init_table { 693 u32 frequency; /* SMU sampling frequency */ 694 bool validate; 695 bool sku_check; 696 bool metadata_macrocheck; 697 struct ta_pmf_load_policy_table policies_table; 698 }; 699 700 /* Everything the TA needs to Enact Policies */ 701 struct ta_pmf_enact_table { 702 struct ta_pmf_condition_info ev_info; 703 u32 name; 704 }; 705 706 struct ta_pmf_action { 707 u32 action_index; 708 u32 value; 709 }; 710 711 /* Output actions from TA */ 712 struct ta_pmf_enact_result { 713 u32 actions_count; 714 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX]; 715 u32 undo_count; 716 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX]; 717 }; 718 719 union ta_pmf_input { 720 struct ta_pmf_enact_table enact_table; 721 struct ta_pmf_init_table init_table; 722 }; 723 724 union ta_pmf_output { 725 struct ta_pmf_enact_result policy_apply_table; 726 u32 rsvd[TA_OUTPUT_RESERVED_MEM]; 727 }; 728 729 struct ta_pmf_shared_memory { 730 int command_id; 731 int resp_id; 732 u32 pmf_result; 733 u32 if_version; 734 union ta_pmf_output pmf_output; 735 union ta_pmf_input pmf_input; 736 }; 737 738 /* Core Layer */ 739 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); 740 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); 741 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index); 742 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); 743 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 744 int amd_pmf_get_power_source(void); 745 int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 746 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); 747 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer); 748 int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag); 749 u32 fixp_q88_fromint(u32 val); 750 751 /* SPS Layer */ 752 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); 753 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, 754 struct amd_pmf_static_slider_granular *table); 755 int amd_pmf_init_sps(struct amd_pmf_dev *dev); 756 void amd_pmf_deinit_sps(struct amd_pmf_dev *dev); 757 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 758 struct apmf_static_slider_granular_output *output); 759 bool is_pprof_balanced(struct amd_pmf_dev *pmf); 760 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); 761 const char *amd_pmf_source_as_str(unsigned int state); 762 763 const char *amd_pmf_source_as_str(unsigned int state); 764 765 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); 766 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf); 767 int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev, 768 struct apmf_static_slider_granular_output_v2 *data); 769 int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev, 770 struct amd_pmf_apts_granular_output *data, u32 apts_idx); 771 772 /* Auto Mode Layer */ 773 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data); 774 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); 775 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); 776 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); 777 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req); 778 int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req); 779 780 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event); 781 int amd_pmf_reset_amt(struct amd_pmf_dev *dev); 782 void amd_pmf_handle_amt(struct amd_pmf_dev *dev); 783 784 /* CnQF Layer */ 785 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 786 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 787 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev); 788 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); 789 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); 790 extern const struct attribute_group cnqf_feature_attribute_group; 791 792 /* Smart PC builder Layer */ 793 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev); 794 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev); 795 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev); 796 int amd_pmf_smartpc_apply_bios_output(struct amd_pmf_dev *dev, u32 val, u32 preq, u32 idx); 797 798 /* Smart PC - TA interfaces */ 799 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 800 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 801 802 /* Quirk infrastructure */ 803 void amd_pmf_quirks_init(struct amd_pmf_dev *dev); 804 805 #endif /* PMF_H */ 806