1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10 #ifndef MPI3MR_H_INCLUDED
11 #define MPI3MR_H_INCLUDED
12
13 #include <linux/blkdev.h>
14 #include <linux/blk-mq.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/delay.h>
17 #include <linux/dmapool.h>
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/miscdevice.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/aer.h>
27 #include <linux/poll.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/types.h>
31 #include <linux/uaccess.h>
32 #include <linux/utsname.h>
33 #include <linux/workqueue.h>
34 #include <linux/unaligned.h>
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
37 #include <scsi/scsi_dbg.h>
38 #include <scsi/scsi_device.h>
39 #include <scsi/scsi_host.h>
40 #include <scsi/scsi_tcq.h>
41 #include <uapi/scsi/scsi_bsg_mpi3mr.h>
42 #include <scsi/scsi_transport_sas.h>
43
44 #include "mpi/mpi30_transport.h"
45 #include "mpi/mpi30_cnfg.h"
46 #include "mpi/mpi30_image.h"
47 #include "mpi/mpi30_init.h"
48 #include "mpi/mpi30_ioc.h"
49 #include "mpi/mpi30_sas.h"
50 #include "mpi/mpi30_pci.h"
51 #include "mpi/mpi30_tool.h"
52 #include "mpi3mr_debug.h"
53
54 /* Global list and lock for storing multiple adapters managed by the driver */
55 extern spinlock_t mrioc_list_lock;
56 extern struct list_head mrioc_list;
57 extern int prot_mask;
58 extern atomic64_t event_counter;
59
60 #define MPI3MR_DRIVER_VERSION "8.12.0.0.50"
61 #define MPI3MR_DRIVER_RELDATE "05-Sept-2024"
62
63 #define MPI3MR_DRIVER_NAME "mpi3mr"
64 #define MPI3MR_DRIVER_LICENSE "GPL"
65 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
66 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"
67
68 #define MPI3MR_NAME_LENGTH 64
69 #define IOCNAME "%s: "
70
71 #define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024)
72
73 /* Definitions for internal SGL and Chain SGL buffers */
74 #define MPI3MR_PAGE_SIZE_4K 4096
75 #define MPI3MR_DEFAULT_SGL_ENTRIES 256
76 #define MPI3MR_MAX_SGL_ENTRIES 2048
77
78 /* Definitions for MAX values for shost */
79 #define MPI3MR_MAX_CMDS_LUN 128
80 #define MPI3MR_MAX_CDB_LENGTH 32
81
82 /* Admin queue management definitions */
83 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K)
84 #define MPI3MR_ADMIN_REPLY_Q_SIZE (8 * MPI3MR_PAGE_SIZE_4K)
85 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128
86 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16
87
88 /* Operational queue management definitions */
89 #define MPI3MR_OP_REQ_Q_QD 512
90 #define MPI3MR_OP_REP_Q_QD 1024
91 #define MPI3MR_OP_REP_Q_QD2K 2048
92 #define MPI3MR_OP_REP_Q_QD4K 4096
93 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096
94 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096
95 #define MPI3MR_MAX_SEG_LIST_SIZE 4096
96
97 /* Reserved Host Tag definitions */
98 #define MPI3MR_HOSTTAG_INVALID 0xFFFF
99 #define MPI3MR_HOSTTAG_INITCMDS 1
100 #define MPI3MR_HOSTTAG_BSG_CMDS 2
101 #define MPI3MR_HOSTTAG_PEL_ABORT 3
102 #define MPI3MR_HOSTTAG_PEL_WAIT 4
103 #define MPI3MR_HOSTTAG_BLK_TMS 5
104 #define MPI3MR_HOSTTAG_CFG_CMDS 6
105 #define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7
106
107 #define MPI3MR_NUM_DEVRMCMD 16
108 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1)
109 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
110 MPI3MR_NUM_DEVRMCMD - 1)
111
112 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
113 #define MPI3MR_NUM_EVTACKCMD 4
114 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
115 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
116 MPI3MR_NUM_EVTACKCMD - 1)
117
118 /* Reduced resource count definition for crash kernel */
119 #define MPI3MR_HOST_IOS_KDUMP 128
120
121 /* command/controller interaction timeout definitions in seconds */
122 #define MPI3MR_INTADMCMD_TIMEOUT 60
123 #define MPI3MR_PORTENABLE_TIMEOUT 300
124 #define MPI3MR_PORTENABLE_POLL_INTERVAL 5
125 #define MPI3MR_ABORTTM_TIMEOUT 60
126 #define MPI3MR_RESETTM_TIMEOUT 60
127 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
128 #define MPI3MR_TSUPDATE_INTERVAL 900
129 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
130 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
131 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180
132 #define MPI3MR_RESET_ACK_TIMEOUT 30
133 #define MPI3MR_MUR_TIMEOUT 120
134 #define MPI3MR_RESET_TIMEOUT 510
135
136 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */
137
138 #define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10
139
140 #define MPI3MR_SCMD_TIMEOUT (60 * HZ)
141 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ)
142
143 /* Internal admin command state definitions*/
144 #define MPI3MR_CMD_NOTUSED 0x8000
145 #define MPI3MR_CMD_COMPLETE 0x0001
146 #define MPI3MR_CMD_PENDING 0x0002
147 #define MPI3MR_CMD_REPLY_VALID 0x0004
148 #define MPI3MR_CMD_RESET 0x0008
149
150 /* Definitions for Event replies and sense buffer allocated per controller */
151 #define MPI3MR_NUM_EVT_REPLIES 64
152 #define MPI3MR_SENSE_BUF_SZ 256
153 #define MPI3MR_SENSEBUF_FACTOR 3
154 #define MPI3MR_CHAINBUF_FACTOR 3
155 #define MPI3MR_CHAINBUFDIX_FACTOR 2
156
157 /* Invalid target device handle */
158 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
159
160 /* Controller Reset related definitions */
161 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
162 #define MPI3MR_MAX_RESET_RETRY_COUNT 3
163
164 /* ResponseCode definitions */
165 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
166 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \
167 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
168
169 #define MPI3MR_DEFAULT_MDTS (128 * 1024)
170 #define MPI3MR_DEFAULT_PGSZEXP (12)
171
172 /* Command retry count definitions */
173 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3
174 #define MPI3MR_PEL_RETRY_COUNT 3
175
176 /* Default target device queue depth */
177 #define MPI3MR_DEFAULT_SDEV_QD 32
178
179 /* Definitions for Threaded IRQ poll*/
180 #define MPI3MR_IRQ_POLL_SLEEP 20
181 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8
182
183 /* Definitions for the controller security status*/
184 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
185 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
186
187 #define MPI3MR_INVALID_DEVICE 0x00
188 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04
189 #define MPI3MR_HARD_SECURE_DEVICE 0x08
190 #define MPI3MR_TAMPERED_DEVICE 0x0C
191
192 #define MPI3MR_DEFAULT_HDB_MAX_SZ (4 * 1024 * 1024)
193 #define MPI3MR_DEFAULT_HDB_DEC_SZ (1 * 1024 * 1024)
194 #define MPI3MR_DEFAULT_HDB_MIN_SZ (2 * 1024 * 1024)
195 #define MPI3MR_MAX_NUM_HDB 2
196
197 #define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0
198 #define MPI3MR_HDB_TRIGGER_TYPE_FAULT 1
199 #define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2
200 #define MPI3MR_HDB_TRIGGER_TYPE_GLOBAL 3
201 #define MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET 4
202 #define MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED 5
203
204 #define MPI3MR_HDB_REFRESH_TYPE_RESERVED 0
205 #define MPI3MR_HDB_REFRESH_TYPE_CURRENT 1
206 #define MPI3MR_HDB_REFRESH_TYPE_DEFAULT 2
207 #define MPI3MR_HDB_HDB_REFRESH_TYPE_PERSISTENT 3
208
209 #define MPI3MR_DEFAULT_HDB_SZ (4 * 1024 * 1024)
210 #define MPI3MR_MAX_NUM_HDB 2
211
212 #define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_INDEX 0
213 #define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_DATA 1
214
215 #define MPI3MR_THRESHOLD_REPLY_COUNT 100
216
217 /* SGE Flag definition */
218 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
219 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
220 MPI3_SGE_FLAGS_END_OF_LIST)
221
222 /* MSI Index from Reply Queue Index */
223 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset)
224
225 /*
226 * Maximum data transfer size definitions for management
227 * application commands
228 */
229 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024)
230 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512
231 /*
232 * 2048 sectors are for data buffers and additional 512 sectors for
233 * other buffers
234 */
235 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512)
236
237 #define MPI3MR_WRITE_SAME_MAX_LEN_256_BLKS 256
238 #define MPI3MR_WRITE_SAME_MAX_LEN_2048_BLKS 2048
239
240 #define MPI3MR_DRIVER_EVENT_PROCESS_TRIGGER (0xFFFD)
241
242 /**
243 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe
244 * Encapsulated commands.
245 *
246 * @base_addr: Physical address
247 * @length: SGE length
248 * @rsvd: Reserved
249 * @rsvd1: Reserved
250 * @sub_type: sgl sub type
251 * @type: sgl type
252 */
253 struct mpi3mr_nvme_pt_sge {
254 __le64 base_addr;
255 __le32 length;
256 u16 rsvd;
257 u8 rsvd1;
258 u8 sub_type:4;
259 u8 type:4;
260 };
261
262 /**
263 * struct mpi3mr_buf_map - local structure to
264 * track kernel and user buffers associated with an BSG
265 * structure.
266 *
267 * @bsg_buf: BSG buffer virtual address
268 * @bsg_buf_len: BSG buffer length
269 * @kern_buf: Kernel buffer virtual address
270 * @kern_buf_len: Kernel buffer length
271 * @kern_buf_dma: Kernel buffer DMA address
272 * @data_dir: Data direction.
273 */
274 struct mpi3mr_buf_map {
275 void *bsg_buf;
276 u32 bsg_buf_len;
277 void *kern_buf;
278 u32 kern_buf_len;
279 dma_addr_t kern_buf_dma;
280 u8 data_dir;
281 u16 num_dma_desc;
282 struct dma_memory_desc *dma_desc;
283 };
284
285 /* IOC State definitions */
286 enum mpi3mr_iocstate {
287 MRIOC_STATE_READY = 1,
288 MRIOC_STATE_RESET,
289 MRIOC_STATE_FAULT,
290 MRIOC_STATE_BECOMING_READY,
291 MRIOC_STATE_RESET_REQUESTED,
292 MRIOC_STATE_UNRECOVERABLE,
293 };
294
295 /* Reset reason code definitions*/
296 enum mpi3mr_reset_reason {
297 MPI3MR_RESET_FROM_BRINGUP = 1,
298 MPI3MR_RESET_FROM_FAULT_WATCH = 2,
299 MPI3MR_RESET_FROM_APP = 3,
300 MPI3MR_RESET_FROM_EH_HOS = 4,
301 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
302 MPI3MR_RESET_FROM_APP_TIMEOUT = 6,
303 MPI3MR_RESET_FROM_MUR_FAILURE = 7,
304 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
305 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
306 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
307 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
308 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
309 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
310 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
311 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
312 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
313 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
314 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
315 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
316 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
317 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
318 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
319 MPI3MR_RESET_FROM_SYSFS = 23,
320 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
321 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25,
322 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT = 26,
323 MPI3MR_RESET_FROM_FIRMWARE = 27,
324 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29,
325 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30,
326 MPI3MR_RESET_FROM_TRIGGER = 31,
327 };
328
329 #define MPI3MR_RESET_REASON_OSTYPE_LINUX 1
330 #define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28
331 #define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20
332
333
334 /* Queue type definitions */
335 enum queue_type {
336 MPI3MR_DEFAULT_QUEUE = 0,
337 MPI3MR_POLL_QUEUE,
338 };
339
340 /**
341 * struct mpi3mr_compimg_ver - replica of component image
342 * version defined in mpi30_image.h in host endianness
343 *
344 */
345 struct mpi3mr_compimg_ver {
346 u16 build_num;
347 u16 cust_id;
348 u8 ph_minor;
349 u8 ph_major;
350 u8 gen_minor;
351 u8 gen_major;
352 };
353
354 /**
355 * struct mpi3mr_ioc_facs - replica of component image version
356 * defined in mpi30_ioc.h in host endianness
357 *
358 */
359 struct mpi3mr_ioc_facts {
360 u32 ioc_capabilities;
361 struct mpi3mr_compimg_ver fw_ver;
362 u32 mpi_version;
363 u32 diag_trace_sz;
364 u32 diag_fw_sz;
365 u32 diag_drvr_sz;
366 u16 max_reqs;
367 u16 product_id;
368 u16 op_req_sz;
369 u16 reply_sz;
370 u16 exceptions;
371 u16 max_perids;
372 u16 max_pds;
373 u16 max_sasexpanders;
374 u32 max_data_length;
375 u16 max_sasinitiators;
376 u16 max_enclosures;
377 u16 max_pcie_switches;
378 u16 max_nvme;
379 u16 max_vds;
380 u16 max_hpds;
381 u16 max_advhpds;
382 u16 max_raid_pds;
383 u16 min_devhandle;
384 u16 max_devhandle;
385 u16 max_op_req_q;
386 u16 max_op_reply_q;
387 u16 shutdown_timeout;
388 u8 ioc_num;
389 u8 who_init;
390 u16 max_msix_vectors;
391 u8 personality;
392 u8 dma_mask;
393 bool max_req_limit;
394 u8 protocol_flags;
395 u8 sge_mod_mask;
396 u8 sge_mod_value;
397 u8 sge_mod_shift;
398 u8 max_dev_per_tg;
399 u16 max_io_throttle_group;
400 u16 io_throttle_data_length;
401 u16 io_throttle_low;
402 u16 io_throttle_high;
403
404 };
405
406 /**
407 * struct segments - memory descriptor structure to store
408 * virtual and dma addresses for operational queue segments.
409 *
410 * @segment: virtual address
411 * @segment_dma: dma address
412 */
413 struct segments {
414 void *segment;
415 dma_addr_t segment_dma;
416 };
417
418 /**
419 * struct op_req_qinfo - Operational Request Queue Information
420 *
421 * @ci: consumer index
422 * @pi: producer index
423 * @num_request: Maximum number of entries in the queue
424 * @qid: Queue Id starting from 1
425 * @reply_qid: Associated reply queue Id
426 * @num_segments: Number of discontiguous memory segments
427 * @segment_qd: Depth of each segments
428 * @q_lock: Concurrent queue access lock
429 * @q_segments: Segment descriptor pointer
430 * @q_segment_list: Segment list base virtual address
431 * @q_segment_list_dma: Segment list base DMA address
432 */
433 struct op_req_qinfo {
434 u16 ci;
435 u16 pi;
436 u16 num_requests;
437 u16 qid;
438 u16 reply_qid;
439 u16 num_segments;
440 u16 segment_qd;
441 spinlock_t q_lock;
442 struct segments *q_segments;
443 void *q_segment_list;
444 dma_addr_t q_segment_list_dma;
445 };
446
447 /**
448 * struct op_reply_qinfo - Operational Reply Queue Information
449 *
450 * @ci: consumer index
451 * @qid: Queue Id starting from 1
452 * @num_replies: Maximum number of entries in the queue
453 * @num_segments: Number of discontiguous memory segments
454 * @segment_qd: Depth of each segments
455 * @q_segments: Segment descriptor pointer
456 * @q_segment_list: Segment list base virtual address
457 * @q_segment_list_dma: Segment list base DMA address
458 * @ephase: Expected phased identifier for the reply queue
459 * @pend_ios: Number of IOs pending in HW for this queue
460 * @enable_irq_poll: Flag to indicate polling is enabled
461 * @in_use: Queue is handled by poll/ISR
462 * @qtype: Type of queue (types defined in enum queue_type)
463 * @qfull_watermark: Watermark defined in reply queue to avoid
464 * reply queue full
465 */
466 struct op_reply_qinfo {
467 u16 ci;
468 u16 qid;
469 u16 num_replies;
470 u16 num_segments;
471 u16 segment_qd;
472 struct segments *q_segments;
473 void *q_segment_list;
474 dma_addr_t q_segment_list_dma;
475 u8 ephase;
476 atomic_t pend_ios;
477 bool enable_irq_poll;
478 atomic_t in_use;
479 enum queue_type qtype;
480 u16 qfull_watermark;
481 };
482
483 /**
484 * struct mpi3mr_intr_info - Interrupt cookie information
485 *
486 * @mrioc: Adapter instance reference
487 * @os_irq: irq number
488 * @msix_index: MSIx index
489 * @op_reply_q: Associated operational reply queue
490 * @name: Dev name for the irq claiming device
491 */
492 struct mpi3mr_intr_info {
493 struct mpi3mr_ioc *mrioc;
494 int os_irq;
495 u16 msix_index;
496 struct op_reply_qinfo *op_reply_q;
497 char name[MPI3MR_NAME_LENGTH];
498 };
499
500 /**
501 * struct mpi3mr_throttle_group_info - Throttle group info
502 *
503 * @io_divert: Flag indicates io divert is on or off for the TG
504 * @need_qd_reduction: Flag to indicate QD reduction is needed
505 * @qd_reduction: Queue Depth reduction in units of 10%
506 * @fw_qd: QueueDepth value reported by the firmware
507 * @modified_qd: Modified QueueDepth value due to throttling
508 * @id: Throttle Group ID.
509 * @high: High limit to turn on throttling in 512 byte blocks
510 * @low: Low limit to turn off throttling in 512 byte blocks
511 * @pend_large_data_sz: Counter to track pending large data
512 */
513 struct mpi3mr_throttle_group_info {
514 u8 io_divert;
515 u8 need_qd_reduction;
516 u8 qd_reduction;
517 u16 fw_qd;
518 u16 modified_qd;
519 u16 id;
520 u32 high;
521 u32 low;
522 atomic_t pend_large_data_sz;
523 };
524
525 /* HBA port flags */
526 #define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01
527 #define MPI3MR_HBA_PORT_FLAG_NEW 0x02
528
529 /* IOCTL data transfer sge*/
530 #define MPI3MR_NUM_IOCTL_SGE 256
531 #define MPI3MR_IOCTL_SGE_SIZE (8 * 1024)
532
533 /**
534 * struct mpi3mr_hba_port - HBA's port information
535 * @port_id: Port number
536 * @flags: HBA port flags
537 */
538 struct mpi3mr_hba_port {
539 struct list_head list;
540 u8 port_id;
541 u8 flags;
542 };
543
544 /**
545 * struct mpi3mr_sas_port - Internal SAS port information
546 * @port_list: List of ports belonging to a SAS node
547 * @num_phys: Number of phys associated with port
548 * @marked_responding: used while refresing the sas ports
549 * @lowest_phy: lowest phy ID of current sas port, valid for controller port
550 * @phy_mask: phy_mask of current sas port, valid for controller port
551 * @hba_port: HBA port entry
552 * @remote_identify: Attached device identification
553 * @rphy: SAS transport layer rphy object
554 * @port: SAS transport layer port object
555 * @phy_list: mpi3mr_sas_phy objects belonging to this port
556 */
557 struct mpi3mr_sas_port {
558 struct list_head port_list;
559 u8 num_phys;
560 u8 marked_responding;
561 int lowest_phy;
562 u64 phy_mask;
563 struct mpi3mr_hba_port *hba_port;
564 struct sas_identify remote_identify;
565 struct sas_rphy *rphy;
566 struct sas_port *port;
567 struct list_head phy_list;
568 };
569
570 /**
571 * struct mpi3mr_sas_phy - Internal SAS Phy information
572 * @port_siblings: List of phys belonging to a port
573 * @identify: Phy identification
574 * @remote_identify: Attached device identification
575 * @phy: SAS transport layer Phy object
576 * @phy_id: Unique phy id within a port
577 * @handle: Firmware device handle for this phy
578 * @attached_handle: Firmware device handle for attached device
579 * @phy_belongs_to_port: Flag to indicate phy belongs to port
580 @hba_port: HBA port entry
581 */
582 struct mpi3mr_sas_phy {
583 struct list_head port_siblings;
584 struct sas_identify identify;
585 struct sas_identify remote_identify;
586 struct sas_phy *phy;
587 u8 phy_id;
588 u16 handle;
589 u16 attached_handle;
590 u8 phy_belongs_to_port;
591 struct mpi3mr_hba_port *hba_port;
592 };
593
594 /**
595 * struct mpi3mr_sas_node - SAS host/expander information
596 * @list: List of sas nodes in a controller
597 * @parent_dev: Parent device class
598 * @num_phys: Number phys belonging to sas_node
599 * @sas_address: SAS address of sas_node
600 * @handle: Firmware device handle for this sas_host/expander
601 * @sas_address_parent: SAS address of parent expander or host
602 * @enclosure_handle: Firmware handle of enclosure of this node
603 * @device_info: Capabilities of this sas_host/expander
604 * @non_responding: used to refresh the expander devices during reset
605 * @host_node: Flag to indicate this is a host_node
606 * @hba_port: HBA port entry
607 * @phy: A list of phys that make up this sas_host/expander
608 * @sas_port_list: List of internal ports of this node
609 * @rphy: sas_rphy object of this expander node
610 */
611 struct mpi3mr_sas_node {
612 struct list_head list;
613 struct device *parent_dev;
614 u8 num_phys;
615 u64 sas_address;
616 u16 handle;
617 u64 sas_address_parent;
618 u16 enclosure_handle;
619 u64 enclosure_logical_id;
620 u8 non_responding;
621 u8 host_node;
622 struct mpi3mr_hba_port *hba_port;
623 struct mpi3mr_sas_phy *phy;
624 struct list_head sas_port_list;
625 struct sas_rphy *rphy;
626 };
627
628 /**
629 * struct mpi3mr_enclosure_node - enclosure information
630 * @list: List of enclosures
631 * @pg0: Enclosure page 0;
632 */
633 struct mpi3mr_enclosure_node {
634 struct list_head list;
635 struct mpi3_enclosure_page0 pg0;
636 };
637
638 /**
639 * struct tgt_dev_sas_sata - SAS/SATA device specific
640 * information cached from firmware given data
641 *
642 * @sas_address: World wide unique SAS address
643 * @sas_address_parent: Sas address of parent expander or host
644 * @dev_info: Device information bits
645 * @phy_id: Phy identifier provided in device page 0
646 * @attached_phy_id: Attached phy identifier provided in device page 0
647 * @sas_transport_attached: Is this device exposed to transport
648 * @pend_sas_rphy_add: Flag to check device is in process of add
649 * @hba_port: HBA port entry
650 * @rphy: SAS transport layer rphy object
651 */
652 struct tgt_dev_sas_sata {
653 u64 sas_address;
654 u64 sas_address_parent;
655 u16 dev_info;
656 u8 phy_id;
657 u8 attached_phy_id;
658 u8 sas_transport_attached;
659 u8 pend_sas_rphy_add;
660 struct mpi3mr_hba_port *hba_port;
661 struct sas_rphy *rphy;
662 };
663
664 /**
665 * struct tgt_dev_pcie - PCIe device specific information cached
666 * from firmware given data
667 *
668 * @mdts: Maximum data transfer size
669 * @capb: Device capabilities
670 * @pgsz: Device page size
671 * @abort_to: Timeout for abort TM
672 * @reset_to: Timeout for Target/LUN reset TM
673 * @dev_info: Device information bits
674 */
675 struct tgt_dev_pcie {
676 u32 mdts;
677 u16 capb;
678 u8 pgsz;
679 u8 abort_to;
680 u8 reset_to;
681 u16 dev_info;
682 };
683
684 /**
685 * struct tgt_dev_vd - virtual device specific information
686 * cached from firmware given data
687 *
688 * @state: State of the VD
689 * @tg_qd_reduction: Queue Depth reduction in units of 10%
690 * @tg_id: VDs throttle group ID
691 * @high: High limit to turn on throttling in 512 byte blocks
692 * @low: Low limit to turn off throttling in 512 byte blocks
693 * @tg: Pointer to throttle group info
694 */
695 struct tgt_dev_vd {
696 u8 state;
697 u8 tg_qd_reduction;
698 u16 tg_id;
699 u32 tg_high;
700 u32 tg_low;
701 struct mpi3mr_throttle_group_info *tg;
702 };
703
704
705 /**
706 * union _form_spec_inf - union of device specific information
707 */
708 union _form_spec_inf {
709 struct tgt_dev_sas_sata sas_sata_inf;
710 struct tgt_dev_pcie pcie_inf;
711 struct tgt_dev_vd vd_inf;
712 };
713
714 enum mpi3mr_dev_state {
715 MPI3MR_DEV_CREATED = 1,
716 MPI3MR_DEV_REMOVE_HS_STARTED = 2,
717 MPI3MR_DEV_DELETED = 3,
718 };
719
720 /**
721 * struct mpi3mr_tgt_dev - target device data structure
722 *
723 * @list: List pointer
724 * @starget: Scsi_target pointer
725 * @dev_handle: FW device handle
726 * @parent_handle: FW parent device handle
727 * @slot: Slot number
728 * @encl_handle: FW enclosure handle
729 * @perst_id: FW assigned Persistent ID
730 * @devpg0_flag: Device Page0 flag
731 * @dev_type: SAS/SATA/PCIE device type
732 * @is_hidden: Should be exposed to upper layers or not
733 * @host_exposed: Already exposed to host or not
734 * @io_unit_port: IO Unit port ID
735 * @non_stl: Is this device not to be attached with SAS TL
736 * @io_throttle_enabled: I/O throttling needed or not
737 * @wslen: Write same max length
738 * @q_depth: Device specific Queue Depth
739 * @wwid: World wide ID
740 * @enclosure_logical_id: Enclosure logical identifier
741 * @dev_spec: Device type specific information
742 * @ref_count: Reference count
743 * @state: device state
744 */
745 struct mpi3mr_tgt_dev {
746 struct list_head list;
747 struct scsi_target *starget;
748 u16 dev_handle;
749 u16 parent_handle;
750 u16 slot;
751 u16 encl_handle;
752 u16 perst_id;
753 u16 devpg0_flag;
754 u8 dev_type;
755 u8 is_hidden;
756 u8 host_exposed;
757 u8 io_unit_port;
758 u8 non_stl;
759 u8 io_throttle_enabled;
760 u16 wslen;
761 u16 q_depth;
762 u64 wwid;
763 u64 enclosure_logical_id;
764 union _form_spec_inf dev_spec;
765 struct kref ref_count;
766 enum mpi3mr_dev_state state;
767 };
768
769 /**
770 * mpi3mr_tgtdev_get - k reference incrementor
771 * @s: Target device reference
772 *
773 * Increment target device reference count.
774 */
mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev * s)775 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
776 {
777 kref_get(&s->ref_count);
778 }
779
780 /**
781 * mpi3mr_free_tgtdev - target device memory dealloctor
782 * @r: k reference pointer of the target device
783 *
784 * Free target device memory when no reference.
785 */
mpi3mr_free_tgtdev(struct kref * r)786 static inline void mpi3mr_free_tgtdev(struct kref *r)
787 {
788 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
789 }
790
791 /**
792 * mpi3mr_tgtdev_put - k reference decrementor
793 * @s: Target device reference
794 *
795 * Decrement target device reference count.
796 */
mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev * s)797 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
798 {
799 kref_put(&s->ref_count, mpi3mr_free_tgtdev);
800 }
801
802
803 /**
804 * struct mpi3mr_stgt_priv_data - SCSI target private structure
805 *
806 * @starget: Scsi_target pointer
807 * @dev_handle: FW device handle
808 * @perst_id: FW assigned Persistent ID
809 * @num_luns: Number of Logical Units
810 * @block_io: I/O blocked to the device or not
811 * @dev_removed: Device removed in the Firmware
812 * @dev_removedelay: Device is waiting to be removed in FW
813 * @dev_type: Device type
814 * @dev_nvme_dif: Device is NVMe DIF enabled
815 * @wslen: Write same max length
816 * @io_throttle_enabled: I/O throttling needed or not
817 * @io_divert: Flag indicates io divert is on or off for the dev
818 * @throttle_group: Pointer to throttle group info
819 * @tgt_dev: Internal target device pointer
820 * @pend_count: Counter to track pending I/Os during error
821 * handling
822 */
823 struct mpi3mr_stgt_priv_data {
824 struct scsi_target *starget;
825 u16 dev_handle;
826 u16 perst_id;
827 u32 num_luns;
828 atomic_t block_io;
829 u8 dev_removed;
830 u8 dev_removedelay;
831 u8 dev_type;
832 u8 dev_nvme_dif;
833 u16 wslen;
834 u8 io_throttle_enabled;
835 u8 io_divert;
836 struct mpi3mr_throttle_group_info *throttle_group;
837 struct mpi3mr_tgt_dev *tgt_dev;
838 u32 pend_count;
839 };
840
841 /**
842 * struct mpi3mr_stgt_priv_data - SCSI device private structure
843 *
844 * @tgt_priv_data: Scsi_target private data pointer
845 * @lun_id: LUN ID of the device
846 * @ncq_prio_enable: NCQ priority enable for SATA device
847 * @pend_count: Counter to track pending I/Os during error
848 * handling
849 * @wslen: Write same max length
850 */
851 struct mpi3mr_sdev_priv_data {
852 struct mpi3mr_stgt_priv_data *tgt_priv_data;
853 u32 lun_id;
854 u8 ncq_prio_enable;
855 u32 pend_count;
856 u16 wslen;
857 };
858
859 /**
860 * struct mpi3mr_drv_cmd - Internal command tracker
861 *
862 * @mutex: Command mutex
863 * @done: Completeor for wakeup
864 * @reply: Firmware reply for internal commands
865 * @sensebuf: Sensebuf for SCSI IO commands
866 * @iou_rc: IO Unit control reason code
867 * @state: Command State
868 * @dev_handle: Firmware handle for device specific commands
869 * @ioc_status: IOC status from the firmware
870 * @ioc_loginfo:IOC log info from the firmware
871 * @is_waiting: Is the command issued in block mode
872 * @is_sense: Is Sense data present
873 * @retry_count: Retry count for retriable commands
874 * @host_tag: Host tag used by the command
875 * @callback: Callback for non blocking commands
876 */
877 struct mpi3mr_drv_cmd {
878 struct mutex mutex;
879 struct completion done;
880 void *reply;
881 u8 *sensebuf;
882 u8 iou_rc;
883 u16 state;
884 u16 dev_handle;
885 u16 ioc_status;
886 u32 ioc_loginfo;
887 u8 is_waiting;
888 u8 is_sense;
889 u8 retry_count;
890 u16 host_tag;
891
892 void (*callback)(struct mpi3mr_ioc *mrioc,
893 struct mpi3mr_drv_cmd *drv_cmd);
894 };
895
896 /**
897 * union mpi3mr_trigger_data - Trigger data information
898 * @fault: Fault code
899 * @global: Global trigger data
900 * @element: element trigger data
901 */
902 union mpi3mr_trigger_data {
903 u16 fault;
904 u64 global;
905 union mpi3_driver2_trigger_element element;
906 };
907
908 /**
909 * struct trigger_event_data - store trigger related
910 * information.
911 *
912 * @trace_hdb: Trace diag buffer descriptor reference
913 * @fw_hdb: FW diag buffer descriptor reference
914 * @trigger_type: Trigger type
915 * @trigger_specific_data: Trigger specific data
916 * @snapdump: Snapdump enable or disable flag
917 */
918 struct trigger_event_data {
919 struct diag_buffer_desc *trace_hdb;
920 struct diag_buffer_desc *fw_hdb;
921 u8 trigger_type;
922 union mpi3mr_trigger_data trigger_specific_data;
923 bool snapdump;
924 };
925
926 /**
927 * struct diag_buffer_desc - memory descriptor structure to
928 * store virtual, dma addresses, size, buffer status for host
929 * diagnostic buffers.
930 *
931 * @type: Buffer type
932 * @trigger_data: Trigger data
933 * @trigger_type: Trigger type
934 * @status: Buffer status
935 * @size: Buffer size
936 * @addr: Virtual address
937 * @dma_addr: Buffer DMA address
938 */
939 struct diag_buffer_desc {
940 u8 type;
941 union mpi3mr_trigger_data trigger_data;
942 u8 trigger_type;
943 u8 status;
944 u32 size;
945 void *addr;
946 dma_addr_t dma_addr;
947 };
948
949 /**
950 * struct dma_memory_desc - memory descriptor structure to store
951 * virtual address, dma address and size for any generic dma
952 * memory allocations in the driver.
953 *
954 * @size: buffer size
955 * @addr: virtual address
956 * @dma_addr: dma address
957 */
958 struct dma_memory_desc {
959 u32 size;
960 void *addr;
961 dma_addr_t dma_addr;
962 };
963
964
965 /**
966 * struct chain_element - memory descriptor structure to store
967 * virtual and dma addresses for chain elements.
968 *
969 * @addr: virtual address
970 * @dma_addr: dma address
971 */
972 struct chain_element {
973 void *addr;
974 dma_addr_t dma_addr;
975 };
976
977 /**
978 * struct scmd_priv - SCSI command private data
979 *
980 * @host_tag: Host tag specific to operational queue
981 * @in_lld_scope: Command in LLD scope or not
982 * @meta_sg_valid: DIX command with meta data SGL or not
983 * @scmd: SCSI Command pointer
984 * @req_q_idx: Operational request queue index
985 * @chain_idx: Chain frame index
986 * @meta_chain_idx: Chain frame index of meta data SGL
987 * @mpi3mr_scsiio_req: MPI SCSI IO request
988 */
989 struct scmd_priv {
990 u16 host_tag;
991 u8 in_lld_scope;
992 u8 meta_sg_valid;
993 struct scsi_cmnd *scmd;
994 u16 req_q_idx;
995 int chain_idx;
996 int meta_chain_idx;
997 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
998 };
999
1000 /**
1001 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
1002 * private data
1003 *
1004 * @list: List pointer
1005 * @pdev: PCI device pointer
1006 * @shost: Scsi_Host pointer
1007 * @id: Controller ID
1008 * @cpu_count: Number of online CPUs
1009 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
1010 * @name: Controller ASCII name
1011 * @driver_name: Driver ASCII name
1012 * @sysif_regs: System interface registers virtual address
1013 * @sysif_regs_phys: System interface registers physical address
1014 * @bars: PCI BARS
1015 * @dma_mask: DMA mask
1016 * @msix_count: Number of MSIX vectors used
1017 * @intr_enabled: Is interrupts enabled
1018 * @num_admin_req: Number of admin requests
1019 * @admin_req_q_sz: Admin request queue size
1020 * @admin_req_pi: Admin request queue producer index
1021 * @admin_req_ci: Admin request queue consumer index
1022 * @admin_req_base: Admin request queue base virtual address
1023 * @admin_req_dma: Admin request queue base dma address
1024 * @admin_req_lock: Admin queue access lock
1025 * @num_admin_replies: Number of admin replies
1026 * @admin_reply_q_sz: Admin reply queue size
1027 * @admin_reply_ci: Admin reply queue consumer index
1028 * @admin_reply_ephase:Admin reply queue expected phase
1029 * @admin_reply_base: Admin reply queue base virtual address
1030 * @admin_reply_dma: Admin reply queue base dma address
1031 * @admin_reply_q_in_use: Queue is handled by poll/ISR
1032 * @ready_timeout: Controller ready timeout
1033 * @intr_info: Interrupt cookie pointer
1034 * @intr_info_count: Number of interrupt cookies
1035 * @is_intr_info_set: Flag to indicate intr info is setup
1036 * @num_queues: Number of operational queues
1037 * @num_op_req_q: Number of operational request queues
1038 * @req_qinfo: Operational request queue info pointer
1039 * @num_op_reply_q: Number of operational reply queues
1040 * @op_reply_qinfo: Operational reply queue info pointer
1041 * @init_cmds: Command tracker for initialization commands
1042 * @cfg_cmds: Command tracker for configuration requests
1043 * @facts: Cached IOC facts data
1044 * @op_reply_desc_sz: Operational reply descriptor size
1045 * @num_reply_bufs: Number of reply buffers allocated
1046 * @reply_buf_pool: Reply buffer pool
1047 * @reply_buf: Reply buffer base virtual address
1048 * @reply_buf_dma: Reply buffer DMA address
1049 * @reply_buf_dma_max_address: Reply DMA address max limit
1050 * @reply_free_qsz: Reply free queue size
1051 * @reply_free_q_pool: Reply free queue pool
1052 * @reply_free_q: Reply free queue base virtual address
1053 * @reply_free_q_dma: Reply free queue base DMA address
1054 * @reply_free_queue_lock: Reply free queue lock
1055 * @reply_free_queue_host_index: Reply free queue host index
1056 * @num_sense_bufs: Number of sense buffers
1057 * @sense_buf_pool: Sense buffer pool
1058 * @sense_buf: Sense buffer base virtual address
1059 * @sense_buf_dma: Sense buffer base DMA address
1060 * @sense_buf_q_sz: Sense buffer queue size
1061 * @sense_buf_q_pool: Sense buffer queue pool
1062 * @sense_buf_q: Sense buffer queue virtual address
1063 * @sense_buf_q_dma: Sense buffer queue DMA address
1064 * @sbq_lock: Sense buffer queue lock
1065 * @sbq_host_index: Sense buffer queuehost index
1066 * @event_masks: Event mask bitmap
1067 * @fwevt_worker_thread: Firmware event worker thread
1068 * @fwevt_lock: Firmware event lock
1069 * @fwevt_list: Firmware event list
1070 * @watchdog_work_q_name: Fault watchdog worker thread name
1071 * @watchdog_work_q: Fault watchdog worker thread
1072 * @watchdog_work: Fault watchdog work
1073 * @watchdog_lock: Fault watchdog lock
1074 * @is_driver_loading: Is driver still loading
1075 * @scan_started: Async scan started
1076 * @scan_failed: Asycn scan failed
1077 * @stop_drv_processing: Stop all command processing
1078 * @device_refresh_on: Don't process the events until devices are refreshed
1079 * @max_host_ios: Maximum host I/O count
1080 * @max_sgl_entries: Max SGL entries per I/O
1081 * @chain_buf_count: Chain buffer count
1082 * @chain_buf_pool: Chain buffer pool
1083 * @chain_sgl_list: Chain SGL list
1084 * @chain_bitmap: Chain buffer allocator bitmap
1085 * @chain_buf_lock: Chain buffer list lock
1086 * @bsg_cmds: Command tracker for BSG command
1087 * @host_tm_cmds: Command tracker for task management commands
1088 * @dev_rmhs_cmds: Command tracker for device removal commands
1089 * @evtack_cmds: Command tracker for event ack commands
1090 * @devrem_bitmap: Device removal bitmap
1091 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap
1092 * @removepend_bitmap: Remove pending bitmap
1093 * @delayed_rmhs_list: Delayed device removal list
1094 * @evtack_cmds_bitmap: Event Ack bitmap
1095 * @delayed_evtack_cmds_list: Delayed event acknowledgment list
1096 * @ts_update_counter: Timestamp update counter
1097 * @ts_update_interval: Timestamp update interval
1098 * @reset_in_progress: Reset in progress flag
1099 * @unrecoverable: Controller unrecoverable flag
1100 * @io_admin_reset_sync: Manage state of I/O ops during an admin reset process
1101 * @prev_reset_result: Result of previous reset
1102 * @reset_mutex: Controller reset mutex
1103 * @reset_waitq: Controller reset wait queue
1104 * @prepare_for_reset: Prepare for reset event received
1105 * @prepare_for_reset_timeout_counter: Prepare for reset timeout
1106 * @prp_list_virt: NVMe encapsulated PRP list virtual base
1107 * @prp_list_dma: NVMe encapsulated PRP list DMA
1108 * @prp_sz: NVME encapsulated PRP list size
1109 * @diagsave_timeout: Diagnostic information save timeout
1110 * @logging_level: Controller debug logging level
1111 * @flush_io_count: I/O count to flush after reset
1112 * @current_event: Firmware event currently in process
1113 * @driver_info: Driver, Kernel, OS information to firmware
1114 * @change_count: Topology change count
1115 * @pel_enabled: Persistent Event Log(PEL) enabled or not
1116 * @pel_abort_requested: PEL abort is requested or not
1117 * @pel_class: PEL Class identifier
1118 * @pel_locale: PEL Locale identifier
1119 * @pel_cmds: Command tracker for PEL wait command
1120 * @pel_abort_cmd: Command tracker for PEL abort command
1121 * @pel_newest_seqnum: Newest PEL sequenece number
1122 * @pel_seqnum_virt: PEL sequence number virtual address
1123 * @pel_seqnum_dma: PEL sequence number DMA address
1124 * @pel_seqnum_sz: PEL sequenece number size
1125 * @op_reply_q_offset: Operational reply queue offset with MSIx
1126 * @default_qcount: Total Default queues
1127 * @active_poll_qcount: Currently active poll queue count
1128 * @requested_poll_qcount: User requested poll queue count
1129 * @bsg_dev: BSG device structure
1130 * @bsg_queue: Request queue for BSG device
1131 * @stop_bsgs: Stop BSG request flag
1132 * @logdata_buf: Circular buffer to store log data entries
1133 * @logdata_buf_idx: Index of entry in buffer to store
1134 * @logdata_entry_sz: log data entry size
1135 * @adm_req_q_bar_writeq_lock: Admin request queue lock
1136 * @adm_reply_q_bar_writeq_lock: Admin reply queue lock
1137 * @pend_large_data_sz: Counter to track pending large data
1138 * @io_throttle_data_length: I/O size to track in 512b blocks
1139 * @io_throttle_high: I/O size to start throttle in 512b blocks
1140 * @io_throttle_low: I/O size to stop throttle in 512b blocks
1141 * @num_io_throttle_group: Maximum number of throttle groups
1142 * @throttle_groups: Pointer to throttle group info structures
1143 * @sas_transport_enabled: SAS transport enabled or not
1144 * @scsi_device_channel: Channel ID for SCSI devices
1145 * @transport_cmds: Command tracker for SAS transport commands
1146 * @sas_hba: SAS node for the controller
1147 * @sas_expander_list: SAS node list of expanders
1148 * @sas_node_lock: Lock to protect SAS node list
1149 * @hba_port_table_list: List of HBA Ports
1150 * @enclosure_list: List of Enclosure objects
1151 * @diag_buffers: Host diagnostic buffers
1152 * @driver_pg2: Driver page 2 pointer
1153 * @reply_trigger_present: Reply trigger present flag
1154 * @event_trigger_present: Event trigger present flag
1155 * @scsisense_trigger_present: Scsi sense trigger present flag
1156 * @ioctl_dma_pool: DMA pool for IOCTL data buffers
1157 * @ioctl_sge: DMA buffer descriptors for IOCTL data
1158 * @ioctl_chain_sge: DMA buffer descriptor for IOCTL chain
1159 * @ioctl_resp_sge: DMA buffer descriptor for Mgmt cmd response
1160 * @ioctl_sges_allocated: Flag for IOCTL SGEs allocated or not
1161 * @trace_release_trigger_active: Trace trigger active flag
1162 * @fw_release_trigger_active: Fw release trigger active flag
1163 * @snapdump_trigger_active: Snapdump trigger active flag
1164 * @pci_err_recovery: PCI error recovery in progress
1165 * @block_on_pci_err: Block IO during PCI error recovery
1166 * @reply_qfull_count: Occurences of reply queue full avoidance kicking-in
1167 * @prevent_reply_qfull: Enable reply queue prevention
1168 */
1169 struct mpi3mr_ioc {
1170 struct list_head list;
1171 struct pci_dev *pdev;
1172 struct Scsi_Host *shost;
1173 u8 id;
1174 int cpu_count;
1175 bool enable_segqueue;
1176 u32 irqpoll_sleep;
1177
1178 char name[MPI3MR_NAME_LENGTH];
1179 char driver_name[MPI3MR_NAME_LENGTH];
1180
1181 struct mpi3_sysif_registers __iomem *sysif_regs;
1182 resource_size_t sysif_regs_phys;
1183 int bars;
1184 u64 dma_mask;
1185
1186 u16 msix_count;
1187 u8 intr_enabled;
1188
1189 u16 num_admin_req;
1190 u32 admin_req_q_sz;
1191 u16 admin_req_pi;
1192 u16 admin_req_ci;
1193 void *admin_req_base;
1194 dma_addr_t admin_req_dma;
1195 spinlock_t admin_req_lock;
1196
1197 u16 num_admin_replies;
1198 u32 admin_reply_q_sz;
1199 u16 admin_reply_ci;
1200 u8 admin_reply_ephase;
1201 void *admin_reply_base;
1202 dma_addr_t admin_reply_dma;
1203 atomic_t admin_reply_q_in_use;
1204
1205 u32 ready_timeout;
1206
1207 struct mpi3mr_intr_info *intr_info;
1208 u16 intr_info_count;
1209 bool is_intr_info_set;
1210
1211 u16 num_queues;
1212 u16 num_op_req_q;
1213 struct op_req_qinfo *req_qinfo;
1214
1215 u16 num_op_reply_q;
1216 struct op_reply_qinfo *op_reply_qinfo;
1217
1218 struct mpi3mr_drv_cmd init_cmds;
1219 struct mpi3mr_drv_cmd cfg_cmds;
1220 struct mpi3mr_ioc_facts facts;
1221 u16 op_reply_desc_sz;
1222
1223 u32 num_reply_bufs;
1224 struct dma_pool *reply_buf_pool;
1225 u8 *reply_buf;
1226 dma_addr_t reply_buf_dma;
1227 dma_addr_t reply_buf_dma_max_address;
1228
1229 u16 reply_free_qsz;
1230 u16 reply_sz;
1231 struct dma_pool *reply_free_q_pool;
1232 __le64 *reply_free_q;
1233 dma_addr_t reply_free_q_dma;
1234 spinlock_t reply_free_queue_lock;
1235 u32 reply_free_queue_host_index;
1236
1237 u32 num_sense_bufs;
1238 struct dma_pool *sense_buf_pool;
1239 u8 *sense_buf;
1240 dma_addr_t sense_buf_dma;
1241
1242 u16 sense_buf_q_sz;
1243 struct dma_pool *sense_buf_q_pool;
1244 __le64 *sense_buf_q;
1245 dma_addr_t sense_buf_q_dma;
1246 spinlock_t sbq_lock;
1247 u32 sbq_host_index;
1248 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
1249
1250 struct workqueue_struct *fwevt_worker_thread;
1251 spinlock_t fwevt_lock;
1252 struct list_head fwevt_list;
1253
1254 char watchdog_work_q_name[50];
1255 struct workqueue_struct *watchdog_work_q;
1256 struct delayed_work watchdog_work;
1257 spinlock_t watchdog_lock;
1258
1259 u8 is_driver_loading;
1260 u8 scan_started;
1261 u16 scan_failed;
1262 u8 stop_drv_processing;
1263 u8 device_refresh_on;
1264
1265 u16 max_host_ios;
1266 spinlock_t tgtdev_lock;
1267 struct list_head tgtdev_list;
1268 u16 max_sgl_entries;
1269
1270 u32 chain_buf_count;
1271 struct dma_pool *chain_buf_pool;
1272 struct chain_element *chain_sgl_list;
1273 unsigned long *chain_bitmap;
1274 spinlock_t chain_buf_lock;
1275
1276 struct mpi3mr_drv_cmd bsg_cmds;
1277 struct mpi3mr_drv_cmd host_tm_cmds;
1278 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
1279 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
1280 unsigned long *devrem_bitmap;
1281 u16 dev_handle_bitmap_bits;
1282 unsigned long *removepend_bitmap;
1283 struct list_head delayed_rmhs_list;
1284 unsigned long *evtack_cmds_bitmap;
1285 struct list_head delayed_evtack_cmds_list;
1286
1287 u16 ts_update_counter;
1288 u16 ts_update_interval;
1289 u8 reset_in_progress;
1290 u8 unrecoverable;
1291 u8 io_admin_reset_sync;
1292 int prev_reset_result;
1293 struct mutex reset_mutex;
1294 wait_queue_head_t reset_waitq;
1295
1296 u8 prepare_for_reset;
1297 u16 prepare_for_reset_timeout_counter;
1298
1299 void *prp_list_virt;
1300 dma_addr_t prp_list_dma;
1301 u32 prp_sz;
1302
1303 u16 diagsave_timeout;
1304 int logging_level;
1305 u16 flush_io_count;
1306
1307 struct mpi3mr_fwevt *current_event;
1308 struct mpi3_driver_info_layout driver_info;
1309 u16 change_count;
1310
1311 u8 pel_enabled;
1312 u8 pel_abort_requested;
1313 u8 pel_class;
1314 u16 pel_locale;
1315 struct mpi3mr_drv_cmd pel_cmds;
1316 struct mpi3mr_drv_cmd pel_abort_cmd;
1317
1318 u32 pel_newest_seqnum;
1319 void *pel_seqnum_virt;
1320 dma_addr_t pel_seqnum_dma;
1321 u32 pel_seqnum_sz;
1322
1323 u16 op_reply_q_offset;
1324 u16 default_qcount;
1325 u16 active_poll_qcount;
1326 u16 requested_poll_qcount;
1327
1328 struct device bsg_dev;
1329 struct request_queue *bsg_queue;
1330 u8 stop_bsgs;
1331 u8 *logdata_buf;
1332 u16 logdata_buf_idx;
1333 u16 logdata_entry_sz;
1334 spinlock_t adm_req_q_bar_writeq_lock;
1335 spinlock_t adm_reply_q_bar_writeq_lock;
1336
1337 atomic_t pend_large_data_sz;
1338 u32 io_throttle_data_length;
1339 u32 io_throttle_high;
1340 u32 io_throttle_low;
1341 u16 num_io_throttle_group;
1342 struct mpi3mr_throttle_group_info *throttle_groups;
1343
1344 u8 sas_transport_enabled;
1345 u8 scsi_device_channel;
1346 struct mpi3mr_drv_cmd transport_cmds;
1347 struct mpi3mr_sas_node sas_hba;
1348 struct list_head sas_expander_list;
1349 spinlock_t sas_node_lock;
1350 struct list_head hba_port_table_list;
1351 struct list_head enclosure_list;
1352
1353 struct dma_pool *ioctl_dma_pool;
1354 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE];
1355 struct dma_memory_desc ioctl_chain_sge;
1356 struct dma_memory_desc ioctl_resp_sge;
1357 bool ioctl_sges_allocated;
1358 bool reply_trigger_present;
1359 bool event_trigger_present;
1360 bool scsisense_trigger_present;
1361 struct diag_buffer_desc diag_buffers[MPI3MR_MAX_NUM_HDB];
1362 struct mpi3_driver_page2 *driver_pg2;
1363 spinlock_t trigger_lock;
1364 bool snapdump_trigger_active;
1365 bool trace_release_trigger_active;
1366 bool fw_release_trigger_active;
1367 bool pci_err_recovery;
1368 bool block_on_pci_err;
1369 atomic_t reply_qfull_count;
1370 bool prevent_reply_qfull;
1371 };
1372
1373 /**
1374 * struct mpi3mr_fwevt - Firmware event structure.
1375 *
1376 * @list: list head
1377 * @work: Work structure
1378 * @mrioc: Adapter instance reference
1379 * @event_id: MPI3 firmware event ID
1380 * @send_ack: Event acknowledgment required or not
1381 * @process_evt: Bottomhalf processing required or not
1382 * @evt_ctx: Event context to send in Ack
1383 * @event_data_size: size of the event data in bytes
1384 * @pending_at_sml: waiting for device add/remove API to complete
1385 * @discard: discard this event
1386 * @ref_count: kref count
1387 * @event_data: Actual MPI3 event data
1388 */
1389 struct mpi3mr_fwevt {
1390 struct list_head list;
1391 struct work_struct work;
1392 struct mpi3mr_ioc *mrioc;
1393 u16 event_id;
1394 bool send_ack;
1395 bool process_evt;
1396 u32 evt_ctx;
1397 u16 event_data_size;
1398 bool pending_at_sml;
1399 bool discard;
1400 struct kref ref_count;
1401 char event_data[] __aligned(4);
1402 };
1403
1404
1405 /**
1406 * struct delayed_dev_rmhs_node - Delayed device removal node
1407 *
1408 * @list: list head
1409 * @handle: Device handle
1410 * @iou_rc: IO Unit Control Reason Code
1411 */
1412 struct delayed_dev_rmhs_node {
1413 struct list_head list;
1414 u16 handle;
1415 u8 iou_rc;
1416 };
1417
1418 /**
1419 * struct delayed_evt_ack_node - Delayed event ack node
1420 * @list: list head
1421 * @event: MPI3 event ID
1422 * @event_ctx: event context
1423 */
1424 struct delayed_evt_ack_node {
1425 struct list_head list;
1426 u8 event;
1427 u32 event_ctx;
1428 };
1429
1430 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
1431 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
1432 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);
1433 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);
1434 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);
1435 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
1436 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1437 u16 admin_req_sz, u8 ignore_reset);
1438 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
1439 struct op_req_qinfo *opreqq, u8 *req);
1440 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
1441 dma_addr_t dma_addr);
1442 void mpi3mr_build_zero_len_sge(void *paddr);
1443 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
1444 dma_addr_t phys_addr);
1445 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
1446 dma_addr_t phys_addr);
1447 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
1448 u64 sense_buf_dma);
1449
1450 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
1451 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);
1452 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
1453 struct mpi3_event_notification_reply *event_reply);
1454 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
1455 struct mpi3_default_reply_descriptor *reply_desc,
1456 u64 *reply_dma, u16 qidx);
1457 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
1458 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
1459
1460 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
1461 u16 reset_reason, u8 snapdump);
1462 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
1463 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
1464
1465 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
1466 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
1467 u32 event_ctx);
1468
1469 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
1470 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
1471 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
1472 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
1473 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
1474 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1475 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
1476 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1477 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
1478 struct op_reply_qinfo *op_reply_q);
1479 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
1480 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc);
1481 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc);
1482 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,
1483 u16 handle, uint lun, u16 htag, ulong timeout,
1484 struct mpi3mr_drv_cmd *drv_cmd,
1485 u8 *resp_code, struct scsi_cmnd *scmd);
1486 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle(
1487 struct mpi3mr_ioc *mrioc, u16 handle);
1488 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
1489 struct mpi3mr_drv_cmd *drv_cmd);
1490 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
1491 struct mpi3mr_drv_cmd *drv_cmd);
1492 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data,
1493 u16 event_data_size);
1494 struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle(
1495 struct mpi3mr_ioc *mrioc, u16 handle);
1496 extern const struct attribute_group *mpi3mr_host_groups[];
1497 extern const struct attribute_group *mpi3mr_dev_groups[];
1498
1499 extern struct sas_function_template mpi3mr_transport_functions;
1500 extern struct scsi_transport_template *mpi3mr_transport_template;
1501
1502 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1503 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec);
1504 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1505 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
1506 u32 form_spec);
1507 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1508 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
1509 u32 form_spec);
1510 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1511 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
1512 u32 form_spec);
1513 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1514 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
1515 u32 form_spec);
1516 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1517 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
1518 u32 form_spec);
1519 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
1520 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz);
1521 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1522 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1523 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1524 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1525 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
1526 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz);
1527 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc,
1528 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_type);
1529
1530 u8 mpi3mr_is_expander_device(u16 device_info);
1531 int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle);
1532 void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address,
1533 struct mpi3mr_hba_port *hba_port);
1534 struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc
1535 *mrioc, u16 handle);
1536 struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc,
1537 u8 port_id);
1538 void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc);
1539 void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc);
1540 void mpi3mr_update_links(struct mpi3mr_ioc *mrioc,
1541 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate,
1542 struct mpi3mr_hba_port *hba_port);
1543 void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc,
1544 struct mpi3mr_tgt_dev *tgtdev);
1545 int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc,
1546 struct mpi3mr_tgt_dev *tgtdev);
1547 void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc,
1548 struct mpi3mr_tgt_dev *tgtdev);
1549 struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy(
1550 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy);
1551 void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc,
1552 bool device_add);
1553 void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc);
1554 void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc);
1555 void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc);
1556 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc);
1557 void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc);
1558 void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc);
1559 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc);
1560 void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc,
1561 struct mpi3mr_sas_node *sas_expander);
1562 void mpi3mr_alloc_diag_bufs(struct mpi3mr_ioc *mrioc);
1563 int mpi3mr_post_diag_bufs(struct mpi3mr_ioc *mrioc);
1564 int mpi3mr_issue_diag_buf_release(struct mpi3mr_ioc *mrioc,
1565 struct diag_buffer_desc *diag_buffer);
1566 void mpi3mr_release_diag_bufs(struct mpi3mr_ioc *mrioc, u8 skip_rel_action);
1567 void mpi3mr_set_trigger_data_in_hdb(struct diag_buffer_desc *hdb,
1568 u8 type, union mpi3mr_trigger_data *trigger_data, bool force);
1569 int mpi3mr_refresh_trigger(struct mpi3mr_ioc *mrioc, u8 page_type);
1570 struct diag_buffer_desc *mpi3mr_diag_buffer_for_type(struct mpi3mr_ioc *mrioc,
1571 u8 buf_type);
1572 int mpi3mr_issue_diag_buf_post(struct mpi3mr_ioc *mrioc,
1573 struct diag_buffer_desc *diag_buffer);
1574 void mpi3mr_set_trigger_data_in_all_hdb(struct mpi3mr_ioc *mrioc,
1575 u8 type, union mpi3mr_trigger_data *trigger_data, bool force);
1576 void mpi3mr_reply_trigger(struct mpi3mr_ioc *mrioc, u16 iocstatus,
1577 u32 iocloginfo);
1578 void mpi3mr_hdb_trigger_data_event(struct mpi3mr_ioc *mrioc,
1579 struct trigger_event_data *event_data);
1580 void mpi3mr_scsisense_trigger(struct mpi3mr_ioc *mrioc, u8 senseky, u8 asc,
1581 u8 ascq);
1582 void mpi3mr_event_trigger(struct mpi3mr_ioc *mrioc, u8 event);
1583 void mpi3mr_global_trigger(struct mpi3mr_ioc *mrioc, u64 trigger_data);
1584 void mpi3mr_hdbstatuschg_evt_th(struct mpi3mr_ioc *mrioc,
1585 struct mpi3_event_notification_reply *event_reply);
1586 #endif /*MPI3MR_H_INCLUDED*/
1587