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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Universal Flash Storage Host controller driver
4  * Copyright (C) 2011-2013 Samsung India Software Operations
5  *
6  * Authors:
7  *	Santosh Yaraganavi <santosh.sy@samsung.com>
8  *	Vinayak Holikatti <h.vinayak@samsung.com>
9  */
10 
11 #ifndef _UFS_H
12 #define _UFS_H
13 
14 #include <linux/bitops.h>
15 #include <linux/types.h>
16 #include <linux/android_vendor.h>
17 #include <linux/android_kabi.h>
18 #include <uapi/scsi/scsi_bsg_ufs.h>
19 #include <linux/time64.h>
20 
21 /*
22  * Using static_assert() is not allowed in UAPI header files. Hence the check
23  * in this header file of the size of struct utp_upiu_header.
24  */
25 static_assert(sizeof(struct utp_upiu_header) == 12);
26 
27 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
28 #define QUERY_DESC_MAX_SIZE       255
29 #define QUERY_DESC_MIN_SIZE       2
30 #define QUERY_DESC_HDR_SIZE       2
31 #define QUERY_OSF_SIZE            (GENERAL_UPIU_REQUEST_SIZE - \
32 					(sizeof(struct utp_upiu_header)))
33 #define UFS_SENSE_SIZE	18
34 
35 /*
36  * UFS device may have standard LUs and LUN id could be from 0x00 to
37  * 0x7F. Standard LUs use "Peripheral Device Addressing Format".
38  * UFS device may also have the Well Known LUs (also referred as W-LU)
39  * which again could be from 0x00 to 0x7F. For W-LUs, device only use
40  * the "Extended Addressing Format" which means the W-LUNs would be
41  * from 0xc100 (SCSI_W_LUN_BASE) onwards.
42  * This means max. LUN number reported from UFS device could be 0xC17F.
43  */
44 #define UFS_UPIU_MAX_UNIT_NUM_ID	0x7F
45 #define UFS_MAX_LUNS		(SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
46 #define UFS_UPIU_WLUN_ID	(1 << 7)
47 
48 /* WriteBooster buffer is available only for the logical unit from 0 to 7 */
49 #define UFS_UPIU_MAX_WB_LUN_ID	8
50 
51 /*
52  * WriteBooster buffer lifetime has a limit setted by vendor.
53  * If it is over the limit, WriteBooster feature will be disabled.
54  */
55 #define UFS_WB_EXCEED_LIFETIME		0x0B
56 
57 /*
58  * In UFS Spec, the Extra Header Segment (EHS) starts from byte 32 in UPIU request/response packet
59  */
60 #define EHS_OFFSET_IN_RESPONSE 32
61 
62 /* Well known logical unit id in LUN field of UPIU */
63 enum {
64 	UFS_UPIU_REPORT_LUNS_WLUN	= 0x81,
65 	UFS_UPIU_UFS_DEVICE_WLUN	= 0xD0,
66 	UFS_UPIU_BOOT_WLUN		= 0xB0,
67 	UFS_UPIU_RPMB_WLUN		= 0xC4,
68 };
69 
70 /*
71  * UFS Protocol Information Unit related definitions
72  */
73 
74 /* Task management functions */
75 enum {
76 	UFS_ABORT_TASK		= 0x01,
77 	UFS_ABORT_TASK_SET	= 0x02,
78 	UFS_CLEAR_TASK_SET	= 0x04,
79 	UFS_LOGICAL_RESET	= 0x08,
80 	UFS_QUERY_TASK		= 0x80,
81 	UFS_QUERY_TASK_SET	= 0x81,
82 };
83 
84 /* UTP UPIU Transaction Codes Initiator to Target */
85 enum upiu_request_transaction {
86 	UPIU_TRANSACTION_NOP_OUT	= 0x00,
87 	UPIU_TRANSACTION_COMMAND	= 0x01,
88 	UPIU_TRANSACTION_DATA_OUT	= 0x02,
89 	UPIU_TRANSACTION_TASK_REQ	= 0x04,
90 	UPIU_TRANSACTION_QUERY_REQ	= 0x16,
91 };
92 
93 /* UTP UPIU Transaction Codes Target to Initiator */
94 enum upiu_response_transaction {
95 	UPIU_TRANSACTION_NOP_IN		= 0x20,
96 	UPIU_TRANSACTION_RESPONSE	= 0x21,
97 	UPIU_TRANSACTION_DATA_IN	= 0x22,
98 	UPIU_TRANSACTION_TASK_RSP	= 0x24,
99 	UPIU_TRANSACTION_READY_XFER	= 0x31,
100 	UPIU_TRANSACTION_QUERY_RSP	= 0x36,
101 	UPIU_TRANSACTION_REJECT_UPIU	= 0x3F,
102 };
103 
104 /* UPIU Read/Write flags. See also table "UPIU Flags" in the UFS standard. */
105 enum {
106 	UPIU_CMD_FLAGS_NONE	= 0x00,
107 	UPIU_CMD_FLAGS_CP	= 0x04,
108 	UPIU_CMD_FLAGS_WRITE	= 0x20,
109 	UPIU_CMD_FLAGS_READ	= 0x40,
110 };
111 
112 /* UPIU response flags */
113 enum {
114 	UPIU_RSP_FLAG_UNDERFLOW	= 0x20,
115 	UPIU_RSP_FLAG_OVERFLOW	= 0x40,
116 };
117 
118 /* UPIU Task Attributes */
119 enum {
120 	UPIU_TASK_ATTR_SIMPLE	= 0x00,
121 	UPIU_TASK_ATTR_ORDERED	= 0x01,
122 	UPIU_TASK_ATTR_HEADQ	= 0x02,
123 	UPIU_TASK_ATTR_ACA	= 0x03,
124 };
125 
126 /* UPIU Query request function */
127 enum {
128 	UPIU_QUERY_FUNC_STANDARD_READ_REQUEST           = 0x01,
129 	UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST          = 0x81,
130 };
131 
132 /* Flag idn for Query Requests*/
133 enum flag_idn {
134 	QUERY_FLAG_IDN_FDEVICEINIT			= 0x01,
135 	QUERY_FLAG_IDN_PERMANENT_WPE			= 0x02,
136 	QUERY_FLAG_IDN_PWR_ON_WPE			= 0x03,
137 	QUERY_FLAG_IDN_BKOPS_EN				= 0x04,
138 	QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE		= 0x05,
139 	QUERY_FLAG_IDN_PURGE_ENABLE			= 0x06,
140 	QUERY_FLAG_IDN_RESERVED2			= 0x07,
141 	QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL		= 0x08,
142 	QUERY_FLAG_IDN_BUSY_RTC				= 0x09,
143 	QUERY_FLAG_IDN_RESERVED3			= 0x0A,
144 	QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE	= 0x0B,
145 	QUERY_FLAG_IDN_WB_EN                            = 0x0E,
146 	QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN                 = 0x0F,
147 	QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8     = 0x10,
148 	QUERY_FLAG_IDN_HPB_RESET                        = 0x11,
149 	QUERY_FLAG_IDN_HPB_EN				= 0x12,
150 };
151 
152 /* Attribute idn for Query requests */
153 enum attr_idn {
154 	QUERY_ATTR_IDN_BOOT_LU_EN		= 0x00,
155 	QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD	= 0x01,
156 	QUERY_ATTR_IDN_POWER_MODE		= 0x02,
157 	QUERY_ATTR_IDN_ACTIVE_ICC_LVL		= 0x03,
158 	QUERY_ATTR_IDN_OOO_DATA_EN		= 0x04,
159 	QUERY_ATTR_IDN_BKOPS_STATUS		= 0x05,
160 	QUERY_ATTR_IDN_PURGE_STATUS		= 0x06,
161 	QUERY_ATTR_IDN_MAX_DATA_IN		= 0x07,
162 	QUERY_ATTR_IDN_MAX_DATA_OUT		= 0x08,
163 	QUERY_ATTR_IDN_DYN_CAP_NEEDED		= 0x09,
164 	QUERY_ATTR_IDN_REF_CLK_FREQ		= 0x0A,
165 	QUERY_ATTR_IDN_CONF_DESC_LOCK		= 0x0B,
166 	QUERY_ATTR_IDN_MAX_NUM_OF_RTT		= 0x0C,
167 	QUERY_ATTR_IDN_EE_CONTROL		= 0x0D,
168 	QUERY_ATTR_IDN_EE_STATUS		= 0x0E,
169 	QUERY_ATTR_IDN_SECONDS_PASSED		= 0x0F,
170 	QUERY_ATTR_IDN_CNTX_CONF		= 0x10,
171 	QUERY_ATTR_IDN_CORR_PRG_BLK_NUM		= 0x11,
172 	QUERY_ATTR_IDN_RESERVED2		= 0x12,
173 	QUERY_ATTR_IDN_RESERVED3		= 0x13,
174 	QUERY_ATTR_IDN_FFU_STATUS		= 0x14,
175 	QUERY_ATTR_IDN_PSA_STATE		= 0x15,
176 	QUERY_ATTR_IDN_PSA_DATA_SIZE		= 0x16,
177 	QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME	= 0x17,
178 	QUERY_ATTR_IDN_CASE_ROUGH_TEMP          = 0x18,
179 	QUERY_ATTR_IDN_HIGH_TEMP_BOUND          = 0x19,
180 	QUERY_ATTR_IDN_LOW_TEMP_BOUND           = 0x1A,
181 	QUERY_ATTR_IDN_WB_FLUSH_STATUS	        = 0x1C,
182 	QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE       = 0x1D,
183 	QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST    = 0x1E,
184 	QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE        = 0x1F,
185 	QUERY_ATTR_IDN_EXT_IID_EN		= 0x2A,
186 	QUERY_ATTR_IDN_TIMESTAMP		= 0x30,
187 	QUERY_ATTR_IDN_DEV_LVL_EXCEPTION_ID     = 0x34,
188 };
189 
190 /* The constants below are not in enum attr_idn to preseve the GKI ABI. */
191 enum {
192 	QUERY_ATTR_IDN_HID_DEFRAG_OPERATION	= 0x35,
193 	QUERY_ATTR_IDN_HID_AVAILABLE_SIZE	= 0x36,
194 	QUERY_ATTR_IDN_HID_SIZE			= 0x37,
195 	QUERY_ATTR_IDN_HID_PROGRESS_RATIO	= 0x38,
196 	QUERY_ATTR_IDN_HID_STATE		= 0x39,
197 };
198 
199 /* Descriptor idn for Query requests */
200 enum desc_idn {
201 	QUERY_DESC_IDN_DEVICE		= 0x0,
202 	QUERY_DESC_IDN_CONFIGURATION	= 0x1,
203 	QUERY_DESC_IDN_UNIT		= 0x2,
204 	QUERY_DESC_IDN_RFU_0		= 0x3,
205 	QUERY_DESC_IDN_INTERCONNECT	= 0x4,
206 	QUERY_DESC_IDN_STRING		= 0x5,
207 	QUERY_DESC_IDN_RFU_1		= 0x6,
208 	QUERY_DESC_IDN_GEOMETRY		= 0x7,
209 	QUERY_DESC_IDN_POWER		= 0x8,
210 	QUERY_DESC_IDN_HEALTH           = 0x9,
211 	QUERY_DESC_IDN_MAX,
212 };
213 
214 enum desc_header_offset {
215 	QUERY_DESC_LENGTH_OFFSET	= 0x00,
216 	QUERY_DESC_DESC_TYPE_OFFSET	= 0x01,
217 };
218 
219 /* Unit descriptor parameters offsets in bytes*/
220 enum unit_desc_param {
221 	UNIT_DESC_PARAM_LEN			= 0x0,
222 	UNIT_DESC_PARAM_TYPE			= 0x1,
223 	UNIT_DESC_PARAM_UNIT_INDEX		= 0x2,
224 	UNIT_DESC_PARAM_LU_ENABLE		= 0x3,
225 	UNIT_DESC_PARAM_BOOT_LUN_ID		= 0x4,
226 	UNIT_DESC_PARAM_LU_WR_PROTECT		= 0x5,
227 	UNIT_DESC_PARAM_LU_Q_DEPTH		= 0x6,
228 	UNIT_DESC_PARAM_PSA_SENSITIVE		= 0x7,
229 	UNIT_DESC_PARAM_MEM_TYPE		= 0x8,
230 	UNIT_DESC_PARAM_DATA_RELIABILITY	= 0x9,
231 	UNIT_DESC_PARAM_LOGICAL_BLK_SIZE	= 0xA,
232 	UNIT_DESC_PARAM_LOGICAL_BLK_COUNT	= 0xB,
233 	UNIT_DESC_PARAM_ERASE_BLK_SIZE		= 0x13,
234 	UNIT_DESC_PARAM_PROVISIONING_TYPE	= 0x17,
235 	UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT	= 0x18,
236 	UNIT_DESC_PARAM_CTX_CAPABILITIES	= 0x20,
237 	UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1	= 0x22,
238 	UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS	= 0x23,
239 	UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF	= 0x25,
240 	UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS	= 0x27,
241 	UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS	= 0x29,
242 };
243 
244 /* RPMB Unit descriptor parameters offsets in bytes*/
245 enum rpmb_unit_desc_param {
246 	RPMB_UNIT_DESC_PARAM_LEN		= 0x0,
247 	RPMB_UNIT_DESC_PARAM_TYPE		= 0x1,
248 	RPMB_UNIT_DESC_PARAM_UNIT_INDEX		= 0x2,
249 	RPMB_UNIT_DESC_PARAM_LU_ENABLE		= 0x3,
250 	RPMB_UNIT_DESC_PARAM_BOOT_LUN_ID	= 0x4,
251 	RPMB_UNIT_DESC_PARAM_LU_WR_PROTECT	= 0x5,
252 	RPMB_UNIT_DESC_PARAM_LU_Q_DEPTH		= 0x6,
253 	RPMB_UNIT_DESC_PARAM_PSA_SENSITIVE	= 0x7,
254 	RPMB_UNIT_DESC_PARAM_MEM_TYPE		= 0x8,
255 	RPMB_UNIT_DESC_PARAM_REGION_EN		= 0x9,
256 	RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_SIZE	= 0xA,
257 	RPMB_UNIT_DESC_PARAM_LOGICAL_BLK_COUNT	= 0xB,
258 	RPMB_UNIT_DESC_PARAM_REGION0_SIZE	= 0x13,
259 	RPMB_UNIT_DESC_PARAM_REGION1_SIZE	= 0x14,
260 	RPMB_UNIT_DESC_PARAM_REGION2_SIZE	= 0x15,
261 	RPMB_UNIT_DESC_PARAM_REGION3_SIZE	= 0x16,
262 	RPMB_UNIT_DESC_PARAM_PROVISIONING_TYPE	= 0x17,
263 	RPMB_UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT	= 0x18,
264 };
265 
266 /* Device descriptor parameters offsets in bytes*/
267 enum device_desc_param {
268 	DEVICE_DESC_PARAM_LEN			= 0x0,
269 	DEVICE_DESC_PARAM_TYPE			= 0x1,
270 	DEVICE_DESC_PARAM_DEVICE_TYPE		= 0x2,
271 	DEVICE_DESC_PARAM_DEVICE_CLASS		= 0x3,
272 	DEVICE_DESC_PARAM_DEVICE_SUB_CLASS	= 0x4,
273 	DEVICE_DESC_PARAM_PRTCL			= 0x5,
274 	DEVICE_DESC_PARAM_NUM_LU		= 0x6,
275 	DEVICE_DESC_PARAM_NUM_WLU		= 0x7,
276 	DEVICE_DESC_PARAM_BOOT_ENBL		= 0x8,
277 	DEVICE_DESC_PARAM_DESC_ACCSS_ENBL	= 0x9,
278 	DEVICE_DESC_PARAM_INIT_PWR_MODE		= 0xA,
279 	DEVICE_DESC_PARAM_HIGH_PR_LUN		= 0xB,
280 	DEVICE_DESC_PARAM_SEC_RMV_TYPE		= 0xC,
281 	DEVICE_DESC_PARAM_SEC_LU		= 0xD,
282 	DEVICE_DESC_PARAM_BKOP_TERM_LT		= 0xE,
283 	DEVICE_DESC_PARAM_ACTVE_ICC_LVL		= 0xF,
284 	DEVICE_DESC_PARAM_SPEC_VER		= 0x10,
285 	DEVICE_DESC_PARAM_MANF_DATE		= 0x12,
286 	DEVICE_DESC_PARAM_MANF_NAME		= 0x14,
287 	DEVICE_DESC_PARAM_PRDCT_NAME		= 0x15,
288 	DEVICE_DESC_PARAM_SN			= 0x16,
289 	DEVICE_DESC_PARAM_OEM_ID		= 0x17,
290 	DEVICE_DESC_PARAM_MANF_ID		= 0x18,
291 	DEVICE_DESC_PARAM_UD_OFFSET		= 0x1A,
292 	DEVICE_DESC_PARAM_UD_LEN		= 0x1B,
293 	DEVICE_DESC_PARAM_RTT_CAP		= 0x1C,
294 	DEVICE_DESC_PARAM_FRQ_RTC		= 0x1D,
295 	DEVICE_DESC_PARAM_UFS_FEAT		= 0x1F,
296 	DEVICE_DESC_PARAM_FFU_TMT		= 0x20,
297 	DEVICE_DESC_PARAM_Q_DPTH		= 0x21,
298 	DEVICE_DESC_PARAM_DEV_VER		= 0x22,
299 	DEVICE_DESC_PARAM_NUM_SEC_WPA		= 0x24,
300 	DEVICE_DESC_PARAM_PSA_MAX_DATA		= 0x25,
301 	DEVICE_DESC_PARAM_PSA_TMT		= 0x29,
302 	DEVICE_DESC_PARAM_PRDCT_REV		= 0x2A,
303 	DEVICE_DESC_PARAM_HPB_VER		= 0x40,
304 	DEVICE_DESC_PARAM_HPB_CONTROL		= 0x42,
305 	DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP	= 0x4F,
306 	DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN	= 0x53,
307 	DEVICE_DESC_PARAM_WB_TYPE		= 0x54,
308 	DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
309 };
310 
311 /* Interconnect descriptor parameters offsets in bytes*/
312 enum interconnect_desc_param {
313 	INTERCONNECT_DESC_PARAM_LEN		= 0x0,
314 	INTERCONNECT_DESC_PARAM_TYPE		= 0x1,
315 	INTERCONNECT_DESC_PARAM_UNIPRO_VER	= 0x2,
316 	INTERCONNECT_DESC_PARAM_MPHY_VER	= 0x4,
317 };
318 
319 /* Geometry descriptor parameters offsets in bytes*/
320 enum geometry_desc_param {
321 	GEOMETRY_DESC_PARAM_LEN			= 0x0,
322 	GEOMETRY_DESC_PARAM_TYPE		= 0x1,
323 	GEOMETRY_DESC_PARAM_DEV_CAP		= 0x4,
324 	GEOMETRY_DESC_PARAM_MAX_NUM_LUN		= 0xC,
325 	GEOMETRY_DESC_PARAM_SEG_SIZE		= 0xD,
326 	GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE	= 0x11,
327 	GEOMETRY_DESC_PARAM_MIN_BLK_SIZE	= 0x12,
328 	GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE	= 0x13,
329 	GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE	= 0x14,
330 	GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE	= 0x15,
331 	GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE	= 0x16,
332 	GEOMETRY_DESC_PARAM_RPMB_RW_SIZE	= 0x17,
333 	GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC	= 0x18,
334 	GEOMETRY_DESC_PARAM_DATA_ORDER		= 0x19,
335 	GEOMETRY_DESC_PARAM_MAX_NUM_CTX		= 0x1A,
336 	GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE	= 0x1B,
337 	GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE	= 0x1C,
338 	GEOMETRY_DESC_PARAM_SEC_RM_TYPES	= 0x1D,
339 	GEOMETRY_DESC_PARAM_MEM_TYPES		= 0x1E,
340 	GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS	= 0x20,
341 	GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR	= 0x24,
342 	GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS	= 0x26,
343 	GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR	= 0x2A,
344 	GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS	= 0x2C,
345 	GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR	= 0x30,
346 	GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS	= 0x32,
347 	GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR	= 0x36,
348 	GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS	= 0x38,
349 	GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR	= 0x3C,
350 	GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS	= 0x3E,
351 	GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR	= 0x42,
352 	GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE	= 0x44,
353 	GEOMETRY_DESC_PARAM_HPB_REGION_SIZE	= 0x48,
354 	GEOMETRY_DESC_PARAM_HPB_NUMBER_LU	= 0x49,
355 	GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE	= 0x4A,
356 	GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS	= 0x4B,
357 	GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS	= 0x4F,
358 	GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS	= 0x53,
359 	GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ	= 0x54,
360 	GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE	= 0x55,
361 	GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE	= 0x56,
362 };
363 
364 /* Health descriptor parameters offsets in bytes*/
365 enum health_desc_param {
366 	HEALTH_DESC_PARAM_LEN			= 0x0,
367 	HEALTH_DESC_PARAM_TYPE			= 0x1,
368 	HEALTH_DESC_PARAM_EOL_INFO		= 0x2,
369 	HEALTH_DESC_PARAM_LIFE_TIME_EST_A	= 0x3,
370 	HEALTH_DESC_PARAM_LIFE_TIME_EST_B	= 0x4,
371 };
372 
373 /* WriteBooster buffer mode */
374 enum {
375 	WB_BUF_MODE_LU_DEDICATED	= 0x0,
376 	WB_BUF_MODE_SHARED		= 0x1,
377 };
378 
379 /*
380  * Logical Unit Write Protect
381  * 00h: LU not write protected
382  * 01h: LU write protected when fPowerOnWPEn =1
383  * 02h: LU permanently write protected when fPermanentWPEn =1
384  */
385 enum ufs_lu_wp_type {
386 	UFS_LU_NO_WP		= 0x00,
387 	UFS_LU_POWER_ON_WP	= 0x01,
388 	UFS_LU_PERM_WP		= 0x02,
389 };
390 
391 /* bActiveICCLevel parameter current units */
392 enum {
393 	UFSHCD_NANO_AMP		= 0,
394 	UFSHCD_MICRO_AMP	= 1,
395 	UFSHCD_MILI_AMP		= 2,
396 	UFSHCD_AMP		= 3,
397 };
398 
399 /* Possible values for dExtendedUFSFeaturesSupport */
400 enum {
401 	UFS_DEV_HIGH_TEMP_NOTIF		= BIT(4),
402 	UFS_DEV_LOW_TEMP_NOTIF		= BIT(5),
403 	UFS_DEV_EXT_TEMP_NOTIF		= BIT(6),
404 	UFS_DEV_HPB_SUPPORT		= BIT(7),
405 	UFS_DEV_WRITE_BOOSTER_SUP	= BIT(8),
406 	UFS_DEV_EXT_IID_SUP		= BIT(16),
407 	UFS_DEV_LVL_EXCEPTION_SUP       = BIT(12),
408 	UFS_DEV_HID_SUPPORT		= BIT(13),
409 };
410 #define UFS_DEV_HPB_SUPPORT_VERSION		0x310
411 
412 #define POWER_DESC_MAX_ACTV_ICC_LVLS		16
413 
414 /* Attribute  bActiveICCLevel parameter bit masks definitions */
415 #define ATTR_ICC_LVL_UNIT_OFFSET	14
416 #define ATTR_ICC_LVL_UNIT_MASK		(0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
417 #define ATTR_ICC_LVL_VALUE_MASK		0x3FF
418 
419 /* Power descriptor parameters offsets in bytes */
420 enum power_desc_param_offset {
421 	PWR_DESC_LEN			= 0x0,
422 	PWR_DESC_TYPE			= 0x1,
423 	PWR_DESC_ACTIVE_LVLS_VCC_0	= 0x2,
424 	PWR_DESC_ACTIVE_LVLS_VCCQ_0	= 0x22,
425 	PWR_DESC_ACTIVE_LVLS_VCCQ2_0	= 0x42,
426 };
427 
428 /* Exception event mask values */
429 enum {
430 	MASK_EE_STATUS			= 0xFFFF,
431 	MASK_EE_DYNCAP_EVENT		= BIT(0),
432 	MASK_EE_SYSPOOL_EVENT		= BIT(1),
433 	MASK_EE_URGENT_BKOPS		= BIT(2),
434 	MASK_EE_TOO_HIGH_TEMP		= BIT(3),
435 	MASK_EE_TOO_LOW_TEMP		= BIT(4),
436 	MASK_EE_WRITEBOOSTER_EVENT	= BIT(5),
437 	MASK_EE_PERFORMANCE_THROTTLING	= BIT(6),
438 	MASK_EE_DEV_LVL_EXCEPTION       = BIT(7),
439 	MASK_EE_HEALTH_CRITICAL		= BIT(9),
440 };
441 #define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP)
442 
443 /* Background operation status */
444 enum bkops_status {
445 	BKOPS_STATUS_NO_OP               = 0x0,
446 	BKOPS_STATUS_NON_CRITICAL        = 0x1,
447 	BKOPS_STATUS_PERF_IMPACT         = 0x2,
448 	BKOPS_STATUS_CRITICAL            = 0x3,
449 	BKOPS_STATUS_MAX		 = BKOPS_STATUS_CRITICAL,
450 };
451 
452 /* UTP QUERY Transaction Specific Fields OpCode */
453 enum query_opcode {
454 	UPIU_QUERY_OPCODE_NOP		= 0x0,
455 	UPIU_QUERY_OPCODE_READ_DESC	= 0x1,
456 	UPIU_QUERY_OPCODE_WRITE_DESC	= 0x2,
457 	UPIU_QUERY_OPCODE_READ_ATTR	= 0x3,
458 	UPIU_QUERY_OPCODE_WRITE_ATTR	= 0x4,
459 	UPIU_QUERY_OPCODE_READ_FLAG	= 0x5,
460 	UPIU_QUERY_OPCODE_SET_FLAG	= 0x6,
461 	UPIU_QUERY_OPCODE_CLEAR_FLAG	= 0x7,
462 	UPIU_QUERY_OPCODE_TOGGLE_FLAG	= 0x8,
463 };
464 
465 /* bRefClkFreq attribute values */
466 enum ufs_ref_clk_freq {
467 	REF_CLK_FREQ_19_2_MHZ	= 0,
468 	REF_CLK_FREQ_26_MHZ	= 1,
469 	REF_CLK_FREQ_38_4_MHZ	= 2,
470 	REF_CLK_FREQ_52_MHZ	= 3,
471 	REF_CLK_FREQ_INVAL	= -1,
472 };
473 
474 /* bDefragOperation attribute values */
475 enum ufs_hid_defrag_operation {
476 	HID_ANALYSIS_AND_DEFRAG_DISABLE	= 0,
477 	HID_ANALYSIS_ENABLE		= 1,
478 	HID_ANALYSIS_AND_DEFRAG_ENABLE	= 2,
479 };
480 
481 /* bHIDState attribute values */
482 enum ufs_hid_state {
483 	HID_IDLE		= 0,
484 	ANALYSIS_IN_PROGRESS	= 1,
485 	DEFRAG_REQUIRED		= 2,
486 	DEFRAG_IN_PROGRESS	= 3,
487 	DEFRAG_COMPLETED	= 4,
488 	DEFRAG_NOT_REQUIRED	= 5,
489 	NUM_UFS_HID_STATES	= 6,
490 };
491 
492 /* Query response result code */
493 enum {
494 	QUERY_RESULT_SUCCESS                    = 0x00,
495 	QUERY_RESULT_NOT_READABLE               = 0xF6,
496 	QUERY_RESULT_NOT_WRITEABLE              = 0xF7,
497 	QUERY_RESULT_ALREADY_WRITTEN            = 0xF8,
498 	QUERY_RESULT_INVALID_LENGTH             = 0xF9,
499 	QUERY_RESULT_INVALID_VALUE              = 0xFA,
500 	QUERY_RESULT_INVALID_SELECTOR           = 0xFB,
501 	QUERY_RESULT_INVALID_INDEX              = 0xFC,
502 	QUERY_RESULT_INVALID_IDN                = 0xFD,
503 	QUERY_RESULT_INVALID_OPCODE             = 0xFE,
504 	QUERY_RESULT_GENERAL_FAILURE            = 0xFF,
505 };
506 
507 /* UTP Transfer Request Command Type (CT) */
508 enum {
509 	UPIU_COMMAND_SET_TYPE_SCSI	= 0x0,
510 	UPIU_COMMAND_SET_TYPE_UFS	= 0x1,
511 	UPIU_COMMAND_SET_TYPE_QUERY	= 0x2,
512 };
513 
514 /* Offset of the response code in the UPIU header */
515 #define UPIU_RSP_CODE_OFFSET		8
516 
517 enum {
518 	MASK_TM_SERVICE_RESP		= 0xFF,
519 };
520 
521 /* Task management service response */
522 enum {
523 	UPIU_TASK_MANAGEMENT_FUNC_COMPL		= 0x00,
524 	UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
525 	UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED	= 0x08,
526 	UPIU_TASK_MANAGEMENT_FUNC_FAILED	= 0x05,
527 	UPIU_INCORRECT_LOGICAL_UNIT_NO		= 0x09,
528 };
529 
530 /* UFS device power modes */
531 enum ufs_dev_pwr_mode {
532 	UFS_ACTIVE_PWR_MODE	= 1,
533 	UFS_SLEEP_PWR_MODE	= 2,
534 	UFS_POWERDOWN_PWR_MODE	= 3,
535 	UFS_DEEPSLEEP_PWR_MODE	= 4,
536 };
537 
538 #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
539 
540 /**
541  * struct utp_cmd_rsp - Response UPIU structure
542  * @residual_transfer_count: Residual transfer count DW-3
543  * @reserved: Reserved double words DW-4 to DW-7
544  * @sense_data_len: Sense data length DW-8 U16
545  * @sense_data: Sense data field DW-8 to DW-12
546  */
547 struct utp_cmd_rsp {
548 	__be32 residual_transfer_count;
549 	__be32 reserved[4];
550 	__be16 sense_data_len;
551 	u8 sense_data[UFS_SENSE_SIZE];
552 };
553 
554 /**
555  * struct utp_upiu_rsp - general upiu response structure
556  * @header: UPIU header structure DW-0 to DW-2
557  * @sr: fields structure for scsi command DW-3 to DW-12
558  * @qr: fields structure for query request DW-3 to DW-7
559  */
560 struct utp_upiu_rsp {
561 	struct utp_upiu_header header;
562 	union {
563 		struct utp_cmd_rsp sr;
564 		struct utp_upiu_query qr;
565 	};
566 };
567 
568 /*
569  * VCCQ & VCCQ2 current requirement when UFS device is in sleep state
570  * and link is in Hibern8 state.
571  */
572 #define UFS_VREG_LPM_LOAD_UA	1000 /* uA */
573 
574 struct ufs_vreg {
575 	struct regulator *reg;
576 	const char *name;
577 	bool always_on;
578 	bool enabled;
579 	int max_uA;
580 };
581 
582 struct ufs_vreg_info {
583 	struct ufs_vreg *vcc;
584 	struct ufs_vreg *vccq;
585 	struct ufs_vreg *vccq2;
586 	struct ufs_vreg *vdd_hba;
587 };
588 
589 /* UFS device descriptor wPeriodicRTCUpdate bit9 defines RTC time baseline */
590 #define UFS_RTC_TIME_BASELINE BIT(9)
591 
592 enum ufs_rtc_time {
593 	UFS_RTC_RELATIVE,
594 	UFS_RTC_ABSOLUTE
595 };
596 
597 struct ufs_dev_info {
598 	bool	f_power_on_wp_en;
599 	/* Keeps information if any of the LU is power on write protected */
600 	bool	is_lu_power_on_wp;
601 	/* Maximum number of general LU supported by the UFS device */
602 	u8	max_lu_supported;
603 	u16	wmanufacturerid;
604 	/*UFS device Product Name */
605 	u8	*model;
606 	u16	wspecversion;
607 	u32	clk_gating_wait_us;
608 	/* Stores the depth of queue in UFS device */
609 	u8	bqueuedepth;
610 
611 	/* UFS WB related flags */
612 	bool    wb_enabled;
613 	bool    wb_buf_flush_enabled;
614 	u8	wb_dedicated_lu;
615 	u8      wb_buffer_type;
616 
617 	bool	b_rpm_dev_flush_capable;
618 	u8	b_presrv_uspc_en;
619 
620 	bool    b_advanced_rpmb_en;
621 
622 	/* UFS EXT_IID Enable */
623 	bool	b_ext_iid_en;
624 
625 	/* UFS RTC */
626 	enum ufs_rtc_time rtc_type;
627 	time64_t rtc_time_baseline;
628 	u32 rtc_update_period;
629 
630 	u8 rtt_cap; /* bDeviceRTTCap */
631 	ANDROID_KABI_RESERVE(1);
632 	ANDROID_KABI_RESERVE(2);
633 	ANDROID_OEM_DATA(1);
634 };
635 
636 /*
637  * This enum is used in string mapping in ufs_trace.h.
638  */
639 enum ufs_trace_str_t {
640 	UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP,
641 	UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QUERY_ERR,
642 	UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR
643 };
644 
645 /*
646  * Transaction Specific Fields (TSF) type in the UPIU package, this enum is
647  * used in ufs_trace.h for UFS command trace.
648  */
649 enum ufs_trace_tsf_t {
650 	UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT
651 };
652 
653 #endif /* End of Header */
654