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1 /*
2  * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at
6  *
7  *     http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 
16 #ifndef ADC_HI35XX_H
17 #define ADC_HI35XX_H
18 
19 #ifdef __cplusplus
20 #if __cplusplus
21 extern "C" {
22 #endif /* __cplusplus */
23 #endif /* __cplusplus */
24 
25 /*
26  * Adc Register Offsets
27  */
28 
29 #define HI35XX_ADC_CONFIG           0x0
30 #define HI35XX_ADC_GLITCH_SAMPLE    0x4
31 #define HI35XX_ADC_TIME_SCAN        0x8
32 #define HI35XX_ADC_INTR_EN          0x10
33 #define HI35XX_ADC_INTR_STATUS      0x14
34 #define HI35XX_ADC_INTR_CLEAR       0x18
35 #define HI35XX_ADC_START            0x1c
36 #define HI35XX_ADC_STOP             0x20
37 #define HI35XX_ADC_ACCURACY         0x24
38 #define HI35XX_ADC_ZERO             0x28
39 #define HI35XX_ADC_DATA0            0x2c
40 #define HI35XX_ADC_DATA1            0x30
41 
42 #define HI35XX_ADC_IO_CONFIG_BASE   0x111f0030
43 #define HI35XX_ADC_IO_CONFIG_SIZE   0x8
44 #define HI35XX_ADC_IO_CONFIG_0      0x0
45 #define HI35XX_ADC_IO_CONFIG_1      0x4
46 
47 #define CYCLE_SCAN_MODE             1
48 #define DEFAULT_DATA_WIDTH          8
49 #define MAX_DATA_WIDTH              10
50 #define DEFAULT_GLITCHSAMPLE        5000
51 #define TIME_SCAN_MINIMUM            20
52 #define TIME_SCAN_CALCULATOR     (1000000 * 3)
53 
54 #define DELTA_OFFSET                 20
55 #define DEGLITCH_OFFSET              17
56 #define SCAN_MODE_OFFSET             13
57 #define VALID_CHANNEL_OFFSET         8
58 
59 #define DATA_WIDTH_MASK             0x3ff
60 #define DELTA_MASK                  0xf
61 #define VALID_CHANNEL_MASK          0x3
62 #define CONFIG_REG_RESET_VALUE      0x80ff
63 #define PINCTRL_MASK                0xf
64 
65 enum ScanMode {
66     CYCLE_MODE = 0,
67     SINGLE_MODE,
68 };
69 
70 #ifdef __cplusplus
71 #if __cplusplus
72 }
73 #endif /* __cplusplus */
74 #endif /* __cplusplus */
75 #endif /* ADC_HI35XX_H */
76