1 /* 2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef DMAC_HI35XX_H 17 #define DMAC_HI35XX_H 18 19 #include "asm/platform.h" 20 21 #ifdef __cplusplus 22 #if __cplusplus 23 extern "C" { 24 #endif /* __cplusplus */ 25 #endif /* __cplusplus */ 26 27 #define HIDMAC_CHANNEL_NUM 8 28 #define HIDMAC_ENABLE 1 29 30 #define HIDMAC_MAX_PERIPHERALS 32 31 #define HIDMAC_PERI_ID_OFFSET 4 32 #define HIDMAC_SRC_WIDTH_OFFSET 16 33 #define HIDMAC_DST_WIDTH_OFFSET 12 34 #define HIDMAC_CH_ENABLE 1 35 36 enum HiDmacPeriphWidth { 37 PERI_MODE_8BIT = 0, 38 PERI_MODE_16BIT = 1, 39 PERI_MODE_32BIT = 2, 40 PERI_MODE_64BIT = 3, 41 }; 42 43 /* UART ADDRESS INFO */ 44 #define UART0_RX_ADDR (UART0_REG_BASE + 0x0) 45 #define UART0_TX_ADDR (UART0_REG_BASE + 0x0) 46 #define UART1_RX_ADDR (UART1_REG_BASE + 0x0) 47 #define UART1_TX_ADDR (UART1_REG_BASE + 0x0) 48 #define UART2_RX_ADDR (UART2_REG_BASE + 0x0) 49 #define UART2_TX_ADDR (UART2_REG_BASE + 0x0) 50 51 /* I2C ADDRESS INFO */ 52 #define I2C0_TX_FIFO (I2C0_REG_BASE + 0x20) 53 #define I2C0_RX_FIFO (I2C0_REG_BASE + 0x24) 54 #define I2C1_TX_FIFO (I2C1_REG_BASE + 0x20) 55 #define I2C1_RX_FIFO (I2C1_REG_BASE + 0x24) 56 #define I2C2_TX_FIFO (I2C2_REG_BASE + 0x20) 57 #define I2C2_RX_FIFO (I2C2_REG_BASE + 0x24) 58 59 /* SPI ADDRESS INFO */ 60 #define SPI0_RX_FIFO (0x120c0000 + 0x8) 61 #define SPI0_TX_FIFO (0x120c0000 + 0x8) 62 #define SPI1_RX_FIFO (0x120c1000 + 0x8) 63 #define SPI1_TX_FIFO (0x120c1000 + 0x8) 64 #define SPI2_RX_FIFO (0x120c2000 + 0x8) 65 #define SPI2_TX_FIFO (0x120c2000 + 0x8) 66 67 #define HIDMAC_PERI_CRG101_OFFSET 0x194 68 #define HIDMA0_AXI_OFFSET 2 69 #define HIDMA0_CLK_OFFSET 1 70 #define HIDMA0_RST_OFFSET 0 71 #define DDRAM_ADDR DDR_MEM_BASE 72 #define DDRAM_SIZE 0x3FFFFFFF 73 74 #define HIDMAC_INT_STAT_OFFSET 0x00 75 #define HIDMAC_INT_TC1_OFFSET 0x04 76 #define HIDMAC_INT_TC2_OFFSET 0x08 77 #define HIDMAC_INT_ERR1_OFFSET 0x0C 78 #define HIDMAC_INT_ERR2_OFFSET 0x10 79 #define HIDMAC_INT_ERR3_OFFSET 0x14 80 #define HIDMAC_INT_TC1_MASK_OFFSET 0x18 81 #define HIDMAC_INT_TC2_MASK_OFFSET 0x1C 82 #define HIDMAC_INT_ERR1_MASK_OFFSET 0x20 83 #define HIDMAC_INT_ERR2_MASK_OFFSET 0x24 84 #define HIDMAC_INT_ERR3_MASK_OFFSET 0x28 85 #define HIDMAC_INT_TC1_RAW_OFFSET 0x600 86 #define HIDMAC_INT_TC2_RAW_OFFSET 0x608 87 #define HIDMAC_INT_ERR1_RAW_OFFSET 0x610 88 #define HIDMAC_INT_ERR2_RAW_OFFSET 0x618 89 #define HIDMAC_INT_ERR3_RAW_OFFSET 0x620 90 #define HIDMAC_CH_PRI_OFFSET 0x688 91 #define HIDMAC_CH_STAT_OFFSET 0x690 92 #define HIDMAC_CX_CUR_SRC_OFFSET(x) (0x408 + (x) * 0x20) 93 #define HIDMAC_CX_CUR_DST_OFFSET(x) (0x410 + (x) * 0x20) 94 #define HIDMAC_CX_LLI_OFFSET_L(x) (0x800 + (x) * 0x40) 95 #define HIDMAC_CX_LLI_OFFSET_H(x) (0x804 + (x) * 0x40) 96 #define HIDMAC_CX_CNT0_OFFSET(x) (0x81C + (x) * 0x40) 97 #define HIDMAC_CX_SRC_OFFSET_L(x) (0x820 + (x) * 0x40) 98 #define HIDMAC_CX_SRC_OFFSET_H(x) (0x824 + (x) * 0x40) 99 #define HIDMAC_CX_DST_OFFSET_L(x) (0x828 + (x) * 0x40) 100 #define HIDMAC_CX_DST_OFFSET_H(x) (0x82C + (x) * 0x40) 101 #define HIDMAC_CX_CFG_OFFSET(x) (0x830 + (x) * 0x40) 102 103 /* others */ 104 #define HIDMAC_ALL_CHAN_CLR 0xFF 105 #define HIDMAC_INT_ENABLE_ALL_CHAN 0xFF 106 #define HIDMAC_CFG_SRC_INC (1 << 31) 107 #define HIDMAC_CFG_DST_INC (1 << 30) 108 #define HIDMAC_CFG_SRC_WIDTH_SHIFT 16 109 #define HIDMAC_CFG_DST_WIDTH_SHIFT 12 110 #define HIDMAC_WIDTH_8BIT 0x0 111 #define HIDMAC_WIDTH_16BIT 0x1 112 #define HIDMAC_WIDTH_32BIT 0x10 113 #define HIDMAC_WIDTH_64BIT 0x11 114 #define HIDMAC_BURST_WIDTH_MAX 16 115 #define HIDMAC_BURST_WIDTH_MIN 1 116 #define HIDMAC_CFG_SRC_BURST_SHIFT 24 117 #define HIDMAC_CFG_DST_BURST_SHIFT 20 118 #define HIDMAC_LLI_ALIGN 0x40 119 #define HIDMAC_LLI_DISABLE 0x0 120 #define HIDMAC_LLI_ENABLE 0x2 121 #define HIDMAC_CX_CFG_SIGNAL_SHIFT 0x4 122 #define HIDMAC_CX_CFG_MEM_TYPE 0x0 123 #define HIDMAC_CX_CFG_DEV_MEM_TYPE 0x1 124 #define HIDMAC_CX_CFG_TSF_TYPE_SHIFT 0x2 125 #define HIDMAC_CX_CFG_ITC_EN 0x1 126 #define HIDMAC_CX_CFG_ITC_EN_SHIFT 0x1 127 #define HIDMAC_CX_CFG_M2M 0xCFF00001 128 #define HIDMAC_CX_CFG_CHN_START 0x1 129 #define HIDMAC_CX_DISABLE 0x0 130 #define HIDMAC_M2M 0x0 131 #define HIDMAC_NOM2M 0x1 132 #define HIDMAC_TRQANS_MAX_SIZE (64 * 1024 - 1) 133 134 struct HiDmacPeripheral { 135 unsigned int periphId; // peripheral ID 136 uintptr_t periphAddr; // peripheral data register address 137 int hostSel; // config request 138 #define HIDMAC_HOST0 0 139 #define HIDMAC_HOST1 1 140 #define HIDMAC_NOT_USE (-1) 141 unsigned long transCfg; // default channel config word 142 unsigned int transWidth; // transfer data width 143 unsigned int dynPeripNum; // dynamic peripheral number 144 }; 145 146 #ifdef __cplusplus 147 #if __cplusplus 148 } 149 #endif /* __cplusplus */ 150 #endif /* __cplusplus */ 151 #endif /* DMAC_HI35XX_H */ 152