1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef MIPI_TX_HI35XX_H 17 #define MIPI_TX_HI35XX_H 18 19 /**************************************************************************** 20 * macro definition * 21 ****************************************************************************/ 22 #define MIPI_TX_REGS_ADDR 0x11270000 23 #define MIPI_TX_REGS_SIZE 0x10000 24 25 #define MIPI_TX_IRQ 120 26 27 #define MIPI_TX_CRG 0x1201010C 28 29 #define MIPI_TX_REF_CLK 27 30 31 #define TLPX 60 32 #define TCLK_PREPARE 60 33 #define TCLK_ZERO 250 34 #define TCLK_TRAIL 80 35 #define TPRE_DELAY 100 36 #define THS_PREPARE 80 37 #define THS_ZERO 180 38 #define THS_TRAIL 110 39 40 /* phy addr */ 41 #define PLL_SET0 0x60 42 #define PLL_SET1 0x64 43 #define PLL_SET2 0x65 44 #ifdef HI_FPGA 45 #define PLL_SET3 0x17 46 #endif 47 #define PLL_SET4 0x66 48 #define PLL_SET5 0x67 49 50 #define DATA0_TPRE_DELAY 0x28 51 #define DATA1_TPRE_DELAY 0x38 52 #define DATA2_TPRE_DELAY 0x48 53 #define DATA3_TPRE_DELAY 0x58 54 55 #define CLK_TLPX 0x10 56 #define CLK_TCLK_PREPARE 0x11 57 #define CLK_TCLK_ZERO 0x12 58 #define CLK_TCLK_TRAIL 0x13 59 60 #define DATA0_TLPX 0x20 61 #define DATA0_THS_PREPARE 0x21 62 #define DATA0_THS_ZERO 0x22 63 #define DATA0_THS_TRAIL 0x23 64 #define DATA1_TLPX 0x30 65 #define DATA1_THS_PREPARE 0x31 66 #define DATA1_THS_ZERO 0x32 67 #define DATA1_THS_TRAIL 0x33 68 #define DATA2_TLPX 0x40 69 #define DATA2_THS_PREPARE 0x41 70 #define DATA2_THS_ZERO 0x42 71 #define DATA2_THS_TRAIL 0x43 72 #define DATA3_TLPX 0x50 73 #define DATA3_THS_PREPARE 0x51 74 #define DATA3_THS_ZERO 0x52 75 #define DATA3_THS_TRAIL 0x53 76 77 #define MIPI_TX_READ_TIMEOUT_CNT 1000 78 79 #define PREPARE_COMPENSATE 10 80 #define ROUNDUP_VALUE 7999 81 #define INNER_PEROID 8000 /* 8 * 1000 ,1000 is 1us = 1000ns, 8 is division ratio */ 82 83 typedef struct { 84 unsigned char dataTpreDelay; 85 unsigned char clkTlpx; 86 unsigned char clkTclkPrepare; 87 unsigned char clkTclkZero; 88 unsigned char clkTclkTrail; 89 unsigned char dataTlpx; 90 unsigned char dataThsPrepare; 91 unsigned char dataThsZero; 92 unsigned char dataThsTrail; 93 } MipiTxPhyTimingParamTag; 94 95 typedef struct { 96 unsigned int vallDet; 97 unsigned int vactDet; 98 unsigned int hallDet; 99 unsigned int hactDet; 100 unsigned int hbpDet; 101 unsigned int hsaDet; 102 unsigned int vsaDet; 103 } MipiTxDevPhyTag; 104 105 void MipiTxDrvGetDevStatus(MipiTxDevPhyTag *phyCtx); 106 #endif 107