1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #ifndef SDHCI_H
17 #define SDHCI_H
18
19 #include "asm/dma.h"
20 #include "asm/io.h"
21 #include "asm/platform.h"
22 #include "device_resource_if.h"
23 #include "linux/scatterlist.h"
24 #include "los_bitmap.h"
25 #include "los_event.h"
26 #include "los_vm_iomap.h"
27 #include "los_vm_zone.h"
28 #include "mmc_corex.h"
29 #include "osal_io.h"
30 #include "osal_irq.h"
31 #include "osal_time.h"
32
33 #ifdef __cplusplus
34 #if __cplusplus
35 extern "C" {
36 #endif /* __cplusplus */
37 #endif /* __cplusplus */
38
39 #define REG_CTRL_SD_CLK IO_DEVICE_ADDR(0x100C0040)
40 #define REG_CTRL_SD_CMD IO_DEVICE_ADDR(0x100C0044)
41 #define REG_CTRL_SD_DATA0 IO_DEVICE_ADDR(0x100C0048)
42 #define REG_CTRL_SD_DATA1 IO_DEVICE_ADDR(0x100C004C)
43 #define REG_CTRL_SD_DATA2 IO_DEVICE_ADDR(0x100C0050)
44 #define REG_CTRL_SD_DATA3 IO_DEVICE_ADDR(0x100C0054)
45
46 #define REG_CTRL_EMMC_CLK IO_DEVICE_ADDR(0x100C0014)
47 #define REG_CTRL_EMMC_CMD IO_DEVICE_ADDR(0x100C0018)
48 #define REG_CTRL_EMMC_DATA0 IO_DEVICE_ADDR(0x100C0020)
49 #define REG_CTRL_EMMC_DATA1 IO_DEVICE_ADDR(0x100C001c)
50 #define REG_CTRL_EMMC_DATA2 IO_DEVICE_ADDR(0x100C0028)
51 #define REG_CTRL_EMMC_DATA3 IO_DEVICE_ADDR(0x100C0024)
52 #define REG_CTRL_EMMC_DATA4 IO_DEVICE_ADDR(0x100C0030)
53 #define REG_CTRL_EMMC_DATA5 IO_DEVICE_ADDR(0x100C0034)
54 #define REG_CTRL_EMMC_DATA6 IO_DEVICE_ADDR(0x100C0038)
55 #define REG_CTRL_EMMC_DATA7 IO_DEVICE_ADDR(0x100C003c)
56 #define REG_CTRL_EMMC_DS IO_DEVICE_ADDR(0x100C0058)
57 #define REG_CTRL_EMMC_RST IO_DEVICE_ADDR(0x100C005C)
58
59 #define REG_CTRL_SDIO_CLK IO_DEVICE_ADDR(0x112C0048)
60 #define REG_CTRL_SDIO_CMD IO_DEVICE_ADDR(0x112C004C)
61 #define REG_CTRL_SDIO_DATA0 IO_DEVICE_ADDR(0x112C0064)
62 #define REG_CTRL_SDIO_DATA1 IO_DEVICE_ADDR(0x112C0060)
63 #define REG_CTRL_SDIO_DATA2 IO_DEVICE_ADDR(0x112C005C)
64 #define REG_CTRL_SDIO_DATA3 IO_DEVICE_ADDR(0x112C0058)
65
66 /* macro for io_mux. */
67 #define IO_CFG_SR (1 << 10)
68 #define IO_CFG_PULL_DOWN (1 << 9)
69 #define IO_CFG_PULL_UP (1 << 8)
70 #define IO_CFG_DRV_STR_MASK (0xfU << 4)
71 #define IO_DRV_MASK 0x7f0
72
73 #define IO_DRV_STR_SEL(str) ((str) << 4)
74
75 #define IO_MUX_CLK_TYPE_EMMC 0x0
76 #define IO_MUX_CLK_TYPE_SD 0x1
77 #define IO_MUX_SHIFT(type) ((type) << 0)
78 #define IO_MUX_MASK (0xfU << 0)
79
80 #define IO_DRV_SDIO_CLK 0x3
81 #define IO_DRV_SDIO_CMD 0x6
82 #define IO_DRV_SDIO_DATA 0x6
83
84 #define IO_DRV_SD_SDHS_CLK 0x5
85 #define IO_DRV_SD_SDHS_CMD 0x7
86 #define IO_DRV_SD_SDHS_DATA 0x7
87
88 #define IO_DRV_SD_OTHER_CLK 0x7
89 #define IO_DRV_SD_OTHER_CMD IO_DRV_SD_OTHER_CLK
90 #define IO_DRV_SD_OTHER_DATA IO_DRV_SD_OTHER_CLK
91
92 #define IO_DRV_EMMC_HS400_CLK 0x3
93 #define IO_DRV_EMMC_HS400_CMD 0x4
94 #define IO_DRV_EMMC_HS400_DATA 0x4
95 #define IO_DRV_EMMC_HS400_DS 0x3
96 #define IO_DRV_EMMC_HS400_RST 0x3
97
98 #define IO_DRV_EMMC_HS200_CLK 0x2
99 #define IO_DRV_EMMC_HS200_CMD 0x4
100 #define IO_DRV_EMMC_HS200_DATA 0x4
101 #define IO_DRV_EMMC_HS200_RST 0x3
102
103 #define IO_DRV_EMMC_HS_CLK 0x4
104 #define IO_DRV_EMMC_HS_CMD 0x6
105 #define IO_DRV_EMMC_HS_DATA 0x6
106 #define IO_DRV_EMMC_HS_RST 0x3
107
108 #define IO_DRV_EMMC_OTHER_CLK 0x5
109 #define IO_DRV_EMMC_OTHER_CMD 0x6
110 #define IO_DRV_EMMC_OTHER_DATA 0x6
111 #define IO_DRV_EMMC_OTHER_RST 0x3
112
113 #define PERI_CRG125 (CRG_REG_BASE + 0x01F4)
114 #define PERI_CRG126 (CRG_REG_BASE + 0x01F8)
115 #define PERI_CRG127 (CRG_REG_BASE + 0x01FC)
116 #define PERI_CRG135 (CRG_REG_BASE + 0x021C)
117 #define PERI_CRG136 (CRG_REG_BASE + 0x0220)
118 #define PERI_CRG139 (CRG_REG_BASE + 0x022C)
119 #define PERI_SD_DRV_DLL_CTRL (CRG_REG_BASE + 0x210)
120 #define PERI_SDIO_DRV_DLL_CTRL (CRG_REG_BASE + 0x228)
121 #define PERI_SD_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x208)
122 #define PERI_SDIO_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x224)
123
124 /*
125 * PERI_CRG125/PERI_CRG139 details.
126 * [28]Clock gating configuration. 0: disabled; 1: enabled.
127 * [27]Soft reset request. 0: reset deasserted; 1: reset.
128 * [26:24]Working clock selection. 000: 100KHz; 001: 400KHz; 010: 25MHz; 011: 50MKz;
129 * 100: 90MKz(Supported only in eMMC mode); 101: 112.5MKz(Supported only in eMMC mode);
130 * 110: 150MKz(Supported only in eMMC mode); others: reserved.
131 */
132 #define SDHCI_MMC_FREQ_MASK 0x7
133 #define SDHCI_MMC_FREQ_SHIFT 24
134 #define SDHCI_CKEN (1U << 28)
135 #define SDHCI_CLK_SEL_100K 0
136 #define SDHCI_CLK_SEL_400K 1
137 #define SDHCI_CLK_SEL_25M 2
138 #define SDHCI_CLK_SEL_50M 3
139 #define SDHCI_CLK_SEL_90M 4
140 #define SDHCI_CLK_SEL_112P5M 5
141 #define SDHCI_CLK_SEL_150M 6
142 #define SDHCI_EMMC_CRG_REQ (1U << 27)
143 #define SDHCI_EMMC_CKEN (1U << 28)
144 #define SDHCI_EMMC_DLL_RST (1U << 29)
145
146 /*
147 * PERI_CRG126/PERI_CRG135 details.
148 * [4:0]Clock phase configuration for B clock debugging during edge detection. The default value is 90 degrees.
149 * 0x00: 0; 0x01: 11.25; 0x02: 22.5; ... 0x1E: 337.5; 0x1F: 348.75; others: reserved.
150 */
151 #define SDHCI_SAMPLB_DLL_CLK_MASK (0x1fU << 0)
152 #define SDHCI_SAMPLB_DLL_CLK 8
153 #define SDHCI_SAMPLB_SEL(phase) ((phase) << 0)
154
155 /*
156 * PERI_CRG127/PERI_CRG136 details.
157 * [28:24]Clock phase configuration. Default value: 180.
158 * 0x00: 0; 0x01: 11.25; 0x02: 22.5; ... 0x1E: 337.5; 0x1F: 348.75; others: reserved.
159 */
160 #define SDHCI_DRV_CLK_PHASE_SHFT 24
161 #define SDHCI_DRV_CLK_PHASE_MASK (0x1f << 24)
162 #define SDHCI_PHASE_112P5_DEGREE 10 /* 112.5 degree */
163 #define SDHCI_PHASE_258P75_DEGREE 23 /* 258.75 degree */
164 #define SDHCI_PHASE_225_DEGREE 20 /* 225 degree */
165 #define SDHCI_PHASE_180_DEGREE 16 /* 180 degree */
166
167 /*
168 * PERI_SD_DRV_DLL_CTRL/PERI_SDIO_DRV_DLL_CTRL details.
169 */
170 #define SDHCI_DRV_DLL_LOCK (1U << 15)
171
172 /*
173 * PERI_SD_SAMPL_DLL_STATUS/PERI_SDIO_SAMPL_DLL_STATUS details.
174 */
175 #define SDHCI_SAMPL_DLL_SLAVE_READY 1
176 #define SDHCI_SAMPL_DLL_SLAVE_EN (1U << 16)
177
178 #define SDHCI_MMC_FREQ_100K 100000
179 #define SDHCI_MMC_FREQ_400K 400000
180 #define SDHCI_MMC_FREQ_25M 25000000
181 #define SDHCI_MMC_FREQ_50M 50000000
182 /* only support for EMMC chip */
183 #define SDHCI_MMC_FREQ_90M 90000000
184 #define SDHCI_MMC_FREQ_112P5M 112500000
185 #define SDHCI_MMC_FREQ_150M 150000000
186
187 #define SDHCI_CMD_DATA_REQ_TIMEOUT (LOSCFG_BASE_CORE_TICK_PER_SECOND * 10) /* 30 s */
188 #define SDHCI_CMD_REQ_TIMEOUT (LOSCFG_BASE_CORE_TICK_PER_SECOND * 1) /* 1s */
189
190 /* define event lock */
191 typedef EVENT_CB_S SDHCI_EVENT;
192 #define SDHCI_EVENT_INIT(event) LOS_EventInit(event)
193 #define SDHCI_EVENT_SIGNAL(event, bit) LOS_EventWrite(event, bit)
194 #define SDHCI_EVENT_WAIT(event, bit, timeout) LOS_EventRead(event, bit, (LOS_WAITMODE_OR + LOS_WAITMODE_CLR), timeout)
195 #define SDHCI_EVENT_DELETE(event) LOS_EventDestroy(event)
196
197 /* define irq lock */
198 #define SDHCI_IRQ_LOCK(flags) do { (*(flags)) = LOS_IntLock(); } while (0)
199 #define SDHCI_IRQ_UNLOCK(flags) do { LOS_IntRestore(flags); } while (0)
200
201 #define SDHCI_SG_DMA_ADDRESS(sg) ((sg)->dma_address)
202 #ifdef CONFIG_NEED_SG_DMA_LENGTH
203 #define SDHCI_SG_DMA_LEN(sg) ((sg)->dma_length)
204 #else
205 #define SDHCI_SG_DMA_LEN(sg) ((sg)->length)
206 #endif
207
208 /*
209 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
210 */
211 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
212 #define SDHCI_DEFAULT_BOUNDARY 19
213 #define SDHCI_DEFAULT_BOUNDARY_ARG (SDHCI_DEFAULT_BOUNDARY - 12)
214
215 enum SdhciDmaDataDirection {
216 DMA_BIDIRECTIONAL = 0,
217 DMA_TO_DEVICE = 1,
218 DMA_FROM_DEVICE = 2,
219 DMA_NONE = 3,
220 };
221
222 enum SdhciHostRegister {
223 SDMASA_R = 0x0000,
224 BLOCKSIZE_R = 0x0004,
225 BLOCKCOUNT_R = 0x0006,
226 ARGUMENT_R = 0x0008,
227 XFER_MODE_R = 0x000c,
228 CMD_R = 0x000e,
229 RESP01_R = 0x0010,
230 RESP23_R = 0x0014,
231 RESP45_R = 0x0018,
232 RESP67_R = 0x001c,
233 BUF_DATA_R = 0x0020,
234 PSTATE_R = 0x0024,
235 HOST_CTRL1_R = 0x0028,
236 PWR_CTRL_R = 0x0029,
237 BLOCK_GAP_CTRL_R = 0x002a,
238 WUP_CTRL_R = 0x002b,
239 CLK_CTRL_R = 0x002c,
240 TOUT_CTRL_R = 0x002e,
241 SW_RST_R = 0x002f,
242 NORMAL_INT_STAT_R = 0x0030,
243 ERROR_INT_STAT_R = 0x0032,
244 NORMAL_INT_STAT_EN_R = 0x0034,
245 ERROR_INT_STAT_EN_R = 0x0036,
246 NORMAL_INT_SIGNAL_EN_R = 0x0038,
247 ERROR_INT_SIGNAL_EN_R = 0x003a,
248 AUTO_CMD_STAT_R = 0x003c,
249 HOST_CTRL2_R = 0x003e,
250 CAPABILITIES1_R = 0x0040,
251 CAPABILITIES2_R = 0x0044,
252 CURR_CAPBILITIES1_R = 0x0048,
253 ADMA_ERR_STAT_R = 0x0054,
254 ADMA_SA_LOW_R = 0x0058,
255 ADMA_SA_HIGH_R = 0x005c,
256 ADMA_ID_LOW_R = 0x0078,
257 ADMA_ID_HIGH_R = 0x007c,
258 SLOT_INT_STATUS_R = 0x00FC,
259 HOST_VERSION_R = 0x00FE,
260 MSHC_VER_ID_R = 0x0500,
261 MSHC_VER_TYPE_R = 0x0504,
262 MSHC_CTRL_R = 0x0508,
263 MBIU_CTRL_R = 0x0510,
264 EMMC_CTRL_R = 0x052c,
265 BOOT_CTRL_R = 0x052e,
266 EMMC_HW_RESET_R = 0x0534,
267 AT_CTRL_R = 0x0540,
268 AT_STAT_R = 0x0544,
269 MULTI_CYCLE_R = 0x054c
270 };
271
272 /*
273 * SDMASA_R(0x0000) details.
274 * [31:0]Whether to use the built-in DMA to transfer data.
275 * If Host Version Enable is set to 0, it indicates the SDMA system address.
276 * If Host Version Enable is set to 1, it indicates the block count. 1 indicates a block.
277 */
278 #define SDHCI_DMA_ADDRESS 0x00
279 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
280
281 /*
282 * BLOCKSIZE_R(0x0004) details.
283 * [14:12]Boundary value of an SDMA data block. 000: 4K bytes; 001: 8K bytes; ... 111: 512K bytes.
284 * [11:0]Transfer block zise. 0x800: 2048bytes.
285 */
286 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
287
288 /*
289 * XFER_MODE_R(0x000c) details.
290 * [15:9]reserved.
291 * [8]Disable the response interrupt. 0: enable; 1: disable.
292 * [7]Response error check enable. 0: disable; 1: enable.
293 * [6]Response R1/R5 Type. 0: R1; 1: R5.
294 * [5]Multiple/single block select. 0: single block; 1: multiple block.
295 * [4]Data transfer direction. 0: Controller-to-card; 1: card-to-Controller.
296 * [3:2]Auto Command Enable. 00: close; 01: Auto CMD12 Enable; 10: Auto CMD23 Enable; 11: Auto CMD Auto Select.(sdio 00)
297 * [1]Block count Enable. 0: disable; 1: enable.
298 * [0]DMA Enable. 0: No data is transmitted or non-DMA data is transmitted; 1: DMA data transfer.
299 */
300 #define SDHCI_TRNS_DMA (1 << 0)
301 #define SDHCI_TRNS_BLK_CNT_EN (1 << 1)
302 #define SDHCI_TRNS_AUTO_CMD12 (1 << 2)
303 #define SDHCI_TRNS_AUTO_CMD23 (1 << 3)
304 #define SDHCI_TRNS_READ (1 << 4)
305 #define SDHCI_TRNS_MULTI (1 << 5)
306
307 /*
308 * CMD_R(0x000e) details.
309 * [15:14]reserved.
310 * [13:8]cmd index.
311 * [7:6]cmd type. 00: Normal cmd; 01: Suspend cmd; 10: Resume cmd; 11: Abort cmd.
312 * [5]Whether data is being transmitted. 0: No data is transmitted. 1: Data is being transmitted.
313 * [4]Command ID check enable. 0: disable; 1: enable.
314 * [3]Command CRC check enable. 0: disable; 1: enable.
315 * [2]Subcommand ID. 0: Main; 1: Sub Command.
316 * [1:0]Response type. 00: no response; 01: response Length 136; 10: response length 48; 11: response length 48 check.
317 */
318 #define SDHCI_CMD_CRC_CHECK_ENABLE 0x08
319 #define SDHCI_CMD_INDEX_CHECK_ENABLE 0x10
320 #define SDHCI_CMD_DATA_TX 0x20
321
322 #define SDHCI_CMD_NONE_RESP 0x00
323 #define SDHCI_CMD_LONG_RESP 0x01
324 #define SDHCI_CMD_SHORT_RESP 0x02
325 #define SDHCI_CMD_SHORT_RESP_BUSY 0x03
326
327 #define SDHCI_GEN_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
328 #define SDHCI_PARSE_CMD(c) ((c >> 8) & 0x3f)
329
330 /*
331 * PSTATE_R(0x0024) details.
332 * [31:28]reserved.
333 * [27]Command sending error status. 0: No error occurs in the sent command. 1: The command cannot be sent.
334 * [26:25]reserved.
335 * [24]CMD pin status. 0: The cmd pin is at low level. 1: The cmd pin is at high level.
336 * [23:20]Data[3:0] pin status, meaning of each bit. 0: low level; 1: high level.
337 * [18]Card_detect_n pin status. 0: low level; 1: high level.
338 * [11]Buffer read enable. 0 : disable; 1: enable.
339 * [10]Buffer write enable. 0 : disable; 1: enable.
340 * [9]Read transfer valid. 0: idle; 1: Data is being read.
341 * [8]Write transfer valid. 0: idle; 1: Data is being written.
342 * [7:4]Data[7:4] pin status, meaning of each bit. 0: low level; 1: high level.
343 * [3]reserved.
344 * [2]The data line is valid. 0: idle; 1: Data is being transmitted.
345 * [1]The command with data is valid. 0: idle state, Commands with data can be sent.
346 * 1: The data line is being transferred or the read operation is valid.
347 * [0]The command line is valid. 0: idle state. The controller can send commands.
348 * 1: busy. The controller cannot send commands.
349 */
350 #define SDHCI_CMD_INVALID 0x00000001
351 #define SDHCI_DATA_INVALID 0x00000002
352 #define SDHCI_CARD_PRESENT 0x00010000
353 #define SDHCI_WRITE_PROTECT 0x00080000
354 #define SDHCI_DATA_0_LEVEL_MASK 0x00100000
355
356 /*
357 * HOST_CTRL1_R(0x0028) details.
358 * [7]Card detection signal select. 0: card detection signal card_detect_n (common use); 1: card detection test level.
359 * [6]Card detection test level. 0: no card; 1: a card is inserted.
360 * [5]reserved.
361 * [4:3]DMA select. When Host Version 4 Enable in HOST_CTRL2_R is 1: 00: SDMA; 01: ADMA1; 10: ADMA2;
362 * 11: ADMA2 or ADMA3. When Host Version 4 Enable in HOST_CTRL2_R is 0: 00: SDMA; 01: reserved;
363 * 10: 32-bit address ADMA2; 11: 64-bit address ADMA2.
364 * [2]High-speed enable. 0: Normal Speed; 1: High Speed.
365 * [1]Bit width of the data transfer. 0: 1bit; 1: 4bit.
366 * [0]reserved.
367 */
368 #define SDHCI_CTRL_4_BIT_BUS 0x02
369 #define SDHCI_CTRL_HIGH_SPEED 0x04
370 #define SDHCI_CTRL_DMA_ENABLE_MASK 0x18
371 #define SDHCI_CTRL_SDMA_ENABLE 0x00
372 #define SDHCI_CTRL_ADMA1_ENABLE 0x08
373 #define SDHCI_CTRL_ADMA32_ENABLE 0x10
374 #define SDHCI_CTRL_ADMA64_ENABLE 0x18
375 #define SDHCI_CTRL_8_BIT_BUS 0x20
376
377 /*
378 * PWR_CTRL_R(0x0029) details.
379 * [0]VDD2 Power enable. 0: power off; 1: power on.
380 */
381 #define SDHCI_POWER_ON 0x01
382 #define SDHCI_POWER_180 0x0A
383 #define SDHCI_POWER_300 0x0C
384 #define SDHCI_POWER_330 0x0E
385
386 /*
387 * CLK_CTRL_R(0x002c) details.
388 * [15:4]reserved.
389 * [3]PLL enable. 0: The PLL is in low power mode. 1: enabled.
390 * [2]SD/eMMC clock enable. 0: disabled; 1: enabled.
391 * [1]Internal clock status. 0: unstable; 1: stable.
392 * [0]Internal clock enable. 0: disabled; 1: enabled.
393 */
394 #define SDHCI_CLK_CTRL_PLL_EN (1 << 3)
395 #define SDHCI_CLK_CTRL_CLK_EN (1 << 2)
396 #define SDHCI_CLK_CTRL_INT_STABLE (1 << 1)
397 #define SDHCI_CLK_CTRL_INT_CLK_EN (1 << 0)
398
399 /*
400 * TOUT_CTRL_R(0x002e) details.
401 * [3:0]Data timeout count. 0x0: TMCLK x 2^13; 0xe: TMCLK x 2^27; others: reserved.
402 */
403 #define SDHCI_DEFINE_TIMEOUT 0xE
404
405 /*
406 * SW_RST_R(0x002f) details.
407 * [7:3]reserved.
408 * [2]Data line soft reset request. 0: not reset; 1: reset.
409 * [1]Command line soft reset request. 0: not reset; 1: reset.
410 * [0]Soft reset request of the controller. 0: not reset; 1: reset.
411 */
412 #define SDHCI_RESET_ALL 0x01
413 #define SDHCI_RESET_CMD 0x02
414 #define SDHCI_RESET_DATA 0x04
415
416 /*
417 * NORMAL_INT_STAT_R(0x0030) details.
418 * [15]Summary error interrupt status. [14]reserved. [13]TX event interrupt status.
419 * [12]Retuning event interrupt status. [11]INT_C interrupt status. [10]INT_B interrupt status.
420 * [9]INT_A interrupt status. [8]Card interrupt status. [7]Card removal interrupt status.
421 * [6]Card insertion interrupt status. [5]Buffer read ready interrupt status. [4]Buffer write ready interrupt status.
422 * [3]DMA interrupt status. [2]Block gap event interrupt status due to a stop request.
423 * [1]Read/write transfer completion interrupt status. [0]Command completion interrupt status.
424 */
425 #define SDHCI_INTERRUPT_RESPONSE 0x00000001
426 #define SDHCI_INTERRUPT_DATA_END 0x00000002
427 #define SDHCI_INTERRUPT_BLK_GAP 0x00000004
428 #define SDHCI_INTERRUPT_DMA_END 0x00000008
429 #define SDHCI_INTERRUPT_SPACE_AVAIL 0x00000010
430 #define SDHCI_INTERRUPT_DATA_AVAIL 0x00000020
431 #define SDHCI_INTERRUPT_CARD_INSERT 0x00000040
432 #define SDHCI_INTERRUPT_CARD_REMOVE 0x00000080
433 #define SDHCI_INTERRUPT_CARD_INT 0x00000100
434 #define SDHCI_INTERRUPT_ERROR 0x00008000
435
436 /*
437 * NORMAL_INT_SIGNAL_EN_R(0x0038) details.
438 */
439 #define SDHCI_INTERRUPT_TIMEOUT 0x00010000
440 #define SDHCI_INTERRUPT_CRC 0x00020000
441 #define SDHCI_INTERRUPT_END_BIT 0x00040000
442 #define SDHCI_INTERRUPT_INDEX 0x00080000
443 #define SDHCI_INTERRUPT_DATA_TIMEOUT 0x00100000
444 #define SDHCI_INTERRUPT_DATA_CRC 0x00200000
445 #define SDHCI_INTERRUPT_DATA_END_BIT 0x00400000
446 #define SDHCI_INTERRUPT_BUS_POWER 0x00800000
447 #define SDHCI_INTERRUPT_AUTO_CMD_ERR 0x01000000
448 #define SDHCI_INTERRUPT_ADMA_ERROR 0x02000000
449
450 #define SDHCI_INT_CMD_MASK (SDHCI_INTERRUPT_RESPONSE | SDHCI_INTERRUPT_TIMEOUT | SDHCI_INTERRUPT_CRC | \
451 SDHCI_INTERRUPT_END_BIT | SDHCI_INTERRUPT_INDEX | SDHCI_INTERRUPT_AUTO_CMD_ERR)
452
453 #define SDHCI_INT_DATA_MASK (SDHCI_INTERRUPT_DATA_END | SDHCI_INTERRUPT_DMA_END | SDHCI_INTERRUPT_DATA_AVAIL | \
454 SDHCI_INTERRUPT_SPACE_AVAIL | SDHCI_INTERRUPT_DATA_TIMEOUT | SDHCI_INTERRUPT_DATA_CRC | \
455 SDHCI_INTERRUPT_DATA_END_BIT | SDHCI_INTERRUPT_ADMA_ERROR | SDHCI_INTERRUPT_BLK_GAP)
456
457 /*
458 * HOST_CTRL2_R(0x003e) details.
459 * [9:8]reserved; [3]reserved.
460 * [15]Automatic selection enable of the preset value. 0: disabled, 1: enabled.
461 * [14]Async interrupt enable. 0: disabled; 1: enabled.
462 * [13]Bus 64-bit address enable. 0: disabled; 1: enabled.
463 * [12]Controller version 4 enable. 0: 3.0; 1: 4.0.
464 * [11]CMD23 enable. 0: disabled; 1: enabled.
465 * [10]ADMA2 length. 0:16-bit data length; 1:26-bit data length.
466 * [7]Sample clock select. 0: Select the fixed clock to collect data. 1: tuned clock.
467 * [6]Run the tuning command. The value is automatically cleared after the tuning operation is complete.
468 * 0: Tuning is not performed or tuning is complete. 1: tuning.
469 * [5:4]Drive capability select. 00: typeB; 01: typeA; 10: typeC; 11: typeD.
470 * [2:0]emmc mode. 000: Legacy; 001: High Speed SDR; 010: HS200; others: reserved.
471 */
472 #define SDHCI_UHS_MASK 0x0007
473 #define SDHCI_UHS_SDR12 0x0000
474 #define SDHCI_UHS_SDR25 0x0001
475 #define SDHCI_UHS_SDR50 0x0002
476 #define SDHCI_UHS_SDR104 0x0003
477 #define SDHCI_UHS_DDR50 0x0004
478 #define SDHCI_HS_SDR200 0x0005 /* reserved value in SDIO spec */
479 #define SDHCI_HS400 0x0007
480 #define SDHCI_VDD_180 0x0008
481 #define SDHCI_DRV_TYPE_MASK 0x0030
482 #define SDHCI_DRV_TYPE_B 0x0000
483 #define SDHCI_DRV_TYPE_A 0x0010
484 #define SDHCI_DRV_TYPE_C 0x0020
485 #define SDHCI_DRV_TYPE_D 0x0030
486 #define SDHCI_EXEC_TUNING 0x0040
487 #define SDHCI_TUNED_CLK 0x0080
488 #define SDHCI_ASYNC_INT_ENABLE 0x4000
489 #define SDHCI_PRESET_VAL_ENABLE 0x8000
490
491 /*
492 * CAPABILITIES1_R(0x0040) details.
493 * [31:30]Slot type. 00: Removable card slot; 01: Embedded Slot;
494 * 10: Shared bus slot (used in SD mode); 11:UHS2 (not supported currently).
495 * [29]Whether the sync interrupt is supported. 0: not supported; 1: supported.
496 * [28]The 64-bit system address is used for V3. 0: not supported; 1: supported.
497 * [27]The 64-bit system address is used for V4. 0: not supported; 1: supported.
498 * [26]The voltage is 1.8 V. 0: not supported; 1: supported.
499 * [25]The voltage is 3.0 V. 0: not supported; 1: supported.
500 * [24]The voltage is 3.3 V. 0: not supported; 1: supported.
501 * [23]Suspending and Resuming Support. 0: not supported; 1: supported.
502 * [22]SDMA Support. 0: not supported; 1: supported.
503 * [21]Indicates whether to support high speed. 0: not supported; 1: supported.
504 * [19]Indicates whether to support ADMA2. 0: not supported; 1: supported.
505 * [18]Whether the 8-bit embedded component is supported. 0: not supported; 1: supported.
506 * [17:16]Maximum block length. 0x0: 512Byte; 0x1: 1024Byte; 0x2: 2048Byte; 0x3: reserved.
507 * [15:8]Basic frequency of the clock. 0x0: 1MHz; 0x3F: 63MHz; 0x40~0xFF: not supported.
508 * [7]Timeout clock unit. 0: KHz; 1: MHz.
509 * [5:0]Timeout interval. 0x1: 1KHz/1MHz; 0x2: 2KHz/2MHz; ... 0x3F: 63KHz/63MHz
510 */
511 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
512 #define SDHCI_CLK_BASE_MASK 0x00003F00
513 #define SDHCI_BASIC_FREQ_OF_CLK_MASK 0x0000FF00
514 #define SDHCI_BASIC_FREQ_OF_CLK_SHIFT 8
515 #define SDHCI_MAX_BLOCK_SIZE_MASK 0x00030000
516 #define SDHCI_MAX_BLOCK_SIZE_SHIFT 16
517 #define SDHCI_SUPPORT_8BIT 0x00040000
518 #define SDHCI_SUPPORT_ADMA2 0x00080000
519 #define SDHCI_SUPPORT_HISPD 0x00200000
520 #define SDHCI_SUPPORT_SDMA 0x00400000
521 #define SDHCI_SUPPORT_VDD_330 0x01000000
522 #define SDHCI_SUPPORT_VDD_300 0x02000000
523 #define SDHCI_SUPPORT_VDD_180 0x04000000
524 #define SDHCI_SUPPORT_64BIT 0x10000000
525 #define SDHCI_SUPPORT_ASYNC_INT 0x20000000
526
527 /*
528 * CAPABILITIES2_R(0x0044) details.
529 * [28]Whether the 1.8V VDDR is supported. 0: not supported; 1: supported.
530 * [27]Whether the ADMA3 is supported. 0: not supported; 1: supported.
531 * [15:14]Retuning mode. 00: MODE1, Timer; 01: MODE2, Timer and ReTuning request;
532 * 10: MODE3, Auto retuning Timer and ReTuning request; 11: reserved.
533 * [13]SDR50 uses Tuning. 0: not use; 1: use.
534 * [11:8]Retuning count. 0x1: 1s; 0x3: 4s; others: reserved.
535 * [6]Support TYPED. 0: not supported; 1: supported.
536 * [5]Support TYPEC. 0: not supported; 1: supported.
537 * [4]Support TYPEA. 0: not supported; 1: supported.
538 * [3]Support UHS2. 0: not supported; 1: supported.
539 * [2]Support DDR50. 0: not supported; 1: supported.
540 * [1]Support SDR104. 0: not supported; 1: supported.
541 * [0]Support SDR50. 0: not supported; 1: supported.
542 */
543 #define SDHCI_SUPPORT_SDR50 0x00000001
544 #define SDHCI_SUPPORT_SDR104 0x00000002
545 #define SDHCI_SUPPORT_DDR50 0x00000004
546 #define SDHCI_SUPPORT_DRIVER_TYPE_A 0x00000010
547 #define SDHCI_SUPPORT_DRIVER_TYPE_C 0x00000020
548 #define SDHCI_SUPPORT_DRIVER_TYPE_D 0x00000040
549 #define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
550 #define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
551 #define SDHCI_USE_SDR50_TUNING 0x00002000
552 #define SDHCI_RETUNING_MODE_MASK 0x0000C000
553 #define SDHCI_RETUNING_MODE_SHIFT 14
554 #define SDHCI_CLK_MUL_MASK 0x00FF0000
555 #define SDHCI_CLK_MUL_SHIFT 16
556 #define SDHCI_SUPPORT_ADMA3 0x8000000
557
558 /*
559 * HOST_VERSION_R(0x00FE) details.
560 */
561 #define SDHCI_HOST_SPEC_VER_MASK 0x00FF
562 #define SDHCI_HOST_SPEC_100 0
563 #define SDHCI_HOST_SPEC_200 1
564 #define SDHCI_HOST_SPEC_300 2
565 #define SDHCI_HOST_SPEC_400 3
566 #define SDHCI_HOST_SPEC_410 4
567 #define SDHCI_HOST_SPEC_420 5
568
569 /*
570 * EMMC_CTRL_R(0x0508) details.
571 */
572 #define SDHC_CMD_CONFLIT_CHECK 0x01
573
574 /*
575 * MBIU_CTRL_R(0x0510) details.
576 * [3]16 burst enable. 0: disable 16 burst; 1: enable 16 burst.
577 * [2]8 burst enable. 0: disable 8 burst; 1: enable 8 burst.
578 * [1]4 burst enable. 0: disable 4 burst; 1: enable 4 burst.
579 * [0]Burst configuration validation enable.
580 * 0: Generate fixed bursts by configuring gm_enburst4, gm_enburst8, gm_enburst16;
581 * 1: Generate bursts based on the actual data length.
582 */
583 #define SDHCI_GM_WR_OSRC_LMT_MASK (0x7 << 24)
584 #define SDHCI_GM_RD_OSRC_LMT_MASK (0x7 << 16)
585 #define SDHCI_GM_WR_OSRC_LMT_VAL (7 << 24)
586 #define SDHCI_GM_RD_OSRC_LMT_VAL (7 << 16)
587 #define SDHCI_UNDEFL_INCR_EN 0x1
588
589 /*
590 * EMMC_CTRL_R(0x052c) details.
591 * [15:10]reserved; [8:2]reserved.
592 * [9]Algorithm for sorting tasks. 0: Tasks with a higher priority are executed first.
593 * Tasks with the same priority are executed first in first. 1: first come first execute.
594 * [1]Disable the CRC check. 0: Data CRC check is enabled. 1: The CRC check is disabled.
595 * [0]Type of the connected card. 0: non-eMMC card; 1: eMMC card.
596 */
597 #define SDHCI_EMMC_CTRL_EMMC (1 << 0)
598 #define SDHCI_EMMC_CTRL_ENH_STROBE_EN (1 << 8)
599
600 /*
601 * AT_CTRL_R(0x0540) details.
602 * [4]Software configuration tuning enable. 0: disable; 1: enable.
603 */
604 #define SDHCI_SW_TUNING_EN 0x00000010
605
606 /*
607 * AT_STAT_R(0x0544) details.
608 * [7:0]Phase value configured by software.
609 */
610 #define SDHCI_CENTER_PH_CODE_MASK 0x000000ff
611 #define SDHCI_SAMPLE_PHASE 4
612 #define SDHCI_PHASE_SCALE 32
613 #define SDHCI_PHASE_SCALE_TIMES 4
614
615 /*
616 * MULTI_CYCLE_R(0x054C) details.
617 */
618 #define SDHCI_FOUND_EDGE (0x1 << 11)
619 #define SDHCI_EDGE_DETECT_EN (0x1 << 8)
620 #define SDHCI_DOUT_EN_F_EDGE (0x1 << 6)
621 #define SDHCI_DATA_DLY_EN (0x1 << 3)
622 #define SDHCI_CMD_DLY_EN (0x1 << 2)
623
624 /*
625 * End of controller registers.
626 */
627 #define ADMA2_END 0x2
628
629 #define SDHCI_USE_SDMA (1 << 0)
630 #define SDHCI_USE_ADMA (1 << 1)
631 #define SDHCI_REQ_USE_DMA (1 << 2)
632 #define SDHCI_DEVICE_DEAD (1 << 3)
633 #define SDHCI_SDR50_NEEDS_TUNING (1 << 4)
634 #define SDHCI_NEEDS_RETUNING (1 << 5)
635 #define SDHCI_AUTO_CMD12 (1 << 6)
636 #define SDHCI_AUTO_CMD23 (1 << 7)
637 #define SDHCI_PV_ENABLED (1 << 8)
638 #define SDHCI_SDIO_IRQ_ENABLED (1 << 9)
639 #define SDHCI_SDR104_NEEDS_TUNING (1 << 10)
640 #define SDHCI_USING_RETUNING_TIMER (1 << 11)
641 #define SDHCI_USE_64BIT_ADMA (1 << 12)
642 #define SDHCI_HOST_IRQ_STATUS (1 << 13)
643
644 #define SDHCI_ADMA_MAX_DESC 128
645 #define SDHCI_ADMA_DEF_SIZE ((SDHCI_ADMA_MAX_DESC * 2 + 1) * 4)
646 #define SDHCI_ADMA_LINE_SIZE 8
647 #define SDHCI_ADMA_64BIT_LINE_SIZE 12
648 #define SDHCI_MAX_DIV_SPEC_200 256
649 #define SDHCI_MAX_DIV_SPEC_300 2046
650
651 union SdhciHostQuirks {
652 uint32_t quirksData;
653 struct QuirksBitData {
654 uint32_t brokenCardDetection : 1;
655 uint32_t forceSWDetect : 1; /* custom requirement: use the SD protocol to detect rather then the interrupt. */
656 uint32_t invertedWriteProtect : 1;
657 uint32_t noEndattrInNopdesc : 1;
658 uint32_t reserved : 28;
659 }bits;
660 };
661
662 #define SDHCI_PEND_REQUEST_DONE (1 << 0)
663 #define SDHCI_PEND_ACCIDENT (1 << 1)
664 struct SdhciHost {
665 struct MmcCntlr *mmc;
666 struct MmcCmd *cmd;
667 void *base;
668 uint32_t irqNum;
669 uint32_t irqEnable;
670 uint32_t hostId;
671 union SdhciHostQuirks quirks;
672 uint32_t flags;
673 uint16_t version;
674 uint32_t maxClk;
675 uint32_t clkMul;
676 uint32_t clock;
677 uint8_t pwr;
678 bool presetEnabled;
679 struct OsalMutex mutex;
680 SDHCI_EVENT sdhciEvent;
681 bool waitForEvent;
682 uint8_t *alignedBuff;
683 uint32_t buffLen;
684 struct scatterlist dmaSg;
685 struct scatterlist *sg;
686 uint32_t dmaSgCount;
687 char *admaDesc;
688 uint32_t admaDescSize;
689 uint32_t admaDescLineSize;
690 uint32_t admaMaxDesc;
691 uint32_t tuningPhase;
692 };
693
SdhciWritel(struct SdhciHost * host,uint32_t val,int reg)694 static inline void SdhciWritel(struct SdhciHost *host, uint32_t val, int reg)
695 {
696 OSAL_WRITEL(val, (uintptr_t)host->base + reg);
697 }
698
SdhciWritew(struct SdhciHost * host,uint16_t val,int reg)699 static inline void SdhciWritew(struct SdhciHost *host, uint16_t val, int reg)
700 {
701 OSAL_WRITEW(val, (uintptr_t)host->base + reg);
702 }
703
SdhciWriteb(struct SdhciHost * host,uint8_t val,int reg)704 static inline void SdhciWriteb(struct SdhciHost *host, uint8_t val, int reg)
705 {
706 OSAL_WRITEB(val, (uintptr_t)host->base + reg);
707 }
708
SdhciReadl(struct SdhciHost * host,int reg)709 static inline uint32_t SdhciReadl(struct SdhciHost *host, int reg)
710 {
711 return OSAL_READL((uintptr_t)host->base + reg);
712 }
713
SdhciReadw(struct SdhciHost * host,int reg)714 static inline uint16_t SdhciReadw(struct SdhciHost *host, int reg)
715 {
716 return OSAL_READW((uintptr_t)host->base + reg);
717 }
718
SdhciReadb(struct SdhciHost * host,int reg)719 static inline uint8_t SdhciReadb(struct SdhciHost *host, int reg)
720 {
721 return OSAL_READB((uintptr_t)host->base + reg);
722 }
723
724 #ifdef __cplusplus
725 #if __cplusplus
726 }
727 #endif /* __cplusplus */
728 #endif /* __cplusplus */
729
730 #endif /* SDHCI_H */
731