1 /*
2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include "hdf_log.h"
17 #include "hifmc100.h"
18 #include "mtd_core.h"
19 #include "mtd_spi_nor.h"
20
21 #define HDF_LOG_TAG mx25l_c
22
HifmcCntlrSpinorQeEnableMx25l(struct SpiFlash * spi)23 int32_t HifmcCntlrSpinorQeEnableMx25l(struct SpiFlash *spi)
24 {
25 uint8_t status;
26 unsigned long reg;
27 int enable;
28 struct HifmcCntlr *cntlr = NULL;
29
30 if (spi == NULL || spi->mtd.cntlr == NULL) {
31 return HDF_ERR_INVALID_OBJECT;
32 }
33 cntlr = spi->mtd.cntlr;
34
35 enable = ((spi->writeCfg.ifType >= MTD_SPI_IF_QUAD) ||
36 (spi->readCfg.ifType >= MTD_SPI_IF_QUAD)) ? 1 : 0;
37
38 status = HifmcCntlrReadDevReg(cntlr, spi, MTD_SPI_CMD_RDSR);
39 if ((!!(status & MTD_SPI_SR_QE_MASK)) == enable) {
40 HDF_LOGI("%s: qe status:%d, qe enable:%d", __func__, status, enable);
41 return HDF_SUCCESS;
42 }
43
44 SpiFlashWriteEnable(spi);
45
46 if (enable == 1) {
47 status |= MTD_SPI_SR_QE_MASK;
48 } else {
49 status &= ~(MTD_SPI_SR_QE_MASK);
50 }
51 OSAL_WRITEB(status, cntlr->memBase);
52
53 reg = HIFMC_CMD_CMD1(MTD_SPI_CMD_WRSR);
54 HIFMC_REG_WRITE(cntlr, reg, HIFMC_CMD_REG_OFF);
55
56 reg = HIFMC_OP_CFG_FM_CS(spi->cs);
57 HIFMC_REG_WRITE(cntlr, reg, HIFMC_OP_CFG_REG_OFF);
58
59 reg = HIFMC_DATA_NUM_CNT(1);
60 HIFMC_REG_WRITE(cntlr, reg, HIFMC_DATA_NUM_REG_OFF);
61
62 reg = HIFMC_OP_CMD1_EN(1) |
63 HIFMC_OP_WRITE_DATA_EN(1) |
64 HIFMC_OP_REG_OP_START;
65 HIFMC_REG_WRITE(cntlr, reg, HIFMC_OP_REG_OFF);
66
67 SpiFlashWaitReady(spi);
68
69 status = HifmcCntlrReadDevReg(cntlr, spi, MTD_SPI_CMD_RDSR);
70 if ((!!(status & MTD_SPI_SR_QE_MASK)) == enable) {
71 HDF_LOGI("%s: qe enable:%d set success", __func__, enable);
72 return HDF_SUCCESS;
73 } else {
74 HDF_LOGE("%s: qe enable:%d set failed", __func__, enable);
75 return HDF_FAILURE;
76 }
77 return HDF_SUCCESS;
78 }
79