1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef PLATFORM_RTC_HI35XX_H 17 #define PLATFORM_RTC_HI35XX_H 18 19 #include "rtc_core.h" 20 21 #ifdef __cplusplus 22 #if __cplusplus 23 extern "C" { 24 #endif /* __cplusplus */ 25 #endif /* __cplusplus */ 26 27 enum RtcErrorType { 28 RTC_ERROR_READ_FAIL = 1, 29 RTC_ERROR_WRITE_FAIL = 2, 30 RTC_ERROR_READ_BUSY = 3, 31 RTC_ERROR_WRITE_BUSY = 4, 32 RTC_ERROR_NULL = 5, 33 }; 34 35 enum RtcFeatureSupportType { 36 RTC_FEATURE_NO_SUPPORT = 0, 37 RTC_FEATURE_SUPPORT = 1, 38 }; 39 40 /* define the union SPI_RW */ 41 union RtcSpiConfig { 42 struct { 43 uint32_t spiWriteData : 8; /* [7:0] */ 44 uint32_t spiReadData : 8; /* [15:8] */ 45 uint32_t spiAddr : 7; /* [22:16] */ 46 uint32_t spiOperateType : 1; /* [23] */ 47 uint32_t spiStart : 1; /* [24] */ 48 uint32_t reserved : 6; /* [30:25] */ 49 uint32_t spiBusy : 1; /* [31] */ 50 } bits; 51 uint32_t data; /* define an unsigned int member */ 52 }; 53 54 struct RtcLockAddr { 55 uint8_t lock0Addr; 56 uint8_t lock1Addr; 57 uint8_t lock2Addr; 58 uint8_t lock3Addr; 59 }; 60 61 struct RtcConfigInfo { 62 uint32_t spiBaseAddr; 63 volatile void *remapBaseAddr; 64 uint16_t regAddrLength; 65 uint8_t supportAnaCtrl; 66 uint8_t supportLock; 67 uint8_t irq; 68 uint8_t alarmIndex; 69 uint8_t anaCtrlAddr; 70 struct RtcLockAddr lockAddr; 71 RtcAlarmCallback cb; 72 struct OsalMutex mutex; 73 }; 74 struct RtcTimeReg { 75 uint8_t millisecondAddr; 76 uint8_t secondAddr; 77 uint8_t minuteAddr; 78 uint8_t hourAddr; 79 uint8_t dayLowAddr; 80 uint8_t dayHighAddr; 81 }; 82 83 #define RTC_SPI_WRITE 0 84 #define RTC_SPI_READ 1 85 86 /* RTC control over SPI */ 87 #define RTC_SPI_CLK_DIV(base) ((base) + 0x000) 88 #define RTC_SPI_RW(base) ((base) + 0x004) 89 90 /* RTC reg */ 91 #define RTC_10MS_COUN 0x00 92 #define RTC_S_COUNT 0x01 93 #define RTC_M_COUNT 0x02 94 #define RTC_H_COUNT 0x03 95 #define RTC_D_COUNT_L 0x04 96 #define RTC_D_COUNT_H 0x05 97 #define RTC_MR_10MS 0x06 98 #define RTC_MR_S 0x07 99 #define RTC_MR_M 0x08 100 #define RTC_MR_H 0x09 101 #define RTC_MR_D_L 0x0A 102 #define RTC_MR_D_H 0x0B 103 #define RTC_LR_10MS 0x0C 104 #define RTC_LR_S 0x0D 105 #define RTC_LR_M 0x0E 106 #define RTC_LR_H 0x0F 107 #define RTC_LR_D_L 0x10 108 #define RTC_LR_D_H 0x11 109 #define RTC_LORD 0x12 110 #define RTC_MSC 0x13 111 #define RTC_INT_CLR 0x14 112 #define RTC_INT 0x15 113 #define RTC_INT_RAW 0x16 114 #define RTC_CLK 0x17 115 #define RTC_POR_N 0x18 116 #define RTC_SAR_CTRL 0x1A 117 #define RTC_FREQ_H 0x51 118 #define RTC_FREQ_L 0x52 119 120 #define RTC_USER_REG1 0x53 121 #define RTC_USER_REG2 0x54 122 #define RTC_USER_REG3 0x55 123 #define RTC_USER_REG4 0x56 124 #define RTC_USER_REG5 0x57 125 #define RTC_USER_REG6 0x58 126 #define RTC_USER_REG7 0x59 127 #define RTC_USER_REG8 0x5A 128 129 /* RTC reg value */ 130 #define RTC_CLK_DIV_VALUE 0X4 131 #define RTC_MSC_ENABLE 0x4 /* 0x4:[2] bit,irq enable */ 132 #define RTC_UV_CTRL_ENABLE 0x20 /* 0x20:[5] bit,low-power detect */ 133 #define RTC_ANA_CTRL_ENABLE 0x02 /* 0x20:[2],ana ctl */ 134 #define RTC_ANA_CTRL_ORDER 0x03 /* 0x03:ana ctl order */ 135 #define RTC_LOCK_ORDER0 0xCD /* 0xCD:ctl order */ 136 #define RTC_LOCK_ORDER1 0xAB /* 0xAB:ctl order */ 137 #define RTC_LOCK_ORDER2 0x5A /* 0x5A:ctl order */ 138 #define FREQ_H_DEFAULT 0x8 139 #define FREQ_L_DEFAULT 0x1B 140 #define RTC_CLK_OUT_SEL 0x01 141 #define RTC_INT_CLR_MASK 0x1 142 #define RTC_INT_RAW_MASK 0x2 143 #define RTC_MSC_TIME_MASK 0x1 144 #define RTC_INT_MASK 0x1 145 #define RTC_INT_UV_MASK 0x2 146 #define RTC_LOCK_BYPASS_MASK 0x4 147 #define RTC_LOCK_MASK 0x2 148 #define RTC_LOAD_MASK 0x1 149 150 #define RETRY_CNT 500 151 #define RTC_WAIT_TIME 10 152 #define FREQ_MAX_VAL 3277000 153 #define FREQ_MIN_VAL 3276000 154 #define FREQ_ROUND_OFF_NUMBER 100 /* freq * 100 round-ff number */ 155 #define REG_INDEX_MAX_VAL 8 156 #define SHIFT_BYTE 8 157 #define FREQ_DIFF 3270000 158 #define FREQ_COEFFICIENT 3052 159 #define FREQ_UNIT 10000 160 #define SHIFT_BYTE 8 161 #define MS_OF_ACCURACY 10 162 163 #ifdef __cplusplus 164 #if __cplusplus 165 } 166 #endif /* __cplusplus */ 167 #endif /* __cplusplus */ 168 169 #endif /* PLATFORM_RTC_HI35XX_H */ 170