1 /* 2 * Copyright (c) 2020-2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef SPI_HI35XX_H 17 #define SPI_HI35XX_H 18 #include "los_vm_zone.h" 19 20 #ifdef __cplusplus 21 #if __cplusplus 22 extern "C" { 23 #endif /* __cplusplus */ 24 #endif /* __cplusplus */ 25 26 /* ********** spi reg offset define *************** */ 27 #define REG_SPI_CR0 0x00 28 #define SPI_CR0_SCR_SHIFT 8 29 #define SPI_CR0_SPH_SHIFT 7 30 #define SPI_CR0_SPO_SHIFT 6 31 #define SPI_CR0_FRF_SHIFT 4 32 #define SPI_CR0_DSS_SHIFT 0 33 #define SPI_CR0_SCR (0xff << 8) /* clkout=clk/(cpsdvsr*(scr+1)) */ 34 #define SPI_CR0_SPH (0x1 << 7) /* spi phase */ 35 #define SPI_CR0_SPO (0x1 << 6) /* spi clk polarity */ 36 #define SPI_CR0_FRF (0x3 << 4) /* frame format set */ 37 #define SPI_CR0_DSS (0xf << 0) /* data bits width */ 38 39 #define REG_SPI_CR1 0x04 40 #define SPI_CR1_WAIT_EN_SHIFT 15 41 #define SPI_CR1_WAIT_VAL_SHIFT 8 42 #define SPI_CR1_ALT_SHIFT 6 43 #define SPI_CR1_BIG_END_SHIFT 4 44 #define SPI_CR1_MS_SHIFT 2 45 #define SPI_CR1_SSE_SHIFT 1 46 #define SPI_CR1_LBN_SHIFT 0 47 #define SPI_CR1_WAIT_EN (0x1 << 15) 48 #define SPI_CR1_WAIT_VAL (0x7f << 8) 49 50 /* alt mode:spi enable csn is select; spi disable csn is cancel */ 51 #define SPI_CR1_ALT (0x1 << 6) 52 #define SPI_CR1_BIG_END (0x1 << 4) /* big end or little */ 53 #define SPI_CR1_MS (0x1 << 2) /* cntlr-device mode */ 54 #define SPI_CR1_SSE (0x1 << 1) /* spi enable set */ 55 #define SPI_CR1_LBN (0x1 << 0) /* loopback mode */ 56 57 #define REG_SPI_DR 0x08 58 59 #define REG_SPI_SR 0x0c 60 #define SPI_SR_BSY_SHIFT 4 61 #define SPI_SR_RFF_SHIFT 3 62 #define SPI_SR_RNE_SHIFT 2 63 #define SPI_SR_TNF_SHIFT 1 64 #define SPI_SR_TFE_SHIFT 0 65 #define SPI_SR_BSY (0x1 << 4) /* spi busy flag */ 66 #define SPI_SR_RFF (0x1 << 3) /* Whether to send fifo is full */ 67 #define SPI_SR_RNE (0x1 << 2) /* Whether to send fifo is no empty */ 68 #define SPI_SR_TNF (0x1 << 1) /* Whether to send fifo is no full */ 69 #define SPI_SR_TFE (0x1 << 0) /* Whether to send fifo is empty */ 70 71 #define REG_SPI_CPSR 0x10 72 #define SPI_CPSR_CPSDVSR_SHIFT 0 73 #define SPI_CPSR_CPSDVSR (0xff << 0) /* even 2~254 */ 74 75 #define REG_SPI_IMSC 0x14 76 #define SPI_ALL_IRQ_DISABLE 0x0 77 #define SPI_ALL_IRQ_ENABLE 0x5 78 #define REG_SPI_RIS 0x18 79 #define REG_SPI_MIS 0x1c 80 #define SPI_RX_INTR_MASK (0x1 << 2) 81 82 #define REG_SPI_ICR 0x20 83 #define SPI_ALL_IRQ_CLEAR 0x3 84 85 #define MAX_WAIT 5000 86 #define DEFAULT_SPEED 2000000 87 88 #define SCR_MAX 255 89 #define SCR_MIN 0 90 #define CPSDVSR_MAX 254 91 #define CPSDVSR_MIN 2 92 93 #define SPI_CS_ACTIVE 0 94 #define SPI_CS_INACTIVE 1 95 #define TWO_BYTES 2 96 #define BITS_PER_WORD_MIN 4 97 #define BITS_PER_WORD_EIGHT 8 98 #define BITS_PER_WORD_MAX 16 99 #define HDF_IO_DEVICE_ADDR IO_DEVICE_ADDR 100 101 #define SPI_DMA_CR 0x24 102 #define TX_DMA_EN_SHIFT 1 103 #define RX_DMA_EN_SHIFT 0 104 105 #define SPI_TX_FIFO_CR 0x28 106 #define TX_INT_SIZE_SHIFT 3 107 #define TX_DMA_BR_SIZE_SHIFT 0 108 #define TX_DMA_BR_SIZE_MASK 0x7 109 110 #define SPI_RX_FIFO_CR 0x2C 111 #define RX_INT_SIZE_SHIFT 3 112 #define RX_INT_SIZE_MASK 0x7 113 #define RX_DMA_BR_SIZE_SHIFT 0 114 #define RX_DMA_BR_SIZE_MASK 0x7 115 116 #ifdef __cplusplus 117 #if __cplusplus 118 } 119 #endif /* __cplusplus */ 120 #endif /* __cplusplus */ 121 #endif /* SPI_HI35XX_H */ 122