1 /* 2 * @file hi_3861_platform.h 3 * 4 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef __HI3861_PLATFORM_H__ 19 #define __HI3861_PLATFORM_H__ 20 21 /* The CPU configuration memory size is 120KB, which cannot be modified. */ 22 #define SRAM_LENGTH 0x0001E000 /* CPU SRAM 0x100000-0x11DFFF 120KB */ 23 24 /* Configure the memory start address. This value cannot be modified. */ 25 #define SRAM_START_ADDR 0x00100000 26 27 #define CONFIG_CPU_CLOCK 160000000 28 #define CONFIG_UART_CLOCK 80000000 29 30 #define HI_CHIP_ID_1131SV200 0xFF /* Refresh after Asic */ 31 32 #define CALI_PMU_32K_CLK_VAL 10 33 #define TCXO_CLK_40MHZ 40000000 34 #define TCXO_CLK_24MHZ 24000000 35 #define CONFIG_WDT_CLOCK 80000000 36 37 /* GLOBAL CONTROL REG */ 38 #define GLB_CTL_BASE 0x50000000 39 #define GLB_CTL_SYS_CTL_ID_REG (GLB_CTL_BASE + 0x0) 40 #define GLB_CTL_AON_SOFT_RST_W_REG (GLB_CTL_BASE + 0x20) 41 #define GLB_CTL_SOFT_RST_WCPU_REG (GLB_CTL_BASE + 0x24) 42 #define GLB_CTL_SOFT_GLB_RESET_CFG (GLB_CTL_BASE + 0x28) 43 #define GLB_CTL_GLB_WDT_RST_SEL_REG (GLB_CTL_BASE + 0x30) 44 #define GLB_CTL_WDT_RST_SEL_REG (GLB_CTL_BASE + 0x34) 45 #define GLB_CTL_AON_CKEN_REG (GLB_CTL_BASE + 0x40) 46 #define GLB_CTL_GLB_AON_32K_CLKEN_REG (GLB_CTL_BASE + 0x50) 47 #define GLB_CTL_A32K_DIV_REG (GLB_CTL_BASE + 0x70) 48 #define GLB_CTL_TCXO_DIV_REG (GLB_CTL_BASE + 0x74) 49 #define GLB_CTL_AON_PERP_CLKSEL_W_REG (GLB_CTL_BASE + 0x90) 50 #define GLB_CTL_RC_32K_TCXO_SEL_REG (GLB_CTL_BASE + 0x94) 51 #define GLB_CTL_AON_32K_SEL_REG (GLB_CTL_BASE + 0x98) 52 #define GLB_CTL_SYS_TICK_CFG_REG (GLB_CTL_BASE + 0xC0) 53 #define GLB_CTL_SYS_TICK_VALUE_0_REG (GLB_CTL_BASE + 0xD0) 54 #define GLB_CTL_SYS_TICK_VALUE_1_REG (GLB_CTL_BASE + 0xD4) 55 #define GLB_CTL_SYS_TICK_VALUE_2_REG (GLB_CTL_BASE + 0xD8) 56 #define GLB_CTL_SYS_TICK_VALUE_3_REG (GLB_CTL_BASE + 0xDC) 57 #define GLB_CTL_CLKMUX_STS_REG (GLB_CTL_BASE + 0x110) 58 #define GLB_CTL_DEBUG_CLKEN_REG (GLB_CTL_BASE + 0x170) 59 #define GLB_CTL_SOFT_INT_EN_REG (GLB_CTL_BASE + 0x280) 60 #define GLB_CTL_SOFT_INT_SET_REG (GLB_CTL_BASE + 0x284) 61 #define GLB_CTL_SOFT_INT_CLR_REG (GLB_CTL_BASE + 0x288) 62 #define GLB_CTL_SOFT_INT_STS_REG (GLB_CTL_BASE + 0x28C) 63 #define GLB_CTL_INT_SEL_REG (GLB_CTL_BASE + 0x290) 64 #define GLB_CTL_REFCLK_FEQ_STATUS_REG (GLB_CTL_BASE + 0x358) 65 #define GLB_CTL_EXT_TSF_CTRL_REG (GLB_CTL_BASE + 0x400) 66 #define GLB_CTL_CALI_32K_TCXO_CTL_REG (GLB_CTL_BASE + 0x800) 67 #define GLB_CTL_CALI_32K_TCXO_CNT_L_REG (GLB_CTL_BASE + 0x810) 68 #define GLB_CTL_CALI_32K_TCXO_CNT_H_REG (GLB_CTL_BASE + 0x814) 69 #define GLB_CTL_CALI_32K_TCXO_RESULT_L_REG (GLB_CTL_BASE + 0x818) 70 #define GLB_CTL_CALI_32K_TCXO_RESULT_H_REG (GLB_CTL_BASE + 0x81C) 71 #define GLB_CTL_AON_ICM_PRIORITY_REG (GLB_CTL_BASE + 0xF30) 72 #define GLB_CTL_MEM_CLK_FORCE_ON_REG (GLB_CTL_BASE + 0xF50) 73 #define GLB_CTL_MARGIN_ADJ_REG (GLB_CTL_BASE + 0xF54) 74 #define GLB_CTL_MARGIN_ADJ_AB (GLB_CTL_BASE + 0xF58) 75 #define GLB_CTL_DEFAULT_SLV_EN_REG (GLB_CTL_BASE + 0xF84) 76 #define GLB_CTL_DEFAULT_SLV_HIT_STATUS_REG (GLB_CTL_BASE + 0xF88) 77 #define GLB_CTL_DEFAULT_SLV_HIT_CLR_REG (GLB_CTL_BASE + 0xF8C) 78 79 /* CLDO CONTROL REG */ 80 #define CLDO_CTL_RB_BASE 0x40010000 81 #define CLDO_CTL_SOFT_RESET_REG (CLDO_CTL_RB_BASE + 0x20) 82 #define CLDO_CTL_WDG_RST_SEL_REG (CLDO_CTL_RB_BASE + 0x28) 83 #define CLDO_CTL_RB_CLKEN_REG (CLDO_CTL_RB_BASE + 0x30) 84 #define CLDO_CTL_CLK_SEL_REG (CLDO_CTL_RB_BASE + 0x38) 85 #define CLDO_CTL_SOFT_RESET2_REG (CLDO_CTL_RB_BASE + 0x3C) 86 #define CLDO_CTL_WDG_RST_SEL1_REG (CLDO_CTL_RB_BASE + 0x4C) 87 #define CLDO_CTL_CLKMUX_STS_REG (CLDO_CTL_RB_BASE + 0x64) 88 #define CLDO_CTL_CLK_DIV1_REG (CLDO_CTL_RB_BASE + 0x78) 89 #define CLDO_CTL_PKT_CPU_MEM_SEL (CLDO_CTL_RB_BASE + 0x100) 90 #define CLDO_CTL_UART_JTAG_CFG_REG (CLDO_CTL_RB_BASE + 0x250) 91 92 #define EFUSE_RST_BIT 9 93 #define JTAG_SWE_ENABLE (1<<3) /* [3] jtag ctrl */ 94 #define UART0_SWE_ENABLE (1<<0) /* [0] uart0 ctrl */ 95 #define UART1_SWE_ENABLE (1<<1) /* [1] uart1 ctrl */ 96 #define UART2_SWE_ENABLE (1<<2) /* [2] uart2 ctrl */ 97 98 /* PMU CMU CONTROL REG */ 99 #define PMU_CMU_CTL_BASE 0x50002000 100 #define PMU_CMU_CTL_UDSLEEP_BUTTON_CTRL_REG (PMU_CMU_CTL_BASE + 0x020) 101 #define PMU_CMU_CTL_UDSLEEP_BUTTON_RPT_REG (PMU_CMU_CTL_BASE + 0x024) 102 #define PMU_CMU_CTL_OSC_TRIM_REG (PMU_CMU_CTL_BASE + 0x028) 103 #define PMU_CMU_CTL_PMU_MAN_CLR_0_REG (PMU_CMU_CTL_BASE + 0x104) 104 #define PMU_CMU_CTL_FLASHLDO_CFG_1_REG (PMU_CMU_CTL_BASE + 0x260) 105 #define PMU_CMU_CTL_GATE_TSENSOR_VDDIO_REG (PMU_CMU_CTL_BASE + 0x350) 106 #define PMU_CMU_CTL_CMU_DBG_SEL_REG (PMU_CMU_CTL_BASE + 0x414) 107 #define PMU_CMU_CTL_CLK_480M_GT_REG (PMU_CMU_CTL_BASE + 0x420) 108 #define PMU_CMU_CTL_CLK_192M_GT_REG (PMU_CMU_CTL_BASE + 0x42C) 109 #define PMU_CMU_CTL_CLK_960M_GT_REG (PMU_CMU_CTL_BASE + 0x430) 110 #define PMU_CMU_CTL_REFDIV_REG (PMU_CMU_CTL_BASE + 0x500) 111 #define PMU_CMU_CTL_FBDIV_REG (PMU_CMU_CTL_BASE + 0x504) 112 #define PMU_CMU_CTL_FRAC_L_REG (PMU_CMU_CTL_BASE + 0x508) 113 #define PMU_CMU_CTL_FRAC_H_REG (PMU_CMU_CTL_BASE + 0x50C) 114 #define PMU_CMU_CTL_CMU_MISC_PD_REG (PMU_CMU_CTL_BASE + 0x514) 115 #define PMU_CMU_CTL_CMU_CLK_SEL_REG (PMU_CMU_CTL_BASE + 0x518) 116 #define PMU_CMU_CTL_CMU_STATUS_RAW_REG (PMU_CMU_CTL_BASE + 0x600) 117 #define PMU_CMU_CTL_SYS_STATUS_REG (PMU_CMU_CTL_BASE + 0x804) 118 #define PMU_CMU_CTL_WLAN_STA0_ALLOW_TO_SLEEP_REG (PMU_CMU_CTL_BASE + 0x900) 119 #define PMU_CMU_CTL_WLAN_STA1_ALLOW_TO_SLEEP_REG (PMU_CMU_CTL_BASE + 0x904) 120 #define PMU_CMU_CTL_WLAN_AP0_ALLOW_TO_SLEEP_REG (PMU_CMU_CTL_BASE + 0x908) 121 #define PMU_CMU_CTL_WLAN_PF_ALLOW_TO_SLEEP_REG (PMU_CMU_CTL_BASE + 0x90C) 122 #define PMU_CMU_CTL_WLAN_HOST_ALLOW_TO_SLEEP_REG (PMU_CMU_CTL_BASE + 0x910) 123 #define PMU_CMU_CTL_WLAN_SLP_EVT_EN_REG (PMU_CMU_CTL_BASE + 0x920) 124 #define PMU_CMU_CTL_WLAN_SLP_EVT_CLR_REG (PMU_CMU_CTL_BASE + 0x924) 125 #define PMU_CMU_CTL_WLAN_SLP_INT_CLR_REG (PMU_CMU_CTL_BASE + 0x934) 126 #define PMU_CMU_CTL_WLAN_WKUP_EVT_EN_REG (PMU_CMU_CTL_BASE + 0x940) 127 #define PMU_CMU_CTL_WLAN_WKUP_EVT_CLR_REG (PMU_CMU_CTL_BASE + 0x944) 128 #define PMU_CMU_CTL_WLAN_WKUP_INT_EN_REG (PMU_CMU_CTL_BASE + 0x950) 129 #define PMU_CMU_CTL_WLAN_WKUP_INT_CLR_REG (PMU_CMU_CTL_BASE + 0x954) 130 131 /* WLAN CONTROL REG */ 132 #define W_CTL_BASE_ADDR 0x40028000 133 #define W_CTL_MAC_WDT_RST_SEL_REG (W_CTL_BASE_ADDR + 0x0034) 134 #define W_CTL_PHY_WDT_RST_SEL_REG (W_CTL_BASE_ADDR + 0x0038) 135 #define W_CTL_WDT_RST_SEL_REG (W_CTL_BASE_ADDR + 0x003C) 136 #define W_CTL_CPU_MAC_CLK_DIV_REG (W_CTL_BASE_ADDR + 0x0070) 137 #define W_CTL_UART01_CKDIV_OFFSET (W_CTL_BASE_ADDR + 0x0074) 138 #define W_CTL_UART2_CKDIV_OFFSET (W_CTL_BASE_ADDR + 0x0090) 139 #define W_CTL_W_TCXO_SEL_REG (W_CTL_BASE_ADDR + 0x0118) 140 #define W_CTL_CLKMUX_STS_DIV_STS_REG (W_CTL_BASE_ADDR + 0x0130) 141 142 /* DIAG CTL REG */ 143 #define DIAG_CTL_BASE 0x40060000 144 #define DIAG_CTL_GP_REG0_REG (DIAG_CTL_BASE + 0x010) /* used to save rsa key */ 145 #define DIAG_CTL_GP_REG1_REG (DIAG_CTL_BASE + 0x014) /* used to save rsa key */ 146 #define DIAG_CTL_GP_REG2_REG (DIAG_CTL_BASE + 0x018) /* used to save ecc key */ 147 #define DIAG_CTL_GP_REG3_REG (DIAG_CTL_BASE + 0x01C) /* used to save ecc key */ 148 149 /* DEVICE REG */ 150 #define HI_WDG_REG_BASE 0x40000000 151 #define HI_GPIO_REG_BASE 0x50006000 152 #define HI_IOCFG_REG_BASE 0x5000A000 153 #define HI_EFUSE_REG_BASE 0x40078000 154 #define HI_SFC_REG_BASE 0x40800000 155 156 #define HI_UART0_REG_BASE 0x40008000 157 #define HI_UART1_REG_BASE 0x40009000 158 #define HI_UART2_REG_BASE 0x4000a000 159 160 #endif 161