1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: sdio driver implementatioin. 16 */ 17 18 #ifndef __SDIO_SLAVE_H__ 19 #define __SDIO_SLAVE_H__ 20 21 #include "hi_types_base.h" 22 23 #ifdef __cplusplus 24 #if __cplusplus 25 extern "C" { 26 #endif 27 #endif 28 29 #define HI_SDIO_BASE_ADDR 0x40340000 30 31 #define SDIO_ESW_CCCR 0x004 /* Card Common Control Registers */ 32 #define SDIO_AMDA_SYS_ADDR 0x008 33 #define SDIO_ESW_CARD_RDY 0x00C 34 #define SDIO_ESW_FUN_RDY 0x010 35 #define SDIO_INTRPT_EN 0x014 36 #define SDIO_INTRPT_STA 0x018 37 #define SDIO_SOFT_RST_VALID 0x01C 38 #define SDIO_AHB_MEM_INT_EN 0x020 39 #define SDIO_AHB_MEM_INT_STA 0x024 40 #define SDIO_GLOBAL_INT_EN 0x028 41 #define SDIO_GLOBAL_INT_STA 0x02C 42 #define SDIO_CSA_PTR 0x030 43 #define SDIO_IO_ACCESS_MODE 0x034 44 #define SDIO_UHS_SUPPORT 0x038 45 #define SDIO_CLK_DELAY_TIMER 0x03C 46 #define SDIO_POWER_CTRL 0x040 47 #define SDIO_POWER_STA 0x044 48 49 /* SDIO FN1 Registers Definition */ 50 #define SDIO_ESW_IO_OCR 0x104 51 #define SDIO_AHB_XFER_COUNT 0x10C 52 #define SDIO_XFER_COUNT 0x110 53 #define SDIO_AHB_INT_STA 0x114 54 #define SDIO_AHB_INT_EN 0x118 55 #define SDIO_ESW_FBR1 0x11C 56 #define SDIO_ESW_IOR 0x120 57 #define SDIO_HOST_MSG 0x124 58 #define SDIO_ARM_HOST 0x128 59 #define SDIO_FUN1_RD_DAT_RDY 0x12C 60 #define GPIO_FUNCTION3 3 61 #define START_TYPE_EFUSE_ADDR 1072 62 63 #define SDIO_FUN1_CREDIT_INFO_BASE 0x13c 64 #define SDIO_FUN1_EXTEND_REG_BASE 0x140 65 #define SDIO_FUN1_EXTEND_REG_LEN 64 66 67 #define SDIO_MEM_ADMA_FETCH_ADDR 0x204 68 69 /* SDIO MEM */ 70 #define SDIO_BLOCK_SIZE_REG 0x244 71 #define SDIO_ARGUMENT_REG 0x248 72 73 /* Block Size Reg */ 74 #define BLK_SIZE_MSK (hi_u32)0x00000fff 75 76 /* Argument Reg */ 77 #define BLKCNT_OR_BYTES_MSK (hi_u32)0x000001ff 78 #define CMD53_ADDR_MSK ((hi_u32)0x0000ffff << 9) 79 #define CMD53_OPCODE BIT26 80 #define CMD53_BLK_MODE BIT27 81 #define CMD53_FUN_NUM (BIT28 | BIT29 | BIT30) 82 #define CMD53_RW_FLAG BIT31 83 84 /* SDIO_INTRPT */ 85 #define AHBSOFT_RST_INT BIT0 86 #define VOLT_SWITCH_CMD_INT BIT1 87 #define CMD19_RD_STRT BIT2 88 #define CMD19_RD_TRANS_OVER BIT3 89 #define FN0_WR_START BIT4 90 #define FN0_WR_TRN_OVER BIT5 91 #define FN0_RD_START BIT6 92 #define FN0_RD_TRN_OVER BIT7 93 #define FN0_RD_TRN_ERR BIT8 94 #define FN0_ADMA_END_INT BIT9 95 #define FN0_ADMA_INT BIT10 96 #define FN0_ADMA_ERR BIT11 97 98 /* global interrupt */ 99 #define INT_FRM_SOFT_RESET BIT0 100 #define INT_FRM_MEM BIT1 101 #define INT_FRM_FN1 BIT2 102 103 /* AHB Interrupt */ 104 #define FN1_WR_OVER BIT0 105 #define FN1_RD_OVER BIT1 106 #define FN1_RD_ERROR BIT2 107 #define FN1_RST BIT3 108 #define SD_HOST_FN1_MSG_RDY BIT4 109 #define FN1_ACK_TO_ARM BIT5 110 #define FN1_SDIO_RD_START BIT6 111 #define FN1_SDIO_WR_START BIT7 112 #define FN1_ADMA_END_INT BIT8 113 #define FN1_SUSPEND BIT9 114 #define FN1_RESUME BIT10 115 #define FN1_ADMA_INT BIT11 116 #define FN1_ADMA_ERR BIT12 117 #define FN1_EN_INT BIT13 118 119 /* UHS Support */ 120 #define UHS_SUPPORT BIT0 121 #define DDR_DLY_SELECT BIT1 122 #define CARD_VOLT_ACCEPTED BIT2 123 #define SD_CLK_LINE_SWITCHED BIT3 124 #define SD_CMD_LINE_SWITCHED BIT4 125 126 #define CCCR_REVISION 3 /* 4Bit 0~3: 1.0, 1.1, 2.0, 3.0, */ 127 #define SDIO_REVISION (4 << 4) /* 4Bit 0~4: 1.0, 1.1, 1.2, 2.0, 3.0 */ 128 #define SD_REVISION (3 << 8) /* 4Bit 0~3: 1.0, 1.1, 2.0, 3.0, */ 129 #define CCCR_SCSI (0 << 12) 130 #define CCCR_SDC (1 << 13) 131 #define CCCR_SMB (1 << 14) 132 #define CCCR_SRW (0 << 15) 133 #define CCCR_SBS (1 << 16) 134 #define CCCR_S4MI (1 << 17) 135 #define CCCR_LSC (0 << 18) 136 #define CCCR_4BLS (0 << 19) 137 #define CCCR_SMPC (1 << 20) 138 #define CCCR_SHS (1 << 21) 139 #define CCCR_MEM_PRE (2 << 22) 140 141 #define SDIO_ESW_CCCR_SET (hi_u32) \ 142 (CCCR_REVISION | SDIO_REVISION | SD_REVISION| CCCR_SCSI | CCCR_SDC | CCCR_SMB | CCCR_SRW| \ 143 CCCR_SBS | CCCR_S4MI | CCCR_LSC | CCCR_4BLS| CCCR_SMPC | CCCR_SHS | CCCR_MEM_PRE) 144 145 #define SDIO_ESW_IO_OCR_SET (hi_u32)(0x00ff8000) /* Bit23~Bit8: 3.6~2.0 0.1/bit */ 146 147 /* ESW FBR1 Register */ 148 #define IO_DEVICE_CODE1 7 /* 4Bit 7:SDIO WLAN interface 149 SDIO Simplified Specification Version 3.00 Chapter 6.10 */ 150 #define FUN_CSA_SUPPORT (0 << 4) /* 1Bit */ 151 #define EXT_IO_DEVICE_CODE1 (0 << 5) /* 8Bit */ 152 #define FBR1_SPS (0 << 13) /* 1Bit Function1 supports high power */ 153 154 #define SDIO_ESW_FBR1_SET (hi_u32)(IO_DEVICE_CODE1 | FUN_CSA_SUPPORT | EXT_IO_DEVICE_CODE1 | FBR1_SPS) 155 156 #define SDIO_IO_ACCESS_SET (hi_u32)0xffffffff 157 158 #define SDIO_CLK_DELAY_SET (hi_u32)0x2f92 159 160 #define SDIO_ADMA_STEP 8 161 #define SDIO_ADMA_VALID BIT0 162 #define SDIO_ADMA_END BIT1 163 #define SDIO_ADMA_INT BIT2 164 #define SDIO_ADMA_NOP 0 165 #define SDIO_ADMA_TRAN BIT5 166 #define SDIO_ADMA_LINK (BIT5 | BIT4) 167 #define SDIO_ADMA_PARAM_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) 168 169 /* SDIO soft reset offset and bit. */ 170 #define SDIO_RESET_OFFSET 0x0020 171 #define SDIO_SOFT_RESET BIT3 172 173 #define SDIO_TRANS_BLK_SIZE 512 174 #define PADDING_BLK SDIO_TRANS_BLK_SIZE 175 #define PADDING_BYTE 4 176 #define padding(x, size) (((x) + (size) - 1) & (~ ((size) - 1))) 177 #define hisdio_align_4_or_blk(len) ((len) < HISDIO_BLOCK_SIZE ? padding((len), 4) : \ 178 padding((len), HISDIO_BLOCK_SIZE)) 179 #define hisdio_shift_check(a, b) ((a) == (((a)<<(b))>>(b))) 180 181 typedef enum { 182 MSG_FLAG_OFF = 0, 183 MSG_FLAG_ON = 1, 184 } msg_flag; 185 186 typedef struct { 187 hi_u32 reg; 188 hi_u32 value; 189 } sdio_reg_store; 190 191 enum _hcc_netbuf_queue_type_ { 192 HCC_NETBUF_NORMAL_QUEUE = 0, /* netbuf is shared with others */ 193 HCC_NETBUF_HIGH_QUEUE = 1, /* netbuf is special for high pri */ 194 HCC_NETBUF_QUEUE_BUTT 195 }; 196 197 hi_void sdio_soft_reset_valid(hi_void); 198 199 #ifdef HI_BOARD_ASIC 200 #define NON_IOT_START_TYPE 0 201 #else 202 #define NON_IOT_START_TYPE 1 203 #endif 204 205 #ifdef __cplusplus 206 #if __cplusplus 207 } 208 #endif 209 #endif 210 211 #endif /* end of sdio_slave.h */ 212