1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __SPI_H__ 17 #define __SPI_H__ 18 19 #include <hi_types_base.h> 20 #include <hi3861_platform_base.h> 21 #include <hi_spi.h> 22 #include <hi_time.h> 23 #include <hi_stdlib.h> 24 #include <hi_isr.h> 25 #include <hi_event.h> 26 #include <hi_sem.h> 27 28 /* if some print is needed :#define SPI_DEBUG */ 29 #ifdef SPI_DEBUG 30 #define spi_printf(fmt...) do { \ 31 printf("[DEBUG]"fmt); \ 32 printf("\n"); \ 33 } while (0) 34 #define spi_process_printf(fmt...) do { \ 35 printf("[PROCESS]"fmt); \ 36 printf("\n"); \ 37 } while (0) 38 #else 39 #define spi_printf(fmt, ...) 40 #define spi_process_printf(fmt, ...) 41 #endif 42 43 #define SPI_NUM 2 44 45 #define REG_SPI_CR0 0x00 46 #define REG_SPI_CR1 0x04 47 #define REG_SPI_DR 0x08 48 #define REG_SPI_SR 0x0c 49 #define REG_SPI_CPSR 0x10 50 #define REG_SPI_IMSC 0x14 51 #define REG_SPI_RIS 0x18 52 #define REG_SPI_MIS 0x1c 53 #define REG_SPI_CR 0x20 54 #define REG_SPI_DMACR 0x24 55 #define REG_SPI_TXFIFOCR 0x28 56 #define REG_SPI_RXFIFOCR 0x2c 57 58 #define MASK_SPI_SR_TFE (1<<0) 59 #define MASK_SPI_SR_TNF (1<<1) 60 #define MASK_SPI_SR_RNE (1<<2) 61 #define MASK_SPI_SR_RFF (1<<3) 62 #define MASK_SPI_SR_BSY (1<<4) 63 64 #define SPI_CR0_ST_BIT_DSS 0 65 #define SPI_CR0_ST_BIT_FRF 4 66 #define SPI_CR0_ST_BIT_SPO 6 67 #define SPI_CR0_ST_BIT_SPH 7 68 #define SPI_CR0_ST_BIT_SCR 8 69 70 #define SPI_CR0_BIT_WIDTH_DSS 4 71 #define SPI_CR0_BIT_WIDTH_FRF 2 72 #define SPI_CR0_BIT_WIDTH_SPO 1 73 #define SPI_CR0_BIT_WIDTH_SPH 1 74 #define SPI_CR0_BIT_WIDTH_SCR 8 75 76 #define SPI_CR1_ST_BIT_LBM 0 77 #define SPI_CR1_ST_BIT_SSE 1 78 #define SPI_CR1_ST_BIT_MS 2 79 #define SPI_CR1_ST_BIT_BIGEND 4 80 #define SPI_CR1_ST_BIT_WAITVAL 8 81 #define SPI_CR1_ST_BIT_WAITEN 15 82 83 #define SPI_CR1_BIT_WIDTH_LBM 1 84 #define SPI_CR1_BIT_WIDTH_SSE 1 85 #define SPI_CR1_BIT_WIDTH_MS 1 86 #define SPI_CR1_BIT_WIDTH_BIGEND 1 87 #define SPI_CR1_BIT_WIDTH_WAITVAL 7 88 #define SPI_CR1_BIT_WIDTH_WAITEN 1 89 90 #define SPI_INT_BIT_TX_FIFO_WATER_LINE (1<<3) 91 #define SPI_INT_BIT_RX_FIFO_WATER_LINE (1<<2) 92 #define SPI_INT_BIT_RX_FIFO_TIME_OUT (1<<1) 93 #define SPI_INT_BIT_RX_FIFO_OVER_FLOW (1<<0) 94 95 #define SPI_INT_BIT_RTIC (1<<1) 96 #define SPI_INT_BIT_RORIC (1<<0) 97 98 #define SPI_TX_DMAE (1<<1) 99 #define SPI_RX_DMAE (1<<0) 100 101 #define SPI_FIFO_LINE_OFFSET 3 102 #define SPI_FIFO_MAX_VAL 7 103 #define SPI_FIFO_LINE_MASK 0x7 104 105 #define SPI_UNUSE_DATA 0xFFFF 106 107 #define spi_get_transfer_size(burst) (((burst) == (DMA_BURST_MSIZE_1)) ? 1 : (1 << ((burst) + 1))) 108 109 #define MEM_TO_SPI 1 110 #define SPI_TO_MEM 2 111 112 #define SCR_MAX 255 113 #define SCR_MIN 0 114 #define CPSDVSR_MAX 254 115 #define CPSDVSR_MIN 4 116 117 #define SPI0_FIFO_LEN 256 118 #define SPI1_FIFO_LEN 64 119 #define SPI0_FIFO_THRESHOLD 128 120 #define SPI1_FIFO_THRESHOLD 32 121 122 #define SPI_HOST_TIMEOUT_US 1000000 123 #define SPI_HOST_TIMEOUT_MS 1000 124 125 #define SPI_SLAVE_TIMEOUT_US 10000000 126 127 #define SPI0_TX_FIFO_WATER_LINE 6 128 #define SPI0_RX_FIFO_WATER_LINE 6 129 #define SPI1_TX_FIFO_WATER_LINE 4 130 #define SPI1_RX_FIFO_WATER_LINE 3 131 132 #define SPI0_TX_FIFO_DMA_WLINE_64 7 133 #define SPI0_RX_FIFO_DMA_WLINE_128 6 134 #define SPI1_TX_FIFO_DMA_WLINE_16 4 135 #define SPI1_RX_FIFO_DMA_WLINE_32 4 136 137 /* 40 or 24M */ 138 #define SPI_DEFAULT_CLK 160000000 139 #define spi_max_speed(clk) ((clk) / (((SCR_MIN) + 1) * (CPSDVSR_MIN))) 140 #define spi_min_speed(clk) ((clk) / (((SCR_MAX) + 1) * (CPSDVSR_MAX))) 141 142 #define SPI_WRITE_FLAG 0x1 /* 发送数据 */ 143 #define SPI_READ_FLAG 0x2 /* 接收数据 */ 144 145 #define GPIO_00_SEL 0x604 146 #define GPIO_01_SEL 0x608 147 #define GPIO_02_SEL 0x60c 148 #define GPIO_03_SEL 0x610 149 150 #define GPIO_05_SEL 0x618 151 #define GPIO_06_SEL 0x61c 152 #define GPIO_07_SEL 0x620 153 #define GPIO_08_SEL 0x624 154 155 #define GPIO_09_SEL 0x628 156 #define GPIO_10_SEL 0x62c 157 #define GPIO_11_SEL 0x630 158 #define GPIO_12_SEL 0x634 159 160 /** 161 * SPI EVENT 162 */ 163 #define HI_EVENT_BIT_RX_DATA 0x1 164 #define HI_EVENT_BIT_TX_DATA 0x2 165 #define HI_EVENT_BIT_RX_DATA_TIME_OUT 0x4 166 #define HI_EVENT_BIT_RX_FIFO_OVER_FLOW 0x8 167 168 #define HI_EVENT_BIT_DMA_RX_DATA 0x10 169 #define HI_EVENT_BIT_DMA_RX_ERR_DATA 0x20 170 #define HI_EVENT_BIT_DMA_TX_DATA 0x40 171 #define HI_EVENT_BIT_DMA_TX_ERR_DATA 0x80 172 173 typedef enum { 174 SPI_OPT_SET_CFG = 0x1, 175 SPI_OPT_ENABLE_SPI = 0x2, 176 SPI_OPT_DISABLE_SPI = 0x4, 177 SPI_OPT_TASKED_SIGNAL = 0x8, 178 SPI_OPT_SEND_FIX_DATA = 0x10, 179 SPI_OPT_RCV_FIX_DATA = 0x20, 180 SPI_OPT_WAIT_SIGNAL = 0x40, 181 SPI_OPT_FREE_SIGNAL = 0x80, 182 } spi_opt; 183 184 /** 185 * @ingroup hct_spi 186 */ 187 typedef enum { 188 SPI_CFG_ROLE_MASTER, 189 SPI_CFG_ROLE_SLAVE, 190 } spi_cfg_role; 191 192 /** 193 * @ingroup hct_spi 194 */ 195 typedef enum { 196 SPI_DATA_WIDTH_1BYTES = 1, 197 SPI_DATA_WIDTH_2BYTES, 198 } spi_data_width; 199 200 /** 201 * @ingroup hct_spi 202 */ 203 typedef enum { 204 HI_SPI0_TX_FIFO_WATER_LINE_1, 205 HI_SPI0_TX_FIFO_WATER_LINE_4, 206 HI_SPI0_TX_FIFO_WATER_LINE_8, 207 HI_SPI0_TX_FIFO_WATER_LINE_16, 208 HI_SPI0_TX_FIFO_WATER_LINE_32, 209 HI_SPI0_TX_FIFO_WATER_LINE_64, 210 HI_SPI0_TX_FIFO_WATER_LINE_128, 211 HI_SPI0_TX_FIFO_WATER_LINE_192, 212 } hi_spi0_tx_fifo_water_line; 213 214 /** 215 * @ingroup hct_spi 216 */ 217 typedef enum { 218 HI_SPI0_RX_FIFO_WATER_LINE_255, 219 HI_SPI0_RX_FIFO_WATER_LINE_252, 220 HI_SPI0_RX_FIFO_WATER_LINE_248, 221 HI_SPI0_RX_FIFO_WATER_LINE_240, 222 HI_SPI0_RX_FIFO_WATER_LINE_224, 223 HI_SPI0_RX_FIFO_WATER_LINE_192, 224 HI_SPI0_RX_FIFO_WATER_LINE_128, 225 HI_SPI0_RX_FIFO_WATER_LINE_32, 226 } hi_spi0_rx_fifo_water_line; 227 /** 228 * @ingroup hct_spi 229 */ 230 typedef enum { 231 HI_SPI1_TX_FIFO_WATER_LINE_1, 232 HI_SPI1_TX_FIFO_WATER_LINE_4, 233 HI_SPI1_TX_FIFO_WATER_LINE_8, 234 HI_SPI1_TX_FIFO_WATER_LINE_16, 235 HI_SPI1_TX_FIFO_WATER_LINE_32, 236 HI_SPI1_TX_FIFO_WATER_LINE_48, 237 HI_SPI1_TX_FIFO_WATER_LINE_56, 238 HI_SPI1_TX_FIFO_WATER_LINE_64, 239 } hi_spi1_tx_fifo_water_line; 240 /** 241 * @ingroup hct_spi 242 */ 243 typedef enum { 244 HI_SPI1_RX_FIFO_WATER_LINE_65, 245 HI_SPI1_RX_FIFO_WATER_LINE_62, 246 HI_SPI1_RX_FIFO_WATER_LINE_48, 247 HI_SPI1_RX_FIFO_WATER_LINE_32, 248 HI_SPI1_RX_FIFO_WATER_LINE_16, 249 HI_SPI1_RX_FIFO_WATER_LINE_8, 250 HI_SPI1_RX_FIFO_WATER_LINE_4, 251 HI_SPI1_RX_FIFO_WATER_LINE_1, 252 } hi_spi1_rx_fifo_water_line; 253 254 typedef struct { 255 hi_u16 cr0; 256 hi_u16 cr1; 257 hi_u16 cpsdvsr; 258 } spi_inner_cfg; 259 260 typedef struct { 261 hi_u16 data_width : 4; 262 hi_u16 fram_mode : 2; 263 hi_u16 cpol : 1; 264 hi_u16 cpha : 1; 265 hi_u16 scr : 8; 266 hi_u16 loop_back : 1; 267 hi_u16 reserver_1 : 1; 268 hi_u16 is_slave : 1; 269 hi_u16 reserver_2 : 1; 270 hi_u16 endian : 1; 271 hi_u16 reserver_3 : 11; 272 hi_u16 cpsdvsr; 273 hi_u16 rx_fifo_line; 274 hi_u16 tx_fifo_line; 275 hi_u16 rx_fifo_dma_line; 276 hi_u16 tx_fifo_dma_line; 277 hi_u16 pad; 278 } spi_hw_cfg; 279 280 typedef struct { 281 hi_u32 time_out_ms; 282 hi_u32 trans_opt; 283 } spi_trans_attr; 284 285 typedef struct { 286 hi_pvoid buf; 287 volatile hi_u32 cur_pos; 288 volatile hi_u32 cur_cnt; 289 } spi_buf; 290 291 typedef struct { 292 hi_u32 reg_base; 293 hi_u32 irq_num; 294 hi_u32 sem_id; 295 hi_u32 event_id; 296 hi_bool use_dma; 297 hi_bool use_irq; 298 volatile hi_bool transferring; 299 volatile hi_bool disable_later; 300 hi_spi_usr_func prepare_func; 301 hi_spi_usr_func restore_func; 302 spi_hw_cfg spi_cfg; 303 hi_u32 single_len; 304 hi_u32 trans_len; 305 spi_buf tx_buf; 306 spi_buf rx_buf; 307 } spi_ctrl; 308 309 HI_EXTERN spi_ctrl *g_spi_ctrl[SPI_NUM]; 310 311 hi_void spi_isr(spi_ctrl *spi_dev_ctrl); 312 hi_void spi_isr_enable(hi_u32 reg_base, hi_u16 enable_bits); 313 hi_void spi_isr_disable(hi_u32 reg_base, hi_u16 disable_bits); 314 hi_u32 spi_trans_prepare(spi_ctrl *spi_hw_ctrl, spi_trans_attr *trans_attr); 315 hi_void spi_trans_restore(spi_ctrl *spi_hw_ctrl, const spi_trans_attr *trans_attr); 316 hi_u32 spi_transfer_8bits_block(const spi_ctrl *spi_hw_ctrl, hi_u32 options); 317 hi_u32 spi_transfer_16bits_block(const spi_ctrl *spi_hw_ctrl, hi_u32 options); 318 hi_void spi_set_fifo_line(const spi_ctrl *spi_hw_ctrl); 319 hi_u32 spi_config(const spi_ctrl *spi_hw_ctrl); 320 hi_void spi_reset(const spi_ctrl *spi_hw_ctrl); 321 hi_void spi_disable(spi_ctrl *ctrl); 322 hi_void spi_flush_fifo(hi_u32 reg_base); 323 324 hi_void spi_isr_clear_cr(hi_u32 reg_base, hi_u16 clear_bit); 325 #ifdef CONFIG_SPI_DMA_SUPPORT 326 hi_u32 spi_hd_dma_read_fifo(spi_ctrl *spi_dev_ctrl, hi_u32 timeout_ms); 327 hi_u32 spi_hd_dma_write_fifo(spi_ctrl *spi_dev_ctrl, hi_u32 timeout_ms); 328 hi_void spi_set_dma_fifo_line(const spi_ctrl *spi_hw_ctrl); 329 hi_void spi_dma_enable(hi_u32 reg_base, hi_u16 enable_bits); 330 hi_void spi_dma_disable(hi_u32 reg_base, hi_u16 disable_bits); 331 #endif 332 333 #endif 334