1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __SERIAL_DW_H__ 17 #define __SERIAL_DW_H__ 18 19 #include <hi3861_platform.h> 20 21 /** 22 * @ingroup hct_io 23 */ 24 typedef enum { 25 UART_0 = 0, /**< uart0 */ 26 UART_1 = 1, /**< uart1 */ 27 UART_2 = 2, /**< uart2 */ 28 } hi_uart; 29 30 /** 31 * @ingroup hct_io 32 * 串口参数结构体 33 */ 34 typedef struct { 35 hi_u32 baudrate; /* ex:115200 */ 36 hi_u8 databit; /* 5; 6; 7; 8 */ 37 hi_u8 stopbit; /* 1:stop_bit 1; 2: stop_bit 2. */ 38 hi_u8 parity; /* 0: None; 1:Odd; 2:Even */ 39 hi_u8 flow_ctrl; /* 0: None; 1:rts&&cts. 2:only rts; 3:only cts */ 40 hi_u8 fifoline_tx_int; /* 0: tx FIFO≤1/8full; 1:tx FIFO≤1/4full; 2:tx FIFO≤1/2full; 41 3:tx FIFO≤3/4full; 4:tx FIFO≤7/8full */ 42 hi_u8 fifoline_rx_int; /* 0: rx FIFO≥1/8full; 1:rx FIFO≥1/4full; 2:rx FIFO≥1/2full; 43 3:rx FIFO≥3/4full; 4:rx FIFO≥7/8full */ 44 hi_u8 fifoline_rts; /* 0:rx FIFO≥1/8full; 1:rx FIFO≥1/4full; 2:rx FIFO≥1/2full; 45 3:rx FIFO≥3/4full; 4:rx FIFO≥7/8full */ 46 hi_u8 pad; 47 } uart_param_stru; 48 49 typedef struct { 50 hi_u32 baudrate; 51 hi_u16 ibrd; 52 hi_u16 fbrd; 53 } hi_uart_brd; 54 55 hi_u32 serial_init(hi_uart uart_num, uart_param_stru default_uart_param); 56 hi_u32 change_uart(hi_uart uart_num); 57 hi_void serial_putc(const hi_char c); 58 hi_void serial_puts(const hi_char *s); 59 hi_void serial_put_buf(const hi_char *buffer, hi_s32 length); 60 hi_void serial_puthex(hi_u32 h, hi_u8 print_all); 61 hi_void serial_put_msg0(const hi_char *s); 62 hi_void serial_put_msg1(const hi_char *s, hi_u32 h); 63 hi_void serial_put_msg2(const hi_char *s, hi_u32 h1, hi_u32 h2); 64 hi_void serial_put_msg4(const hi_char *s, hi_u32 h1, hi_u32 h2, hi_u32 h3, hi_u32 h4); 65 hi_void dw_putc(hi_char c); 66 hi_s32 serial_getc(hi_void); 67 hi_s32 serial_tstc(hi_void); 68 hi_u8 dw_getc(hi_void); 69 hi_s32 dw_tstc(hi_void); 70 hi_u32 set_uart_param(hi_u32 base_addr, uart_param_stru uart_param); 71 72 /* UART register OFFSET */ 73 #define UART_DR 0x0 74 #define UART_RSR_ECR 0x04 75 #define UART_FR 0x18 76 #define UART_ILPR 0x20 77 #define UART_IBRD 0x24 78 #define UART_FBRD 0x28 79 #define UART_LCR_H 0x2C 80 #define UART_CR 0x30 81 #define UART_IFLS 0x34 82 #define UART_IMSC 0x38 83 #define UART_RIS 0x3C 84 #define UART_MIS 0x40 85 #define UART_ICR 0x44 86 #define UART_DMACR 0x48 87 88 #define UARTFR_TXFE_MASK 0x80 89 #define UARTFR_RXFF_MASK 0x40 90 #define UARTFR_TXFF_MASK 0x20 91 #define UARTFR_RXFE_MASK 0x10 92 #define UARTFR_BUSY_MASK 0x04 93 #define UARTDR_DATA_MASK 0xFF 94 95 #define UARTIFS_CFG 0x10A /* FIFO water mark:Rx 16 Tx 32 RTS 56 */ 96 #define UART_DMA_ENABLE 0X03 97 #define UART_DMA_DISABLE 0X04 98 #define UARTICR_CFG 0x7FF /* Clear up all uart interrupt */ 99 100 #define UARTIMSC_CFG 0x0 /* Disable all uart interrupt */ 101 #define UARTIMSC_CFG_INT 0x50 /* enable rx time out interrupt */ 102 103 /* UART register OFFSET */ 104 #define UART_LCH_H 0x2C 105 106 #define UART_INTMASK_OVERRUN (1 << 10) 107 #define UART_INTMASK_BREAKERR (1 << 9) 108 #define UART_INTMASK_PARERR (1 << 8) 109 #define UART_INTMASK_FRAMINGERR (1 << 7) 110 #define UART_INTMASK_RECTIMEOUT (1 << 6) 111 #define UART_INTMASK_TX (1 << 5) 112 #define UART_INTMASK_RX (1 << 4) 113 114 #define UARTLCR_H_CFG 0x60 /* 8bit, no parity, FIFO disable */ 115 #define UARTLCR_H_CFG_ODD 0x72 /* 8bit, odd parity,FIFO enable */ 116 #define UARTLCR_H_CFG_FIFO 0x70 /* 8bit, no parity, FIFO enable */ 117 #define UARTCR_CFG 0x301 /* UART tx enable, rx enable, uart enable */ 118 #define UARTCR_CFG_FLOWENABLE 0xC301 /* UART tx enable, rx enable, uart enable, flow control enable */ 119 120 #define UART_FIFO_TX_SIZE 64 121 122 typedef enum { 123 HI_UART_BRD_IDX_1200 = 0, 124 HI_UART_BRD_IDX_2400 = 1, 125 HI_UART_BRD_IDX_9600 = 2, 126 HI_UART_BRD_IDX_19200 = 3, 127 HI_UART_BRD_IDX_115200 = 4, 128 HI_UART_BRD_IDX_230400 = 5, 129 HI_UART_BRD_IDX_460800 = 6, 130 HI_UART_BRD_IDX_921600 = 7, 131 HI_UART_BRD_IDX_1000000 = 8, 132 HI_UART_BRD_IDX_1024000 = 9, 133 HI_UART_BRD_IDX_1500000 = 10, 134 HI_UART_BRD_IDX_1536000 = 11, 135 HI_UART_BRD_IDX_2000000 = 12, 136 HI_UART_BRD_IDX_2048000 = 13, 137 HI_UART_BRD_IDX_2252800 = 14, 138 HI_UART_BRD_IDX_2304000 = 15, 139 HI_UART_BRD_IDX_2500000 = 16, 140 HI_UART_BRD_IDX_2560000 = 17, 141 HI_UART_BRD_IDX_3000000 = 18, 142 HI_UART_BRD_IDX_3072000 = 19, 143 HI_UART_BRD_IDX_3500000 = 20, 144 HI_UART_BRD_IDX_3584000 = 21, 145 HI_UART_BRD_IDX_3840000 = 22, 146 HI_UART_BRD_IDX_4000000 = 23, 147 HI_UART_BRD_IDX_4096000 = 24, 148 HI_UART_BRD_IDX_4500000 = 25, 149 HI_UART_BRD_IDX_4608000 = 26, 150 HI_UART_BRD_IDX_5000000 = 27, 151 HI_UART_BRD_IDX_6000000 = 28, 152 HI_UART_BRD_IDX_MAX, 153 } hi_uart_brd_idx_e; 154 155 typedef enum { 156 HI_UART_BRD_1200 = 1200, 157 HI_UART_BRD_2400 = 2400, 158 HI_UART_BRD_9600 = 9600, 159 HI_UART_BRD_19200 = 19200, 160 HI_UART_BRD_115200 = 115200, 161 HI_UART_BRD_230400 = 230400, 162 HI_UART_BRD_460800 = 460800, 163 HI_UART_BRD_921600 = 921600, 164 HI_UART_BRD_1000000 = 1000000, 165 HI_UART_BRD_1024000 = 1024000, 166 HI_UART_BRD_1500000 = 1500000, 167 HI_UART_BRD_1536000 = 1536000, 168 HI_UART_BRD_2000000 = 2000000, 169 HI_UART_BRD_2048000 = 2048000, 170 HI_UART_BRD_2252800 = 2252800, 171 HI_UART_BRD_2304000 = 2304000, 172 HI_UART_BRD_2500000 = 2500000, 173 HI_UART_BRD_2560000 = 2560000, 174 HI_UART_BRD_3000000 = 3000000, 175 HI_UART_BRD_3072000 = 3072000, 176 HI_UART_BRD_3500000 = 3500000, 177 HI_UART_BRD_3584000 = 3584000, 178 HI_UART_BRD_3840000 = 3840000, 179 HI_UART_BRD_4000000 = 4000000, 180 HI_UART_BRD_4096000 = 4096000, 181 HI_UART_BRD_4500000 = 4500000, 182 HI_UART_BRD_4608000 = 4608000, 183 HI_UART_BRD_5000000 = 5000000, 184 HI_UART_BRD_6000000 = 6000000, 185 } hi_uart_baudrate_e; 186 187 #endif 188